1/* 2 * Copyright (c) 2010 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Copyright (c) 2004-2005 The Regents of The University of Michigan 15 * All rights reserved. 16 * 17 * Redistribution and use in source and binary forms, with or without 18 * modification, are permitted provided that the following conditions are 19 * met: redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer; 21 * redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution; 24 * neither the name of the copyright holders nor the names of its 25 * contributors may be used to endorse or promote products derived from 26 * this software without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 39 * 40 * Authors: Kevin Lim 41 * Korey Sewell 42 */ 43 44#include "arch/generic/debugfaults.hh" 45#include "arch/locked_mem.hh" 46#include "base/str.hh" 47#include "config/the_isa.hh" 48#include "config/use_checker.hh" 49#include "cpu/o3/lsq.hh" 50#include "cpu/o3/lsq_unit.hh" 51#include "debug/Activity.hh" 52#include "debug/IEW.hh" 53#include "debug/LSQUnit.hh" 54#include "mem/packet.hh" 55#include "mem/request.hh" 56 57#if USE_CHECKER 58#include "cpu/checker/cpu.hh" 59#endif 60 61template<class Impl> 62LSQUnit<Impl>::WritebackEvent::WritebackEvent(DynInstPtr &_inst, PacketPtr _pkt, 63 LSQUnit *lsq_ptr) 64 : Event(Default_Pri, AutoDelete), 65 inst(_inst), pkt(_pkt), lsqPtr(lsq_ptr) 66{ 67} 68 69template<class Impl> 70void 71LSQUnit<Impl>::WritebackEvent::process() 72{ 73 if (!lsqPtr->isSwitchedOut()) { 74 lsqPtr->writeback(inst, pkt); 75 } 76 77 if (pkt->senderState) 78 delete pkt->senderState; 79 80 delete pkt->req; 81 delete pkt; 82} 83 84template<class Impl> 85const char * 86LSQUnit<Impl>::WritebackEvent::description() const 87{ 88 return "Store writeback"; 89} 90 91template<class Impl> 92void 93LSQUnit<Impl>::completeDataAccess(PacketPtr pkt) 94{ 95 LSQSenderState *state = dynamic_cast<LSQSenderState *>(pkt->senderState); 96 DynInstPtr inst = state->inst; 97 DPRINTF(IEW, "Writeback event [sn:%lli].\n", inst->seqNum); 98 DPRINTF(Activity, "Activity: Writeback event [sn:%lli].\n", inst->seqNum); 99 100 //iewStage->ldstQueue.removeMSHR(inst->threadNumber,inst->seqNum); 101 102 assert(!pkt->wasNacked()); 103 104 // If this is a split access, wait until all packets are received. 105 if (TheISA::HasUnalignedMemAcc && !state->complete()) { 106 delete pkt->req; 107 delete pkt; 108 return; 109 } 110 111 if (isSwitchedOut() || inst->isSquashed()) { 112 iewStage->decrWb(inst->seqNum); 113 } else { 114 if (!state->noWB) { 115 if (!TheISA::HasUnalignedMemAcc || !state->isSplit || 116 !state->isLoad) { 117 writeback(inst, pkt); 118 } else { 119 writeback(inst, state->mainPkt); 120 } 121 } 122 123 if (inst->isStore()) { 124 completeStore(state->idx); 125 } 126 } 127 128 if (TheISA::HasUnalignedMemAcc && state->isSplit && state->isLoad) { 129 delete state->mainPkt->req; 130 delete state->mainPkt; 131 } 132 delete state; 133 delete pkt->req; 134 delete pkt; 135} 136 137template <class Impl> 138LSQUnit<Impl>::LSQUnit() 139 : loads(0), stores(0), storesToWB(0), cacheBlockMask(0), stalled(false), 140 isStoreBlocked(false), isLoadBlocked(false),
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141 loadBlockedHandled(false), hasPendingPkt(false)
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141 loadBlockedHandled(false), storeInFlight(false), hasPendingPkt(false) |
142{ 143} 144 145template<class Impl> 146void 147LSQUnit<Impl>::init(O3CPU *cpu_ptr, IEW *iew_ptr, DerivO3CPUParams *params, 148 LSQ *lsq_ptr, unsigned maxLQEntries, unsigned maxSQEntries, 149 unsigned id) 150{ 151 cpu = cpu_ptr; 152 iewStage = iew_ptr; 153 154 DPRINTF(LSQUnit, "Creating LSQUnit%i object.\n",id); 155 156 switchedOut = false; 157 158 cacheBlockMask = 0; 159 160 lsq = lsq_ptr; 161 162 lsqID = id; 163 164 // Add 1 for the sentinel entry (they are circular queues). 165 LQEntries = maxLQEntries + 1; 166 SQEntries = maxSQEntries + 1; 167 168 loadQueue.resize(LQEntries); 169 storeQueue.resize(SQEntries); 170 171 depCheckShift = params->LSQDepCheckShift; 172 checkLoads = params->LSQCheckLoads; 173 174 loadHead = loadTail = 0; 175 176 storeHead = storeWBIdx = storeTail = 0; 177 178 usedPorts = 0; 179 cachePorts = params->cachePorts; 180 181 retryPkt = NULL; 182 memDepViolator = NULL; 183 184 blockedLoadSeqNum = 0;
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185 needsTSO = params->needsTSO; |
186} 187 188template<class Impl> 189std::string 190LSQUnit<Impl>::name() const 191{ 192 if (Impl::MaxThreads == 1) { 193 return iewStage->name() + ".lsq"; 194 } else { 195 return iewStage->name() + ".lsq.thread" + to_string(lsqID); 196 } 197} 198 199template<class Impl> 200void 201LSQUnit<Impl>::regStats() 202{ 203 lsqForwLoads 204 .name(name() + ".forwLoads") 205 .desc("Number of loads that had data forwarded from stores"); 206 207 invAddrLoads 208 .name(name() + ".invAddrLoads") 209 .desc("Number of loads ignored due to an invalid address"); 210 211 lsqSquashedLoads 212 .name(name() + ".squashedLoads") 213 .desc("Number of loads squashed"); 214 215 lsqIgnoredResponses 216 .name(name() + ".ignoredResponses") 217 .desc("Number of memory responses ignored because the instruction is squashed"); 218 219 lsqMemOrderViolation 220 .name(name() + ".memOrderViolation") 221 .desc("Number of memory ordering violations"); 222 223 lsqSquashedStores 224 .name(name() + ".squashedStores") 225 .desc("Number of stores squashed"); 226 227 invAddrSwpfs 228 .name(name() + ".invAddrSwpfs") 229 .desc("Number of software prefetches ignored due to an invalid address"); 230 231 lsqBlockedLoads 232 .name(name() + ".blockedLoads") 233 .desc("Number of blocked loads due to partial load-store forwarding"); 234 235 lsqRescheduledLoads 236 .name(name() + ".rescheduledLoads") 237 .desc("Number of loads that were rescheduled"); 238 239 lsqCacheBlocked 240 .name(name() + ".cacheBlocked") 241 .desc("Number of times an access to memory failed due to the cache being blocked"); 242} 243 244template<class Impl> 245void 246LSQUnit<Impl>::setDcachePort(Port *dcache_port) 247{ 248 dcachePort = dcache_port; 249 250#if USE_CHECKER 251 if (cpu->checker) { 252 cpu->checker->setDcachePort(dcachePort); 253 } 254#endif 255} 256 257template<class Impl> 258void 259LSQUnit<Impl>::clearLQ() 260{ 261 loadQueue.clear(); 262} 263 264template<class Impl> 265void 266LSQUnit<Impl>::clearSQ() 267{ 268 storeQueue.clear(); 269} 270 271template<class Impl> 272void 273LSQUnit<Impl>::switchOut() 274{ 275 switchedOut = true; 276 for (int i = 0; i < loadQueue.size(); ++i) { 277 assert(!loadQueue[i]); 278 loadQueue[i] = NULL; 279 } 280 281 assert(storesToWB == 0); 282} 283 284template<class Impl> 285void 286LSQUnit<Impl>::takeOverFrom() 287{ 288 switchedOut = false; 289 loads = stores = storesToWB = 0; 290 291 loadHead = loadTail = 0; 292 293 storeHead = storeWBIdx = storeTail = 0; 294 295 usedPorts = 0; 296 297 memDepViolator = NULL; 298 299 blockedLoadSeqNum = 0; 300 301 stalled = false; 302 isLoadBlocked = false; 303 loadBlockedHandled = false; 304 305 // Just incase the memory system changed out from under us 306 cacheBlockMask = 0; 307} 308 309template<class Impl> 310void 311LSQUnit<Impl>::resizeLQ(unsigned size) 312{ 313 unsigned size_plus_sentinel = size + 1; 314 assert(size_plus_sentinel >= LQEntries); 315 316 if (size_plus_sentinel > LQEntries) { 317 while (size_plus_sentinel > loadQueue.size()) { 318 DynInstPtr dummy; 319 loadQueue.push_back(dummy); 320 LQEntries++; 321 } 322 } else { 323 LQEntries = size_plus_sentinel; 324 } 325 326} 327 328template<class Impl> 329void 330LSQUnit<Impl>::resizeSQ(unsigned size) 331{ 332 unsigned size_plus_sentinel = size + 1; 333 if (size_plus_sentinel > SQEntries) { 334 while (size_plus_sentinel > storeQueue.size()) { 335 SQEntry dummy; 336 storeQueue.push_back(dummy); 337 SQEntries++; 338 } 339 } else { 340 SQEntries = size_plus_sentinel; 341 } 342} 343 344template <class Impl> 345void 346LSQUnit<Impl>::insert(DynInstPtr &inst) 347{ 348 assert(inst->isMemRef()); 349 350 assert(inst->isLoad() || inst->isStore()); 351 352 if (inst->isLoad()) { 353 insertLoad(inst); 354 } else { 355 insertStore(inst); 356 } 357 358 inst->setInLSQ(); 359} 360 361template <class Impl> 362void 363LSQUnit<Impl>::insertLoad(DynInstPtr &load_inst) 364{ 365 assert((loadTail + 1) % LQEntries != loadHead); 366 assert(loads < LQEntries); 367 368 DPRINTF(LSQUnit, "Inserting load PC %s, idx:%i [sn:%lli]\n", 369 load_inst->pcState(), loadTail, load_inst->seqNum); 370 371 load_inst->lqIdx = loadTail; 372 373 if (stores == 0) { 374 load_inst->sqIdx = -1; 375 } else { 376 load_inst->sqIdx = storeTail; 377 } 378 379 loadQueue[loadTail] = load_inst; 380 381 incrLdIdx(loadTail); 382 383 ++loads; 384} 385 386template <class Impl> 387void 388LSQUnit<Impl>::insertStore(DynInstPtr &store_inst) 389{ 390 // Make sure it is not full before inserting an instruction. 391 assert((storeTail + 1) % SQEntries != storeHead); 392 assert(stores < SQEntries); 393 394 DPRINTF(LSQUnit, "Inserting store PC %s, idx:%i [sn:%lli]\n", 395 store_inst->pcState(), storeTail, store_inst->seqNum); 396 397 store_inst->sqIdx = storeTail; 398 store_inst->lqIdx = loadTail; 399 400 storeQueue[storeTail] = SQEntry(store_inst); 401 402 incrStIdx(storeTail); 403 404 ++stores; 405} 406 407template <class Impl> 408typename Impl::DynInstPtr 409LSQUnit<Impl>::getMemDepViolator() 410{ 411 DynInstPtr temp = memDepViolator; 412 413 memDepViolator = NULL; 414 415 return temp; 416} 417 418template <class Impl> 419unsigned 420LSQUnit<Impl>::numFreeEntries() 421{ 422 unsigned free_lq_entries = LQEntries - loads; 423 unsigned free_sq_entries = SQEntries - stores; 424 425 // Both the LQ and SQ entries have an extra dummy entry to differentiate 426 // empty/full conditions. Subtract 1 from the free entries. 427 if (free_lq_entries < free_sq_entries) { 428 return free_lq_entries - 1; 429 } else { 430 return free_sq_entries - 1; 431 } 432} 433 434template <class Impl> 435int 436LSQUnit<Impl>::numLoadsReady() 437{ 438 int load_idx = loadHead; 439 int retval = 0; 440 441 while (load_idx != loadTail) { 442 assert(loadQueue[load_idx]); 443 444 if (loadQueue[load_idx]->readyToIssue()) { 445 ++retval; 446 } 447 } 448 449 return retval; 450} 451 452template <class Impl> 453void 454LSQUnit<Impl>::checkSnoop(PacketPtr pkt) 455{ 456 int load_idx = loadHead; 457 458 if (!cacheBlockMask) { 459 assert(dcachePort); 460 Addr bs = dcachePort->peerBlockSize(); 461 462 // Make sure we actually got a size 463 assert(bs != 0); 464 465 cacheBlockMask = ~(bs - 1); 466 } 467 468 // If this is the only load in the LSQ we don't care 469 if (load_idx == loadTail) 470 return; 471 incrLdIdx(load_idx); 472 473 DPRINTF(LSQUnit, "Got snoop for address %#x\n", pkt->getAddr()); 474 Addr invalidate_addr = pkt->getAddr() & cacheBlockMask; 475 while (load_idx != loadTail) { 476 DynInstPtr ld_inst = loadQueue[load_idx]; 477 478 if (!ld_inst->effAddrValid || ld_inst->uncacheable()) { 479 incrLdIdx(load_idx); 480 continue; 481 } 482 483 Addr load_addr = ld_inst->physEffAddr & cacheBlockMask; 484 DPRINTF(LSQUnit, "-- inst [sn:%lli] load_addr: %#x to pktAddr:%#x\n", 485 ld_inst->seqNum, load_addr, invalidate_addr); 486 487 if (load_addr == invalidate_addr) { 488 if (ld_inst->possibleLoadViolation) { 489 DPRINTF(LSQUnit, "Conflicting load at addr %#x [sn:%lli]\n", 490 ld_inst->physEffAddr, pkt->getAddr(), ld_inst->seqNum); 491 492 // Mark the load for re-execution 493 ld_inst->fault = new ReExec; 494 } else { 495 // If a older load checks this and it's true 496 // then we might have missed the snoop 497 // in which case we need to invalidate to be sure 498 ld_inst->hitExternalSnoop = true; 499 } 500 } 501 incrLdIdx(load_idx); 502 } 503 return; 504} 505 506template <class Impl> 507Fault 508LSQUnit<Impl>::checkViolations(int load_idx, DynInstPtr &inst) 509{ 510 Addr inst_eff_addr1 = inst->effAddr >> depCheckShift; 511 Addr inst_eff_addr2 = (inst->effAddr + inst->effSize - 1) >> depCheckShift; 512 513 /** @todo in theory you only need to check an instruction that has executed 514 * however, there isn't a good way in the pipeline at the moment to check 515 * all instructions that will execute before the store writes back. Thus, 516 * like the implementation that came before it, we're overly conservative. 517 */ 518 while (load_idx != loadTail) { 519 DynInstPtr ld_inst = loadQueue[load_idx]; 520 if (!ld_inst->effAddrValid || ld_inst->uncacheable()) { 521 incrLdIdx(load_idx); 522 continue; 523 } 524 525 Addr ld_eff_addr1 = ld_inst->effAddr >> depCheckShift; 526 Addr ld_eff_addr2 = 527 (ld_inst->effAddr + ld_inst->effSize - 1) >> depCheckShift; 528 529 if (inst_eff_addr2 >= ld_eff_addr1 && inst_eff_addr1 <= ld_eff_addr2) { 530 if (inst->isLoad()) { 531 // If this load is to the same block as an external snoop 532 // invalidate that we've observed then the load needs to be 533 // squashed as it could have newer data 534 if (ld_inst->hitExternalSnoop) { 535 if (!memDepViolator || 536 ld_inst->seqNum < memDepViolator->seqNum) { 537 DPRINTF(LSQUnit, "Detected fault with inst [sn:%lli] " 538 "and [sn:%lli] at address %#x\n", 539 inst->seqNum, ld_inst->seqNum, ld_eff_addr1); 540 memDepViolator = ld_inst; 541 542 ++lsqMemOrderViolation; 543 544 return new GenericISA::M5PanicFault( 545 "Detected fault with inst [sn:%lli] and " 546 "[sn:%lli] at address %#x\n", 547 inst->seqNum, ld_inst->seqNum, ld_eff_addr1); 548 } 549 } 550 551 // Otherwise, mark the load has a possible load violation 552 // and if we see a snoop before it's commited, we need to squash 553 ld_inst->possibleLoadViolation = true; 554 DPRINTF(LSQUnit, "Found possible load violaiton at addr: %#x" 555 " between instructions [sn:%lli] and [sn:%lli]\n", 556 inst_eff_addr1, inst->seqNum, ld_inst->seqNum); 557 } else { 558 // A load/store incorrectly passed this store. 559 // Check if we already have a violator, or if it's newer 560 // squash and refetch. 561 if (memDepViolator && ld_inst->seqNum > memDepViolator->seqNum) 562 break; 563 564 DPRINTF(LSQUnit, "Detected fault with inst [sn:%lli] and " 565 "[sn:%lli] at address %#x\n", 566 inst->seqNum, ld_inst->seqNum, ld_eff_addr1); 567 memDepViolator = ld_inst; 568 569 ++lsqMemOrderViolation; 570 571 return new GenericISA::M5PanicFault("Detected fault with " 572 "inst [sn:%lli] and [sn:%lli] at address %#x\n", 573 inst->seqNum, ld_inst->seqNum, ld_eff_addr1); 574 } 575 } 576 577 incrLdIdx(load_idx); 578 } 579 return NoFault; 580} 581 582 583 584 585template <class Impl> 586Fault 587LSQUnit<Impl>::executeLoad(DynInstPtr &inst) 588{ 589 using namespace TheISA; 590 // Execute a specific load. 591 Fault load_fault = NoFault; 592 593 DPRINTF(LSQUnit, "Executing load PC %s, [sn:%lli]\n", 594 inst->pcState(), inst->seqNum); 595 596 assert(!inst->isSquashed()); 597 598 load_fault = inst->initiateAcc(); 599 600 if (inst->isTranslationDelayed() && 601 load_fault == NoFault) 602 return load_fault; 603 604 // If the instruction faulted or predicated false, then we need to send it 605 // along to commit without the instruction completing. 606 if (load_fault != NoFault || inst->readPredicate() == false) { 607 // Send this instruction to commit, also make sure iew stage 608 // realizes there is activity. 609 // Mark it as executed unless it is an uncached load that 610 // needs to hit the head of commit. 611 if (inst->readPredicate() == false) 612 inst->forwardOldRegs(); 613 DPRINTF(LSQUnit, "Load [sn:%lli] not executed from %s\n", 614 inst->seqNum, 615 (load_fault != NoFault ? "fault" : "predication")); 616 if (!(inst->hasRequest() && inst->uncacheable()) || 617 inst->isAtCommit()) { 618 inst->setExecuted(); 619 } 620 iewStage->instToCommit(inst); 621 iewStage->activityThisCycle(); 622 } else if (!loadBlocked()) { 623 assert(inst->effAddrValid); 624 int load_idx = inst->lqIdx; 625 incrLdIdx(load_idx); 626 627 if (checkLoads) 628 return checkViolations(load_idx, inst); 629 } 630 631 return load_fault; 632} 633 634template <class Impl> 635Fault 636LSQUnit<Impl>::executeStore(DynInstPtr &store_inst) 637{ 638 using namespace TheISA; 639 // Make sure that a store exists. 640 assert(stores != 0); 641 642 int store_idx = store_inst->sqIdx; 643 644 DPRINTF(LSQUnit, "Executing store PC %s [sn:%lli]\n", 645 store_inst->pcState(), store_inst->seqNum); 646 647 assert(!store_inst->isSquashed()); 648 649 // Check the recently completed loads to see if any match this store's 650 // address. If so, then we have a memory ordering violation. 651 int load_idx = store_inst->lqIdx; 652 653 Fault store_fault = store_inst->initiateAcc(); 654 655 if (store_inst->isTranslationDelayed() && 656 store_fault == NoFault) 657 return store_fault; 658 659 if (store_inst->readPredicate() == false) 660 store_inst->forwardOldRegs(); 661 662 if (storeQueue[store_idx].size == 0) { 663 DPRINTF(LSQUnit,"Fault on Store PC %s, [sn:%lli], Size = 0\n", 664 store_inst->pcState(), store_inst->seqNum); 665 666 return store_fault; 667 } else if (store_inst->readPredicate() == false) { 668 DPRINTF(LSQUnit, "Store [sn:%lli] not executed from predication\n", 669 store_inst->seqNum); 670 return store_fault; 671 } 672 673 assert(store_fault == NoFault); 674 675 if (store_inst->isStoreConditional()) { 676 // Store conditionals need to set themselves as able to 677 // writeback if we haven't had a fault by here. 678 storeQueue[store_idx].canWB = true; 679 680 ++storesToWB; 681 } 682 683 return checkViolations(load_idx, store_inst); 684 685} 686 687template <class Impl> 688void 689LSQUnit<Impl>::commitLoad() 690{ 691 assert(loadQueue[loadHead]); 692 693 DPRINTF(LSQUnit, "Committing head load instruction, PC %s\n", 694 loadQueue[loadHead]->pcState()); 695 696 loadQueue[loadHead] = NULL; 697 698 incrLdIdx(loadHead); 699 700 --loads; 701} 702 703template <class Impl> 704void 705LSQUnit<Impl>::commitLoads(InstSeqNum &youngest_inst) 706{ 707 assert(loads == 0 || loadQueue[loadHead]); 708 709 while (loads != 0 && loadQueue[loadHead]->seqNum <= youngest_inst) { 710 commitLoad(); 711 } 712} 713 714template <class Impl> 715void 716LSQUnit<Impl>::commitStores(InstSeqNum &youngest_inst) 717{ 718 assert(stores == 0 || storeQueue[storeHead].inst); 719 720 int store_idx = storeHead; 721 722 while (store_idx != storeTail) { 723 assert(storeQueue[store_idx].inst); 724 // Mark any stores that are now committed and have not yet 725 // been marked as able to write back. 726 if (!storeQueue[store_idx].canWB) { 727 if (storeQueue[store_idx].inst->seqNum > youngest_inst) { 728 break; 729 } 730 DPRINTF(LSQUnit, "Marking store as able to write back, PC " 731 "%s [sn:%lli]\n", 732 storeQueue[store_idx].inst->pcState(), 733 storeQueue[store_idx].inst->seqNum); 734 735 storeQueue[store_idx].canWB = true; 736 737 ++storesToWB; 738 } 739 740 incrStIdx(store_idx); 741 } 742} 743 744template <class Impl> 745void 746LSQUnit<Impl>::writebackPendingStore() 747{ 748 if (hasPendingPkt) { 749 assert(pendingPkt != NULL); 750 751 // If the cache is blocked, this will store the packet for retry. 752 if (sendStore(pendingPkt)) { 753 storePostSend(pendingPkt); 754 } 755 pendingPkt = NULL; 756 hasPendingPkt = false; 757 } 758} 759 760template <class Impl> 761void 762LSQUnit<Impl>::writebackStores() 763{ 764 // First writeback the second packet from any split store that didn't 765 // complete last cycle because there weren't enough cache ports available. 766 if (TheISA::HasUnalignedMemAcc) { 767 writebackPendingStore(); 768 } 769 770 while (storesToWB > 0 && 771 storeWBIdx != storeTail && 772 storeQueue[storeWBIdx].inst && 773 storeQueue[storeWBIdx].canWB &&
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774 ((!needsTSO) || (!storeInFlight)) && |
775 usedPorts < cachePorts) { 776 777 if (isStoreBlocked || lsq->cacheBlocked()) { 778 DPRINTF(LSQUnit, "Unable to write back any more stores, cache" 779 " is blocked!\n"); 780 break; 781 } 782 783 // Store didn't write any data so no need to write it back to 784 // memory. 785 if (storeQueue[storeWBIdx].size == 0) { 786 completeStore(storeWBIdx); 787 788 incrStIdx(storeWBIdx); 789 790 continue; 791 } 792 793 ++usedPorts; 794 795 if (storeQueue[storeWBIdx].inst->isDataPrefetch()) { 796 incrStIdx(storeWBIdx); 797 798 continue; 799 } 800 801 assert(storeQueue[storeWBIdx].req); 802 assert(!storeQueue[storeWBIdx].committed); 803 804 if (TheISA::HasUnalignedMemAcc && storeQueue[storeWBIdx].isSplit) { 805 assert(storeQueue[storeWBIdx].sreqLow); 806 assert(storeQueue[storeWBIdx].sreqHigh); 807 } 808 809 DynInstPtr inst = storeQueue[storeWBIdx].inst; 810 811 Request *req = storeQueue[storeWBIdx].req; 812 RequestPtr sreqLow = storeQueue[storeWBIdx].sreqLow; 813 RequestPtr sreqHigh = storeQueue[storeWBIdx].sreqHigh; 814 815 storeQueue[storeWBIdx].committed = true; 816 817 assert(!inst->memData); 818 inst->memData = new uint8_t[64]; 819 820 memcpy(inst->memData, storeQueue[storeWBIdx].data, req->getSize()); 821 822 MemCmd command = 823 req->isSwap() ? MemCmd::SwapReq : 824 (req->isLLSC() ? MemCmd::StoreCondReq : MemCmd::WriteReq); 825 PacketPtr data_pkt; 826 PacketPtr snd_data_pkt = NULL; 827 828 LSQSenderState *state = new LSQSenderState; 829 state->isLoad = false; 830 state->idx = storeWBIdx; 831 state->inst = inst; 832 833 if (!TheISA::HasUnalignedMemAcc || !storeQueue[storeWBIdx].isSplit) { 834 835 // Build a single data packet if the store isn't split. 836 data_pkt = new Packet(req, command, Packet::Broadcast); 837 data_pkt->dataStatic(inst->memData); 838 data_pkt->senderState = state; 839 } else { 840 // Create two packets if the store is split in two. 841 data_pkt = new Packet(sreqLow, command, Packet::Broadcast); 842 snd_data_pkt = new Packet(sreqHigh, command, Packet::Broadcast); 843 844 data_pkt->dataStatic(inst->memData); 845 snd_data_pkt->dataStatic(inst->memData + sreqLow->getSize()); 846 847 data_pkt->senderState = state; 848 snd_data_pkt->senderState = state; 849 850 state->isSplit = true; 851 state->outstanding = 2; 852 853 // Can delete the main request now. 854 delete req; 855 req = sreqLow; 856 } 857 858 DPRINTF(LSQUnit, "D-Cache: Writing back store idx:%i PC:%s " 859 "to Addr:%#x, data:%#x [sn:%lli]\n", 860 storeWBIdx, inst->pcState(), 861 req->getPaddr(), (int)*(inst->memData), 862 inst->seqNum); 863 864 // @todo: Remove this SC hack once the memory system handles it. 865 if (inst->isStoreConditional()) { 866 assert(!storeQueue[storeWBIdx].isSplit); 867 // Disable recording the result temporarily. Writing to 868 // misc regs normally updates the result, but this is not 869 // the desired behavior when handling store conditionals. 870 inst->recordResult = false; 871 bool success = TheISA::handleLockedWrite(inst.get(), req); 872 inst->recordResult = true; 873 874 if (!success) { 875 // Instantly complete this store. 876 DPRINTF(LSQUnit, "Store conditional [sn:%lli] failed. " 877 "Instantly completing it.\n", 878 inst->seqNum); 879 WritebackEvent *wb = new WritebackEvent(inst, data_pkt, this); 880 cpu->schedule(wb, curTick() + 1); 881 completeStore(storeWBIdx); 882 incrStIdx(storeWBIdx); 883 continue; 884 } 885 } else { 886 // Non-store conditionals do not need a writeback. 887 state->noWB = true; 888 } 889 890 bool split = 891 TheISA::HasUnalignedMemAcc && storeQueue[storeWBIdx].isSplit; 892 893 ThreadContext *thread = cpu->tcBase(lsqID); 894 895 if (req->isMmappedIpr()) { 896 assert(!inst->isStoreConditional()); 897 TheISA::handleIprWrite(thread, data_pkt); 898 delete data_pkt; 899 if (split) { 900 assert(snd_data_pkt->req->isMmappedIpr()); 901 TheISA::handleIprWrite(thread, snd_data_pkt); 902 delete snd_data_pkt; 903 delete sreqLow; 904 delete sreqHigh; 905 } 906 delete state; 907 delete req; 908 completeStore(storeWBIdx); 909 incrStIdx(storeWBIdx); 910 } else if (!sendStore(data_pkt)) { 911 DPRINTF(IEW, "D-Cache became blocked when writing [sn:%lli], will" 912 "retry later\n", 913 inst->seqNum); 914 915 // Need to store the second packet, if split. 916 if (split) { 917 state->pktToSend = true; 918 state->pendingPacket = snd_data_pkt; 919 } 920 } else { 921 922 // If split, try to send the second packet too 923 if (split) { 924 assert(snd_data_pkt); 925 926 // Ensure there are enough ports to use. 927 if (usedPorts < cachePorts) { 928 ++usedPorts; 929 if (sendStore(snd_data_pkt)) { 930 storePostSend(snd_data_pkt); 931 } else { 932 DPRINTF(IEW, "D-Cache became blocked when writing" 933 " [sn:%lli] second packet, will retry later\n", 934 inst->seqNum); 935 } 936 } else { 937 938 // Store the packet for when there's free ports. 939 assert(pendingPkt == NULL); 940 pendingPkt = snd_data_pkt; 941 hasPendingPkt = true; 942 } 943 } else { 944 945 // Not a split store. 946 storePostSend(data_pkt); 947 } 948 } 949 } 950 951 // Not sure this should set it to 0. 952 usedPorts = 0; 953 954 assert(stores >= 0 && storesToWB >= 0); 955} 956 957/*template <class Impl> 958void 959LSQUnit<Impl>::removeMSHR(InstSeqNum seqNum) 960{ 961 list<InstSeqNum>::iterator mshr_it = find(mshrSeqNums.begin(), 962 mshrSeqNums.end(), 963 seqNum); 964 965 if (mshr_it != mshrSeqNums.end()) { 966 mshrSeqNums.erase(mshr_it); 967 DPRINTF(LSQUnit, "Removing MSHR. count = %i\n",mshrSeqNums.size()); 968 } 969}*/ 970 971template <class Impl> 972void 973LSQUnit<Impl>::squash(const InstSeqNum &squashed_num) 974{ 975 DPRINTF(LSQUnit, "Squashing until [sn:%lli]!" 976 "(Loads:%i Stores:%i)\n", squashed_num, loads, stores); 977 978 int load_idx = loadTail; 979 decrLdIdx(load_idx); 980 981 while (loads != 0 && loadQueue[load_idx]->seqNum > squashed_num) { 982 DPRINTF(LSQUnit,"Load Instruction PC %s squashed, " 983 "[sn:%lli]\n", 984 loadQueue[load_idx]->pcState(), 985 loadQueue[load_idx]->seqNum); 986 987 if (isStalled() && load_idx == stallingLoadIdx) { 988 stalled = false; 989 stallingStoreIsn = 0; 990 stallingLoadIdx = 0; 991 } 992 993 // Clear the smart pointer to make sure it is decremented. 994 loadQueue[load_idx]->setSquashed(); 995 loadQueue[load_idx] = NULL; 996 --loads; 997 998 // Inefficient! 999 loadTail = load_idx; 1000 1001 decrLdIdx(load_idx); 1002 ++lsqSquashedLoads; 1003 } 1004 1005 if (isLoadBlocked) { 1006 if (squashed_num < blockedLoadSeqNum) { 1007 isLoadBlocked = false; 1008 loadBlockedHandled = false; 1009 blockedLoadSeqNum = 0; 1010 } 1011 } 1012 1013 if (memDepViolator && squashed_num < memDepViolator->seqNum) { 1014 memDepViolator = NULL; 1015 } 1016 1017 int store_idx = storeTail; 1018 decrStIdx(store_idx); 1019 1020 while (stores != 0 && 1021 storeQueue[store_idx].inst->seqNum > squashed_num) { 1022 // Instructions marked as can WB are already committed. 1023 if (storeQueue[store_idx].canWB) { 1024 break; 1025 } 1026 1027 DPRINTF(LSQUnit,"Store Instruction PC %s squashed, " 1028 "idx:%i [sn:%lli]\n", 1029 storeQueue[store_idx].inst->pcState(), 1030 store_idx, storeQueue[store_idx].inst->seqNum); 1031 1032 // I don't think this can happen. It should have been cleared 1033 // by the stalling load. 1034 if (isStalled() && 1035 storeQueue[store_idx].inst->seqNum == stallingStoreIsn) { 1036 panic("Is stalled should have been cleared by stalling load!\n"); 1037 stalled = false; 1038 stallingStoreIsn = 0; 1039 } 1040 1041 // Clear the smart pointer to make sure it is decremented. 1042 storeQueue[store_idx].inst->setSquashed(); 1043 storeQueue[store_idx].inst = NULL; 1044 storeQueue[store_idx].canWB = 0; 1045 1046 // Must delete request now that it wasn't handed off to 1047 // memory. This is quite ugly. @todo: Figure out the proper 1048 // place to really handle request deletes. 1049 delete storeQueue[store_idx].req; 1050 if (TheISA::HasUnalignedMemAcc && storeQueue[store_idx].isSplit) { 1051 delete storeQueue[store_idx].sreqLow; 1052 delete storeQueue[store_idx].sreqHigh; 1053 1054 storeQueue[store_idx].sreqLow = NULL; 1055 storeQueue[store_idx].sreqHigh = NULL; 1056 } 1057 1058 storeQueue[store_idx].req = NULL; 1059 --stores; 1060 1061 // Inefficient! 1062 storeTail = store_idx; 1063 1064 decrStIdx(store_idx); 1065 ++lsqSquashedStores; 1066 } 1067} 1068 1069template <class Impl> 1070void 1071LSQUnit<Impl>::storePostSend(PacketPtr pkt) 1072{ 1073 if (isStalled() && 1074 storeQueue[storeWBIdx].inst->seqNum == stallingStoreIsn) { 1075 DPRINTF(LSQUnit, "Unstalling, stalling store [sn:%lli] " 1076 "load idx:%i\n", 1077 stallingStoreIsn, stallingLoadIdx); 1078 stalled = false; 1079 stallingStoreIsn = 0; 1080 iewStage->replayMemInst(loadQueue[stallingLoadIdx]); 1081 } 1082 1083 if (!storeQueue[storeWBIdx].inst->isStoreConditional()) { 1084 // The store is basically completed at this time. This 1085 // only works so long as the checker doesn't try to 1086 // verify the value in memory for stores. 1087 storeQueue[storeWBIdx].inst->setCompleted(); 1088#if USE_CHECKER 1089 if (cpu->checker) { 1090 cpu->checker->verify(storeQueue[storeWBIdx].inst); 1091 } 1092#endif 1093 } 1094
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1095 if (needsTSO) { 1096 storeInFlight = true; 1097 } 1098 |
1099 incrStIdx(storeWBIdx); 1100} 1101 1102template <class Impl> 1103void 1104LSQUnit<Impl>::writeback(DynInstPtr &inst, PacketPtr pkt) 1105{ 1106 iewStage->wakeCPU(); 1107 1108 // Squashed instructions do not need to complete their access. 1109 if (inst->isSquashed()) { 1110 iewStage->decrWb(inst->seqNum); 1111 assert(!inst->isStore()); 1112 ++lsqIgnoredResponses; 1113 return; 1114 } 1115 1116 if (!inst->isExecuted()) { 1117 inst->setExecuted(); 1118 1119 // Complete access to copy data to proper place. 1120 inst->completeAcc(pkt); 1121 } 1122 1123 // Need to insert instruction into queue to commit 1124 iewStage->instToCommit(inst); 1125 1126 iewStage->activityThisCycle(); 1127 1128 // see if this load changed the PC 1129 iewStage->checkMisprediction(inst); 1130} 1131 1132template <class Impl> 1133void 1134LSQUnit<Impl>::completeStore(int store_idx) 1135{ 1136 assert(storeQueue[store_idx].inst); 1137 storeQueue[store_idx].completed = true; 1138 --storesToWB; 1139 // A bit conservative because a store completion may not free up entries, 1140 // but hopefully avoids two store completions in one cycle from making 1141 // the CPU tick twice. 1142 cpu->wakeCPU(); 1143 cpu->activityThisCycle(); 1144 1145 if (store_idx == storeHead) { 1146 do { 1147 incrStIdx(storeHead); 1148 1149 --stores; 1150 } while (storeQueue[storeHead].completed && 1151 storeHead != storeTail); 1152 1153 iewStage->updateLSQNextCycle = true; 1154 } 1155 1156 DPRINTF(LSQUnit, "Completing store [sn:%lli], idx:%i, store head " 1157 "idx:%i\n", 1158 storeQueue[store_idx].inst->seqNum, store_idx, storeHead); 1159 1160 if (isStalled() && 1161 storeQueue[store_idx].inst->seqNum == stallingStoreIsn) { 1162 DPRINTF(LSQUnit, "Unstalling, stalling store [sn:%lli] " 1163 "load idx:%i\n", 1164 stallingStoreIsn, stallingLoadIdx); 1165 stalled = false; 1166 stallingStoreIsn = 0; 1167 iewStage->replayMemInst(loadQueue[stallingLoadIdx]); 1168 } 1169 1170 storeQueue[store_idx].inst->setCompleted(); 1171
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1172 if (needsTSO) { 1173 storeInFlight = false; 1174 } 1175 |
1176 // Tell the checker we've completed this instruction. Some stores 1177 // may get reported twice to the checker, but the checker can 1178 // handle that case. 1179#if USE_CHECKER 1180 if (cpu->checker) { 1181 cpu->checker->verify(storeQueue[store_idx].inst); 1182 } 1183#endif 1184} 1185 1186template <class Impl> 1187bool 1188LSQUnit<Impl>::sendStore(PacketPtr data_pkt) 1189{ 1190 if (!dcachePort->sendTiming(data_pkt)) { 1191 // Need to handle becoming blocked on a store. 1192 isStoreBlocked = true; 1193 ++lsqCacheBlocked; 1194 assert(retryPkt == NULL); 1195 retryPkt = data_pkt; 1196 lsq->setRetryTid(lsqID); 1197 return false; 1198 } 1199 return true; 1200} 1201 1202template <class Impl> 1203void 1204LSQUnit<Impl>::recvRetry() 1205{ 1206 if (isStoreBlocked) { 1207 DPRINTF(LSQUnit, "Receiving retry: store blocked\n"); 1208 assert(retryPkt != NULL); 1209 1210 LSQSenderState *state = 1211 dynamic_cast<LSQSenderState *>(retryPkt->senderState); 1212 1213 if (dcachePort->sendTiming(retryPkt)) { 1214 // Don't finish the store unless this is the last packet. 1215 if (!TheISA::HasUnalignedMemAcc || !state->pktToSend || 1216 state->pendingPacket == retryPkt) { 1217 state->pktToSend = false; 1218 storePostSend(retryPkt); 1219 } 1220 retryPkt = NULL; 1221 isStoreBlocked = false; 1222 lsq->setRetryTid(InvalidThreadID); 1223 1224 // Send any outstanding packet. 1225 if (TheISA::HasUnalignedMemAcc && state->pktToSend) { 1226 assert(state->pendingPacket); 1227 if (sendStore(state->pendingPacket)) { 1228 storePostSend(state->pendingPacket); 1229 } 1230 } 1231 } else { 1232 // Still blocked! 1233 ++lsqCacheBlocked; 1234 lsq->setRetryTid(lsqID); 1235 } 1236 } else if (isLoadBlocked) { 1237 DPRINTF(LSQUnit, "Loads squash themselves and all younger insts, " 1238 "no need to resend packet.\n"); 1239 } else { 1240 DPRINTF(LSQUnit, "Retry received but LSQ is no longer blocked.\n"); 1241 } 1242} 1243 1244template <class Impl> 1245inline void 1246LSQUnit<Impl>::incrStIdx(int &store_idx) 1247{ 1248 if (++store_idx >= SQEntries) 1249 store_idx = 0; 1250} 1251 1252template <class Impl> 1253inline void 1254LSQUnit<Impl>::decrStIdx(int &store_idx) 1255{ 1256 if (--store_idx < 0) 1257 store_idx += SQEntries; 1258} 1259 1260template <class Impl> 1261inline void 1262LSQUnit<Impl>::incrLdIdx(int &load_idx) 1263{ 1264 if (++load_idx >= LQEntries) 1265 load_idx = 0; 1266} 1267 1268template <class Impl> 1269inline void 1270LSQUnit<Impl>::decrLdIdx(int &load_idx) 1271{ 1272 if (--load_idx < 0) 1273 load_idx += LQEntries; 1274} 1275 1276template <class Impl> 1277void 1278LSQUnit<Impl>::dumpInsts() 1279{ 1280 cprintf("Load store queue: Dumping instructions.\n"); 1281 cprintf("Load queue size: %i\n", loads); 1282 cprintf("Load queue: "); 1283 1284 int load_idx = loadHead; 1285 1286 while (load_idx != loadTail && loadQueue[load_idx]) { 1287 cprintf("%s ", loadQueue[load_idx]->pcState()); 1288 1289 incrLdIdx(load_idx); 1290 } 1291 1292 cprintf("Store queue size: %i\n", stores); 1293 cprintf("Store queue: "); 1294 1295 int store_idx = storeHead; 1296 1297 while (store_idx != storeTail && storeQueue[store_idx].inst) { 1298 cprintf("%s ", storeQueue[store_idx].inst->pcState()); 1299 1300 incrStIdx(store_idx); 1301 } 1302 1303 cprintf("\n"); 1304}
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