5 * All rights reserved 6 * 7 * The license below extends only to copyright in the software and shall 8 * not be construed as granting a license to any other intellectual 9 * property including but not limited to intellectual property relating 10 * to a hardware implementation of the functionality of the software 11 * licensed hereunder. You may use the software subject to the license 12 * terms below provided that you ensure that this notice is replicated 13 * unmodified and in its entirety in all distributions of the software, 14 * modified or unmodified, in source code or in binary form. 15 * 16 * Copyright (c) 2004-2005 The Regents of The University of Michigan 17 * All rights reserved. 18 * 19 * Redistribution and use in source and binary forms, with or without 20 * modification, are permitted provided that the following conditions are 21 * met: redistributions of source code must retain the above copyright 22 * notice, this list of conditions and the following disclaimer; 23 * redistributions in binary form must reproduce the above copyright 24 * notice, this list of conditions and the following disclaimer in the 25 * documentation and/or other materials provided with the distribution; 26 * neither the name of the copyright holders nor the names of its 27 * contributors may be used to endorse or promote products derived from 28 * this software without specific prior written permission. 29 * 30 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 31 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 32 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 33 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 34 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 35 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 36 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 37 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 38 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 39 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 40 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 41 * 42 * Authors: Kevin Lim 43 * Korey Sewell 44 */ 45 46#ifndef __CPU_O3_LSQ_UNIT_IMPL_HH__ 47#define __CPU_O3_LSQ_UNIT_IMPL_HH__ 48 49#include "arch/generic/debugfaults.hh" 50#include "arch/locked_mem.hh" 51#include "base/str.hh" 52#include "config/the_isa.hh" 53#include "cpu/checker/cpu.hh" 54#include "cpu/o3/lsq.hh" 55#include "cpu/o3/lsq_unit.hh" 56#include "debug/Activity.hh" 57#include "debug/IEW.hh" 58#include "debug/LSQUnit.hh" 59#include "debug/O3PipeView.hh" 60#include "mem/packet.hh" 61#include "mem/request.hh" 62 63template<class Impl> 64LSQUnit<Impl>::WritebackEvent::WritebackEvent(DynInstPtr &_inst, PacketPtr _pkt, 65 LSQUnit *lsq_ptr) 66 : Event(Default_Pri, AutoDelete), 67 inst(_inst), pkt(_pkt), lsqPtr(lsq_ptr) 68{ 69} 70 71template<class Impl> 72void 73LSQUnit<Impl>::WritebackEvent::process() 74{ 75 assert(!lsqPtr->cpu->switchedOut()); 76 77 lsqPtr->writeback(inst, pkt); 78 79 if (pkt->senderState) 80 delete pkt->senderState; 81 82 delete pkt->req; 83 delete pkt; 84} 85 86template<class Impl> 87const char * 88LSQUnit<Impl>::WritebackEvent::description() const 89{ 90 return "Store writeback"; 91} 92 93template<class Impl> 94void 95LSQUnit<Impl>::completeDataAccess(PacketPtr pkt) 96{ 97 LSQSenderState *state = dynamic_cast<LSQSenderState *>(pkt->senderState); 98 DynInstPtr inst = state->inst; 99 DPRINTF(IEW, "Writeback event [sn:%lli].\n", inst->seqNum); 100 DPRINTF(Activity, "Activity: Writeback event [sn:%lli].\n", inst->seqNum); 101 102 //iewStage->ldstQueue.removeMSHR(inst->threadNumber,inst->seqNum); 103 104 // If this is a split access, wait until all packets are received. 105 if (TheISA::HasUnalignedMemAcc && !state->complete()) { 106 delete pkt->req; 107 delete pkt; 108 return; 109 } 110 111 assert(!cpu->switchedOut()); 112 if (inst->isSquashed()) { 113 iewStage->decrWb(inst->seqNum); 114 } else { 115 if (!state->noWB) { 116 if (!TheISA::HasUnalignedMemAcc || !state->isSplit || 117 !state->isLoad) { 118 writeback(inst, pkt); 119 } else { 120 writeback(inst, state->mainPkt); 121 } 122 } 123 124 if (inst->isStore()) { 125 completeStore(state->idx); 126 } 127 } 128 129 if (TheISA::HasUnalignedMemAcc && state->isSplit && state->isLoad) { 130 delete state->mainPkt->req; 131 delete state->mainPkt; 132 } 133 134 pkt->req->setAccessLatency(); 135 cpu->ppDataAccessComplete->notify(std::make_pair(inst, pkt)); 136 137 delete state; 138 delete pkt->req; 139 delete pkt; 140} 141 142template <class Impl> 143LSQUnit<Impl>::LSQUnit() 144 : loads(0), stores(0), storesToWB(0), cacheBlockMask(0), stalled(false), 145 isStoreBlocked(false), isLoadBlocked(false), 146 loadBlockedHandled(false), storeInFlight(false), hasPendingPkt(false) 147{ 148} 149 150template<class Impl> 151void 152LSQUnit<Impl>::init(O3CPU *cpu_ptr, IEW *iew_ptr, DerivO3CPUParams *params, 153 LSQ *lsq_ptr, unsigned maxLQEntries, unsigned maxSQEntries, 154 unsigned id) 155{ 156 cpu = cpu_ptr; 157 iewStage = iew_ptr; 158 159 lsq = lsq_ptr; 160 161 lsqID = id; 162 163 DPRINTF(LSQUnit, "Creating LSQUnit%i object.\n",id); 164 165 // Add 1 for the sentinel entry (they are circular queues). 166 LQEntries = maxLQEntries + 1; 167 SQEntries = maxSQEntries + 1; 168 169 //Due to uint8_t index in LSQSenderState 170 assert(LQEntries <= 256); 171 assert(SQEntries <= 256); 172 173 loadQueue.resize(LQEntries); 174 storeQueue.resize(SQEntries); 175 176 depCheckShift = params->LSQDepCheckShift; 177 checkLoads = params->LSQCheckLoads; 178 cachePorts = params->cachePorts; 179 needsTSO = params->needsTSO; 180 181 resetState(); 182} 183 184 185template<class Impl> 186void 187LSQUnit<Impl>::resetState() 188{ 189 loads = stores = storesToWB = 0; 190 191 loadHead = loadTail = 0; 192 193 storeHead = storeWBIdx = storeTail = 0; 194 195 usedPorts = 0; 196 197 retryPkt = NULL; 198 memDepViolator = NULL; 199 200 blockedLoadSeqNum = 0; 201 202 stalled = false; 203 isLoadBlocked = false; 204 loadBlockedHandled = false; 205 206 cacheBlockMask = ~(cpu->cacheLineSize() - 1); 207} 208 209template<class Impl> 210std::string 211LSQUnit<Impl>::name() const 212{ 213 if (Impl::MaxThreads == 1) { 214 return iewStage->name() + ".lsq"; 215 } else { 216 return iewStage->name() + ".lsq.thread" + to_string(lsqID); 217 } 218} 219 220template<class Impl> 221void 222LSQUnit<Impl>::regStats() 223{ 224 lsqForwLoads 225 .name(name() + ".forwLoads") 226 .desc("Number of loads that had data forwarded from stores"); 227 228 invAddrLoads 229 .name(name() + ".invAddrLoads") 230 .desc("Number of loads ignored due to an invalid address"); 231 232 lsqSquashedLoads 233 .name(name() + ".squashedLoads") 234 .desc("Number of loads squashed"); 235 236 lsqIgnoredResponses 237 .name(name() + ".ignoredResponses") 238 .desc("Number of memory responses ignored because the instruction is squashed"); 239 240 lsqMemOrderViolation 241 .name(name() + ".memOrderViolation") 242 .desc("Number of memory ordering violations"); 243 244 lsqSquashedStores 245 .name(name() + ".squashedStores") 246 .desc("Number of stores squashed"); 247 248 invAddrSwpfs 249 .name(name() + ".invAddrSwpfs") 250 .desc("Number of software prefetches ignored due to an invalid address"); 251 252 lsqBlockedLoads 253 .name(name() + ".blockedLoads") 254 .desc("Number of blocked loads due to partial load-store forwarding"); 255 256 lsqRescheduledLoads 257 .name(name() + ".rescheduledLoads") 258 .desc("Number of loads that were rescheduled"); 259 260 lsqCacheBlocked 261 .name(name() + ".cacheBlocked") 262 .desc("Number of times an access to memory failed due to the cache being blocked"); 263} 264 265template<class Impl> 266void 267LSQUnit<Impl>::setDcachePort(MasterPort *dcache_port) 268{ 269 dcachePort = dcache_port; 270} 271 272template<class Impl> 273void 274LSQUnit<Impl>::clearLQ() 275{ 276 loadQueue.clear(); 277} 278 279template<class Impl> 280void 281LSQUnit<Impl>::clearSQ() 282{ 283 storeQueue.clear(); 284} 285 286template<class Impl> 287void 288LSQUnit<Impl>::drainSanityCheck() const 289{ 290 for (int i = 0; i < loadQueue.size(); ++i) 291 assert(!loadQueue[i]); 292 293 assert(storesToWB == 0); 294 assert(!retryPkt); 295} 296 297template<class Impl> 298void 299LSQUnit<Impl>::takeOverFrom() 300{ 301 resetState(); 302} 303 304template<class Impl> 305void 306LSQUnit<Impl>::resizeLQ(unsigned size) 307{ 308 unsigned size_plus_sentinel = size + 1; 309 assert(size_plus_sentinel >= LQEntries); 310 311 if (size_plus_sentinel > LQEntries) { 312 while (size_plus_sentinel > loadQueue.size()) { 313 DynInstPtr dummy; 314 loadQueue.push_back(dummy); 315 LQEntries++; 316 } 317 } else { 318 LQEntries = size_plus_sentinel; 319 } 320 321 assert(LQEntries <= 256); 322} 323 324template<class Impl> 325void 326LSQUnit<Impl>::resizeSQ(unsigned size) 327{ 328 unsigned size_plus_sentinel = size + 1; 329 if (size_plus_sentinel > SQEntries) { 330 while (size_plus_sentinel > storeQueue.size()) { 331 SQEntry dummy; 332 storeQueue.push_back(dummy); 333 SQEntries++; 334 } 335 } else { 336 SQEntries = size_plus_sentinel; 337 } 338 339 assert(SQEntries <= 256); 340} 341 342template <class Impl> 343void 344LSQUnit<Impl>::insert(DynInstPtr &inst) 345{ 346 assert(inst->isMemRef()); 347 348 assert(inst->isLoad() || inst->isStore()); 349 350 if (inst->isLoad()) { 351 insertLoad(inst); 352 } else { 353 insertStore(inst); 354 } 355 356 inst->setInLSQ(); 357} 358 359template <class Impl> 360void 361LSQUnit<Impl>::insertLoad(DynInstPtr &load_inst) 362{ 363 assert((loadTail + 1) % LQEntries != loadHead); 364 assert(loads < LQEntries); 365 366 DPRINTF(LSQUnit, "Inserting load PC %s, idx:%i [sn:%lli]\n", 367 load_inst->pcState(), loadTail, load_inst->seqNum); 368 369 load_inst->lqIdx = loadTail; 370 371 if (stores == 0) { 372 load_inst->sqIdx = -1; 373 } else { 374 load_inst->sqIdx = storeTail; 375 } 376 377 loadQueue[loadTail] = load_inst; 378 379 incrLdIdx(loadTail); 380 381 ++loads; 382} 383 384template <class Impl> 385void 386LSQUnit<Impl>::insertStore(DynInstPtr &store_inst) 387{ 388 // Make sure it is not full before inserting an instruction. 389 assert((storeTail + 1) % SQEntries != storeHead); 390 assert(stores < SQEntries); 391 392 DPRINTF(LSQUnit, "Inserting store PC %s, idx:%i [sn:%lli]\n", 393 store_inst->pcState(), storeTail, store_inst->seqNum); 394 395 store_inst->sqIdx = storeTail; 396 store_inst->lqIdx = loadTail; 397 398 storeQueue[storeTail] = SQEntry(store_inst); 399 400 incrStIdx(storeTail); 401 402 ++stores; 403} 404 405template <class Impl> 406typename Impl::DynInstPtr 407LSQUnit<Impl>::getMemDepViolator() 408{ 409 DynInstPtr temp = memDepViolator; 410 411 memDepViolator = NULL; 412 413 return temp; 414} 415 416template <class Impl> 417unsigned
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438void 439LSQUnit<Impl>::checkSnoop(PacketPtr pkt) 440{ 441 int load_idx = loadHead; 442 DPRINTF(LSQUnit, "Got snoop for address %#x\n", pkt->getAddr()); 443 444 // Unlock the cpu-local monitor when the CPU sees a snoop to a locked 445 // address. The CPU can speculatively execute a LL operation after a pending 446 // SC operation in the pipeline and that can make the cache monitor the CPU 447 // is connected to valid while it really shouldn't be. 448 for (int x = 0; x < cpu->numContexts(); x++) { 449 ThreadContext *tc = cpu->getContext(x); 450 bool no_squash = cpu->thread[x]->noSquashFromTC; 451 cpu->thread[x]->noSquashFromTC = true; 452 TheISA::handleLockedSnoop(tc, pkt, cacheBlockMask); 453 cpu->thread[x]->noSquashFromTC = no_squash; 454 } 455 456 Addr invalidate_addr = pkt->getAddr() & cacheBlockMask; 457 458 DynInstPtr ld_inst = loadQueue[load_idx]; 459 if (ld_inst) { 460 Addr load_addr = ld_inst->physEffAddr & cacheBlockMask; 461 // Check that this snoop didn't just invalidate our lock flag 462 if (ld_inst->effAddrValid() && load_addr == invalidate_addr && 463 ld_inst->memReqFlags & Request::LLSC) 464 TheISA::handleLockedSnoopHit(ld_inst.get()); 465 } 466 467 // If this is the only load in the LSQ we don't care 468 if (load_idx == loadTail) 469 return; 470 471 incrLdIdx(load_idx); 472 473 bool force_squash = false; 474 475 while (load_idx != loadTail) { 476 DynInstPtr ld_inst = loadQueue[load_idx]; 477 478 if (!ld_inst->effAddrValid() || ld_inst->uncacheable()) { 479 incrLdIdx(load_idx); 480 continue; 481 } 482 483 Addr load_addr = ld_inst->physEffAddr & cacheBlockMask; 484 DPRINTF(LSQUnit, "-- inst [sn:%lli] load_addr: %#x to pktAddr:%#x\n", 485 ld_inst->seqNum, load_addr, invalidate_addr); 486 487 if (load_addr == invalidate_addr || force_squash) { 488 if (needsTSO) { 489 // If we have a TSO system, as all loads must be ordered with 490 // all other loads, this load as well as *all* subsequent loads 491 // need to be squashed to prevent possible load reordering. 492 force_squash = true; 493 } 494 if (ld_inst->possibleLoadViolation() || force_squash) { 495 DPRINTF(LSQUnit, "Conflicting load at addr %#x [sn:%lli]\n", 496 pkt->getAddr(), ld_inst->seqNum); 497 498 // Mark the load for re-execution 499 ld_inst->fault = new ReExec; 500 } else { 501 DPRINTF(LSQUnit, "HitExternal Snoop for addr %#x [sn:%lli]\n", 502 pkt->getAddr(), ld_inst->seqNum); 503 504 // Make sure that we don't lose a snoop hitting a LOCKED 505 // address since the LOCK* flags don't get updated until 506 // commit. 507 if (ld_inst->memReqFlags & Request::LLSC) 508 TheISA::handleLockedSnoopHit(ld_inst.get()); 509 510 // If a older load checks this and it's true 511 // then we might have missed the snoop 512 // in which case we need to invalidate to be sure 513 ld_inst->hitExternalSnoop(true); 514 } 515 } 516 incrLdIdx(load_idx); 517 } 518 return; 519} 520 521template <class Impl> 522Fault 523LSQUnit<Impl>::checkViolations(int load_idx, DynInstPtr &inst) 524{ 525 Addr inst_eff_addr1 = inst->effAddr >> depCheckShift; 526 Addr inst_eff_addr2 = (inst->effAddr + inst->effSize - 1) >> depCheckShift; 527 528 /** @todo in theory you only need to check an instruction that has executed 529 * however, there isn't a good way in the pipeline at the moment to check 530 * all instructions that will execute before the store writes back. Thus, 531 * like the implementation that came before it, we're overly conservative. 532 */ 533 while (load_idx != loadTail) { 534 DynInstPtr ld_inst = loadQueue[load_idx]; 535 if (!ld_inst->effAddrValid() || ld_inst->uncacheable()) { 536 incrLdIdx(load_idx); 537 continue; 538 } 539 540 Addr ld_eff_addr1 = ld_inst->effAddr >> depCheckShift; 541 Addr ld_eff_addr2 = 542 (ld_inst->effAddr + ld_inst->effSize - 1) >> depCheckShift; 543 544 if (inst_eff_addr2 >= ld_eff_addr1 && inst_eff_addr1 <= ld_eff_addr2) { 545 if (inst->isLoad()) { 546 // If this load is to the same block as an external snoop 547 // invalidate that we've observed then the load needs to be 548 // squashed as it could have newer data 549 if (ld_inst->hitExternalSnoop()) { 550 if (!memDepViolator || 551 ld_inst->seqNum < memDepViolator->seqNum) { 552 DPRINTF(LSQUnit, "Detected fault with inst [sn:%lli] " 553 "and [sn:%lli] at address %#x\n", 554 inst->seqNum, ld_inst->seqNum, ld_eff_addr1); 555 memDepViolator = ld_inst; 556 557 ++lsqMemOrderViolation; 558 559 return new GenericISA::M5PanicFault( 560 "Detected fault with inst [sn:%lli] and " 561 "[sn:%lli] at address %#x\n", 562 inst->seqNum, ld_inst->seqNum, ld_eff_addr1); 563 } 564 } 565 566 // Otherwise, mark the load has a possible load violation 567 // and if we see a snoop before it's commited, we need to squash 568 ld_inst->possibleLoadViolation(true); 569 DPRINTF(LSQUnit, "Found possible load violaiton at addr: %#x" 570 " between instructions [sn:%lli] and [sn:%lli]\n", 571 inst_eff_addr1, inst->seqNum, ld_inst->seqNum); 572 } else { 573 // A load/store incorrectly passed this store. 574 // Check if we already have a violator, or if it's newer 575 // squash and refetch. 576 if (memDepViolator && ld_inst->seqNum > memDepViolator->seqNum) 577 break; 578 579 DPRINTF(LSQUnit, "Detected fault with inst [sn:%lli] and " 580 "[sn:%lli] at address %#x\n", 581 inst->seqNum, ld_inst->seqNum, ld_eff_addr1); 582 memDepViolator = ld_inst; 583 584 ++lsqMemOrderViolation; 585 586 return new GenericISA::M5PanicFault("Detected fault with " 587 "inst [sn:%lli] and [sn:%lli] at address %#x\n", 588 inst->seqNum, ld_inst->seqNum, ld_eff_addr1); 589 } 590 } 591 592 incrLdIdx(load_idx); 593 } 594 return NoFault; 595} 596 597 598 599 600template <class Impl> 601Fault 602LSQUnit<Impl>::executeLoad(DynInstPtr &inst) 603{ 604 using namespace TheISA; 605 // Execute a specific load. 606 Fault load_fault = NoFault; 607 608 DPRINTF(LSQUnit, "Executing load PC %s, [sn:%lli]\n", 609 inst->pcState(), inst->seqNum); 610 611 assert(!inst->isSquashed()); 612 613 load_fault = inst->initiateAcc(); 614 615 if (inst->isTranslationDelayed() && 616 load_fault == NoFault) 617 return load_fault; 618 619 // If the instruction faulted or predicated false, then we need to send it 620 // along to commit without the instruction completing. 621 if (load_fault != NoFault || !inst->readPredicate()) { 622 // Send this instruction to commit, also make sure iew stage 623 // realizes there is activity. 624 // Mark it as executed unless it is an uncached load that 625 // needs to hit the head of commit. 626 if (!inst->readPredicate()) 627 inst->forwardOldRegs(); 628 DPRINTF(LSQUnit, "Load [sn:%lli] not executed from %s\n", 629 inst->seqNum, 630 (load_fault != NoFault ? "fault" : "predication")); 631 if (!(inst->hasRequest() && inst->uncacheable()) || 632 inst->isAtCommit()) { 633 inst->setExecuted(); 634 } 635 iewStage->instToCommit(inst); 636 iewStage->activityThisCycle(); 637 } else if (!loadBlocked()) { 638 assert(inst->effAddrValid()); 639 int load_idx = inst->lqIdx; 640 incrLdIdx(load_idx); 641 642 if (checkLoads) 643 return checkViolations(load_idx, inst); 644 } 645 646 return load_fault; 647} 648 649template <class Impl> 650Fault 651LSQUnit<Impl>::executeStore(DynInstPtr &store_inst) 652{ 653 using namespace TheISA; 654 // Make sure that a store exists. 655 assert(stores != 0); 656 657 int store_idx = store_inst->sqIdx; 658 659 DPRINTF(LSQUnit, "Executing store PC %s [sn:%lli]\n", 660 store_inst->pcState(), store_inst->seqNum); 661 662 assert(!store_inst->isSquashed()); 663 664 // Check the recently completed loads to see if any match this store's 665 // address. If so, then we have a memory ordering violation. 666 int load_idx = store_inst->lqIdx; 667 668 Fault store_fault = store_inst->initiateAcc(); 669 670 if (store_inst->isTranslationDelayed() && 671 store_fault == NoFault) 672 return store_fault; 673 674 if (!store_inst->readPredicate()) 675 store_inst->forwardOldRegs(); 676 677 if (storeQueue[store_idx].size == 0) { 678 DPRINTF(LSQUnit,"Fault on Store PC %s, [sn:%lli], Size = 0\n", 679 store_inst->pcState(), store_inst->seqNum); 680 681 return store_fault; 682 } else if (!store_inst->readPredicate()) { 683 DPRINTF(LSQUnit, "Store [sn:%lli] not executed from predication\n", 684 store_inst->seqNum); 685 return store_fault; 686 } 687 688 assert(store_fault == NoFault); 689 690 if (store_inst->isStoreConditional()) { 691 // Store conditionals need to set themselves as able to 692 // writeback if we haven't had a fault by here. 693 storeQueue[store_idx].canWB = true; 694 695 ++storesToWB; 696 } 697 698 return checkViolations(load_idx, store_inst); 699 700} 701 702template <class Impl> 703void 704LSQUnit<Impl>::commitLoad() 705{ 706 assert(loadQueue[loadHead]); 707 708 DPRINTF(LSQUnit, "Committing head load instruction, PC %s\n", 709 loadQueue[loadHead]->pcState()); 710 711 loadQueue[loadHead] = NULL; 712 713 incrLdIdx(loadHead); 714 715 --loads; 716} 717 718template <class Impl> 719void 720LSQUnit<Impl>::commitLoads(InstSeqNum &youngest_inst) 721{ 722 assert(loads == 0 || loadQueue[loadHead]); 723 724 while (loads != 0 && loadQueue[loadHead]->seqNum <= youngest_inst) { 725 commitLoad(); 726 } 727} 728 729template <class Impl> 730void 731LSQUnit<Impl>::commitStores(InstSeqNum &youngest_inst) 732{ 733 assert(stores == 0 || storeQueue[storeHead].inst); 734 735 int store_idx = storeHead; 736 737 while (store_idx != storeTail) { 738 assert(storeQueue[store_idx].inst); 739 // Mark any stores that are now committed and have not yet 740 // been marked as able to write back. 741 if (!storeQueue[store_idx].canWB) { 742 if (storeQueue[store_idx].inst->seqNum > youngest_inst) { 743 break; 744 } 745 DPRINTF(LSQUnit, "Marking store as able to write back, PC " 746 "%s [sn:%lli]\n", 747 storeQueue[store_idx].inst->pcState(), 748 storeQueue[store_idx].inst->seqNum); 749 750 storeQueue[store_idx].canWB = true; 751 752 ++storesToWB; 753 } 754 755 incrStIdx(store_idx); 756 } 757} 758 759template <class Impl> 760void 761LSQUnit<Impl>::writebackPendingStore() 762{ 763 if (hasPendingPkt) { 764 assert(pendingPkt != NULL); 765 766 // If the cache is blocked, this will store the packet for retry. 767 if (sendStore(pendingPkt)) { 768 storePostSend(pendingPkt); 769 } 770 pendingPkt = NULL; 771 hasPendingPkt = false; 772 } 773} 774 775template <class Impl> 776void 777LSQUnit<Impl>::writebackStores() 778{ 779 // First writeback the second packet from any split store that didn't 780 // complete last cycle because there weren't enough cache ports available. 781 if (TheISA::HasUnalignedMemAcc) { 782 writebackPendingStore(); 783 } 784 785 while (storesToWB > 0 && 786 storeWBIdx != storeTail && 787 storeQueue[storeWBIdx].inst && 788 storeQueue[storeWBIdx].canWB && 789 ((!needsTSO) || (!storeInFlight)) && 790 usedPorts < cachePorts) { 791 792 if (isStoreBlocked || lsq->cacheBlocked()) { 793 DPRINTF(LSQUnit, "Unable to write back any more stores, cache" 794 " is blocked!\n"); 795 break; 796 } 797 798 // Store didn't write any data so no need to write it back to 799 // memory. 800 if (storeQueue[storeWBIdx].size == 0) { 801 completeStore(storeWBIdx); 802 803 incrStIdx(storeWBIdx); 804 805 continue; 806 } 807 808 ++usedPorts; 809 810 if (storeQueue[storeWBIdx].inst->isDataPrefetch()) { 811 incrStIdx(storeWBIdx); 812 813 continue; 814 } 815 816 assert(storeQueue[storeWBIdx].req); 817 assert(!storeQueue[storeWBIdx].committed); 818 819 if (TheISA::HasUnalignedMemAcc && storeQueue[storeWBIdx].isSplit) { 820 assert(storeQueue[storeWBIdx].sreqLow); 821 assert(storeQueue[storeWBIdx].sreqHigh); 822 } 823 824 DynInstPtr inst = storeQueue[storeWBIdx].inst; 825 826 Request *req = storeQueue[storeWBIdx].req; 827 RequestPtr sreqLow = storeQueue[storeWBIdx].sreqLow; 828 RequestPtr sreqHigh = storeQueue[storeWBIdx].sreqHigh; 829 830 storeQueue[storeWBIdx].committed = true; 831 832 assert(!inst->memData); 833 inst->memData = new uint8_t[req->getSize()]; 834 835 if (storeQueue[storeWBIdx].isAllZeros) 836 memset(inst->memData, 0, req->getSize()); 837 else 838 memcpy(inst->memData, storeQueue[storeWBIdx].data, req->getSize()); 839 840 MemCmd command = 841 req->isSwap() ? MemCmd::SwapReq : 842 (req->isLLSC() ? MemCmd::StoreCondReq : MemCmd::WriteReq); 843 PacketPtr data_pkt; 844 PacketPtr snd_data_pkt = NULL; 845 846 LSQSenderState *state = new LSQSenderState; 847 state->isLoad = false; 848 state->idx = storeWBIdx; 849 state->inst = inst; 850 851 if (!TheISA::HasUnalignedMemAcc || !storeQueue[storeWBIdx].isSplit) { 852 853 // Build a single data packet if the store isn't split. 854 data_pkt = new Packet(req, command); 855 data_pkt->dataStatic(inst->memData); 856 data_pkt->senderState = state; 857 } else { 858 // Create two packets if the store is split in two. 859 data_pkt = new Packet(sreqLow, command); 860 snd_data_pkt = new Packet(sreqHigh, command); 861 862 data_pkt->dataStatic(inst->memData); 863 snd_data_pkt->dataStatic(inst->memData + sreqLow->getSize()); 864 865 data_pkt->senderState = state; 866 snd_data_pkt->senderState = state; 867 868 state->isSplit = true; 869 state->outstanding = 2; 870 871 // Can delete the main request now. 872 delete req; 873 req = sreqLow; 874 } 875 876 DPRINTF(LSQUnit, "D-Cache: Writing back store idx:%i PC:%s " 877 "to Addr:%#x, data:%#x [sn:%lli]\n", 878 storeWBIdx, inst->pcState(), 879 req->getPaddr(), (int)*(inst->memData), 880 inst->seqNum); 881 882 // @todo: Remove this SC hack once the memory system handles it. 883 if (inst->isStoreConditional()) { 884 assert(!storeQueue[storeWBIdx].isSplit); 885 // Disable recording the result temporarily. Writing to 886 // misc regs normally updates the result, but this is not 887 // the desired behavior when handling store conditionals. 888 inst->recordResult(false); 889 bool success = TheISA::handleLockedWrite(inst.get(), req, cacheBlockMask); 890 inst->recordResult(true); 891 892 if (!success) { 893 // Instantly complete this store. 894 DPRINTF(LSQUnit, "Store conditional [sn:%lli] failed. " 895 "Instantly completing it.\n", 896 inst->seqNum); 897 WritebackEvent *wb = new WritebackEvent(inst, data_pkt, this); 898 cpu->schedule(wb, curTick() + 1); 899 if (cpu->checker) { 900 // Make sure to set the LLSC data for verification 901 // if checker is loaded 902 inst->reqToVerify->setExtraData(0); 903 inst->completeAcc(data_pkt); 904 } 905 completeStore(storeWBIdx); 906 incrStIdx(storeWBIdx); 907 continue; 908 } 909 } else { 910 // Non-store conditionals do not need a writeback. 911 state->noWB = true; 912 } 913 914 bool split = 915 TheISA::HasUnalignedMemAcc && storeQueue[storeWBIdx].isSplit; 916 917 ThreadContext *thread = cpu->tcBase(lsqID); 918 919 if (req->isMmappedIpr()) { 920 assert(!inst->isStoreConditional()); 921 TheISA::handleIprWrite(thread, data_pkt); 922 delete data_pkt; 923 if (split) { 924 assert(snd_data_pkt->req->isMmappedIpr()); 925 TheISA::handleIprWrite(thread, snd_data_pkt); 926 delete snd_data_pkt; 927 delete sreqLow; 928 delete sreqHigh; 929 } 930 delete state; 931 delete req; 932 completeStore(storeWBIdx); 933 incrStIdx(storeWBIdx); 934 } else if (!sendStore(data_pkt)) { 935 DPRINTF(IEW, "D-Cache became blocked when writing [sn:%lli], will" 936 "retry later\n", 937 inst->seqNum); 938 939 // Need to store the second packet, if split. 940 if (split) { 941 state->pktToSend = true; 942 state->pendingPacket = snd_data_pkt; 943 } 944 } else { 945 946 // If split, try to send the second packet too 947 if (split) { 948 assert(snd_data_pkt); 949 950 // Ensure there are enough ports to use. 951 if (usedPorts < cachePorts) { 952 ++usedPorts; 953 if (sendStore(snd_data_pkt)) { 954 storePostSend(snd_data_pkt); 955 } else { 956 DPRINTF(IEW, "D-Cache became blocked when writing" 957 " [sn:%lli] second packet, will retry later\n", 958 inst->seqNum); 959 } 960 } else { 961 962 // Store the packet for when there's free ports. 963 assert(pendingPkt == NULL); 964 pendingPkt = snd_data_pkt; 965 hasPendingPkt = true; 966 } 967 } else { 968 969 // Not a split store. 970 storePostSend(data_pkt); 971 } 972 } 973 } 974 975 // Not sure this should set it to 0. 976 usedPorts = 0; 977 978 assert(stores >= 0 && storesToWB >= 0); 979} 980 981/*template <class Impl> 982void 983LSQUnit<Impl>::removeMSHR(InstSeqNum seqNum) 984{ 985 list<InstSeqNum>::iterator mshr_it = find(mshrSeqNums.begin(), 986 mshrSeqNums.end(), 987 seqNum); 988 989 if (mshr_it != mshrSeqNums.end()) { 990 mshrSeqNums.erase(mshr_it); 991 DPRINTF(LSQUnit, "Removing MSHR. count = %i\n",mshrSeqNums.size()); 992 } 993}*/ 994 995template <class Impl> 996void 997LSQUnit<Impl>::squash(const InstSeqNum &squashed_num) 998{ 999 DPRINTF(LSQUnit, "Squashing until [sn:%lli]!" 1000 "(Loads:%i Stores:%i)\n", squashed_num, loads, stores); 1001 1002 int load_idx = loadTail; 1003 decrLdIdx(load_idx); 1004 1005 while (loads != 0 && loadQueue[load_idx]->seqNum > squashed_num) { 1006 DPRINTF(LSQUnit,"Load Instruction PC %s squashed, " 1007 "[sn:%lli]\n", 1008 loadQueue[load_idx]->pcState(), 1009 loadQueue[load_idx]->seqNum); 1010 1011 if (isStalled() && load_idx == stallingLoadIdx) { 1012 stalled = false; 1013 stallingStoreIsn = 0; 1014 stallingLoadIdx = 0; 1015 } 1016 1017 // Clear the smart pointer to make sure it is decremented. 1018 loadQueue[load_idx]->setSquashed(); 1019 loadQueue[load_idx] = NULL; 1020 --loads; 1021 1022 // Inefficient! 1023 loadTail = load_idx; 1024 1025 decrLdIdx(load_idx); 1026 ++lsqSquashedLoads; 1027 } 1028 1029 if (isLoadBlocked) { 1030 if (squashed_num < blockedLoadSeqNum) { 1031 isLoadBlocked = false; 1032 loadBlockedHandled = false; 1033 blockedLoadSeqNum = 0; 1034 } 1035 } 1036 1037 if (memDepViolator && squashed_num < memDepViolator->seqNum) { 1038 memDepViolator = NULL; 1039 } 1040 1041 int store_idx = storeTail; 1042 decrStIdx(store_idx); 1043 1044 while (stores != 0 && 1045 storeQueue[store_idx].inst->seqNum > squashed_num) { 1046 // Instructions marked as can WB are already committed. 1047 if (storeQueue[store_idx].canWB) { 1048 break; 1049 } 1050 1051 DPRINTF(LSQUnit,"Store Instruction PC %s squashed, " 1052 "idx:%i [sn:%lli]\n", 1053 storeQueue[store_idx].inst->pcState(), 1054 store_idx, storeQueue[store_idx].inst->seqNum); 1055 1056 // I don't think this can happen. It should have been cleared 1057 // by the stalling load. 1058 if (isStalled() && 1059 storeQueue[store_idx].inst->seqNum == stallingStoreIsn) { 1060 panic("Is stalled should have been cleared by stalling load!\n"); 1061 stalled = false; 1062 stallingStoreIsn = 0; 1063 } 1064 1065 // Clear the smart pointer to make sure it is decremented. 1066 storeQueue[store_idx].inst->setSquashed(); 1067 storeQueue[store_idx].inst = NULL; 1068 storeQueue[store_idx].canWB = 0; 1069 1070 // Must delete request now that it wasn't handed off to 1071 // memory. This is quite ugly. @todo: Figure out the proper 1072 // place to really handle request deletes. 1073 delete storeQueue[store_idx].req; 1074 if (TheISA::HasUnalignedMemAcc && storeQueue[store_idx].isSplit) { 1075 delete storeQueue[store_idx].sreqLow; 1076 delete storeQueue[store_idx].sreqHigh; 1077 1078 storeQueue[store_idx].sreqLow = NULL; 1079 storeQueue[store_idx].sreqHigh = NULL; 1080 } 1081 1082 storeQueue[store_idx].req = NULL; 1083 --stores; 1084 1085 // Inefficient! 1086 storeTail = store_idx; 1087 1088 decrStIdx(store_idx); 1089 ++lsqSquashedStores; 1090 } 1091} 1092 1093template <class Impl> 1094void 1095LSQUnit<Impl>::storePostSend(PacketPtr pkt) 1096{ 1097 if (isStalled() && 1098 storeQueue[storeWBIdx].inst->seqNum == stallingStoreIsn) { 1099 DPRINTF(LSQUnit, "Unstalling, stalling store [sn:%lli] " 1100 "load idx:%i\n", 1101 stallingStoreIsn, stallingLoadIdx); 1102 stalled = false; 1103 stallingStoreIsn = 0; 1104 iewStage->replayMemInst(loadQueue[stallingLoadIdx]); 1105 } 1106 1107 if (!storeQueue[storeWBIdx].inst->isStoreConditional()) { 1108 // The store is basically completed at this time. This 1109 // only works so long as the checker doesn't try to 1110 // verify the value in memory for stores. 1111 storeQueue[storeWBIdx].inst->setCompleted(); 1112 1113 if (cpu->checker) { 1114 cpu->checker->verify(storeQueue[storeWBIdx].inst); 1115 } 1116 } 1117 1118 if (needsTSO) { 1119 storeInFlight = true; 1120 } 1121 1122 incrStIdx(storeWBIdx); 1123} 1124 1125template <class Impl> 1126void 1127LSQUnit<Impl>::writeback(DynInstPtr &inst, PacketPtr pkt) 1128{ 1129 iewStage->wakeCPU(); 1130 1131 // Squashed instructions do not need to complete their access. 1132 if (inst->isSquashed()) { 1133 iewStage->decrWb(inst->seqNum); 1134 assert(!inst->isStore()); 1135 ++lsqIgnoredResponses; 1136 return; 1137 } 1138 1139 if (!inst->isExecuted()) { 1140 inst->setExecuted(); 1141 1142 // Complete access to copy data to proper place. 1143 inst->completeAcc(pkt); 1144 } 1145 1146 // Need to insert instruction into queue to commit 1147 iewStage->instToCommit(inst); 1148 1149 iewStage->activityThisCycle(); 1150 1151 // see if this load changed the PC 1152 iewStage->checkMisprediction(inst); 1153} 1154 1155template <class Impl> 1156void 1157LSQUnit<Impl>::completeStore(int store_idx) 1158{ 1159 assert(storeQueue[store_idx].inst); 1160 storeQueue[store_idx].completed = true; 1161 --storesToWB; 1162 // A bit conservative because a store completion may not free up entries, 1163 // but hopefully avoids two store completions in one cycle from making 1164 // the CPU tick twice. 1165 cpu->wakeCPU(); 1166 cpu->activityThisCycle(); 1167 1168 if (store_idx == storeHead) { 1169 do { 1170 incrStIdx(storeHead); 1171 1172 --stores; 1173 } while (storeQueue[storeHead].completed && 1174 storeHead != storeTail); 1175 1176 iewStage->updateLSQNextCycle = true; 1177 } 1178 1179 DPRINTF(LSQUnit, "Completing store [sn:%lli], idx:%i, store head " 1180 "idx:%i\n", 1181 storeQueue[store_idx].inst->seqNum, store_idx, storeHead); 1182 1183#if TRACING_ON 1184 if (DTRACE(O3PipeView)) { 1185 storeQueue[store_idx].inst->storeTick = 1186 curTick() - storeQueue[store_idx].inst->fetchTick; 1187 } 1188#endif 1189 1190 if (isStalled() && 1191 storeQueue[store_idx].inst->seqNum == stallingStoreIsn) { 1192 DPRINTF(LSQUnit, "Unstalling, stalling store [sn:%lli] " 1193 "load idx:%i\n", 1194 stallingStoreIsn, stallingLoadIdx); 1195 stalled = false; 1196 stallingStoreIsn = 0; 1197 iewStage->replayMemInst(loadQueue[stallingLoadIdx]); 1198 } 1199 1200 storeQueue[store_idx].inst->setCompleted(); 1201 1202 if (needsTSO) { 1203 storeInFlight = false; 1204 } 1205 1206 // Tell the checker we've completed this instruction. Some stores 1207 // may get reported twice to the checker, but the checker can 1208 // handle that case. 1209 if (cpu->checker) { 1210 cpu->checker->verify(storeQueue[store_idx].inst); 1211 } 1212} 1213 1214template <class Impl> 1215bool 1216LSQUnit<Impl>::sendStore(PacketPtr data_pkt) 1217{ 1218 if (!dcachePort->sendTimingReq(data_pkt)) { 1219 // Need to handle becoming blocked on a store. 1220 isStoreBlocked = true; 1221 ++lsqCacheBlocked; 1222 assert(retryPkt == NULL); 1223 retryPkt = data_pkt; 1224 lsq->setRetryTid(lsqID); 1225 return false; 1226 } 1227 return true; 1228} 1229 1230template <class Impl> 1231void 1232LSQUnit<Impl>::recvRetry() 1233{ 1234 if (isStoreBlocked) { 1235 DPRINTF(LSQUnit, "Receiving retry: store blocked\n"); 1236 assert(retryPkt != NULL); 1237 1238 LSQSenderState *state = 1239 dynamic_cast<LSQSenderState *>(retryPkt->senderState); 1240 1241 if (dcachePort->sendTimingReq(retryPkt)) { 1242 // Don't finish the store unless this is the last packet. 1243 if (!TheISA::HasUnalignedMemAcc || !state->pktToSend || 1244 state->pendingPacket == retryPkt) { 1245 state->pktToSend = false; 1246 storePostSend(retryPkt); 1247 } 1248 retryPkt = NULL; 1249 isStoreBlocked = false; 1250 lsq->setRetryTid(InvalidThreadID); 1251 1252 // Send any outstanding packet. 1253 if (TheISA::HasUnalignedMemAcc && state->pktToSend) { 1254 assert(state->pendingPacket); 1255 if (sendStore(state->pendingPacket)) { 1256 storePostSend(state->pendingPacket); 1257 } 1258 } 1259 } else { 1260 // Still blocked! 1261 ++lsqCacheBlocked; 1262 lsq->setRetryTid(lsqID); 1263 } 1264 } else if (isLoadBlocked) { 1265 DPRINTF(LSQUnit, "Loads squash themselves and all younger insts, " 1266 "no need to resend packet.\n"); 1267 } else { 1268 DPRINTF(LSQUnit, "Retry received but LSQ is no longer blocked.\n"); 1269 } 1270} 1271 1272template <class Impl> 1273inline void 1274LSQUnit<Impl>::incrStIdx(int &store_idx) const 1275{ 1276 if (++store_idx >= SQEntries) 1277 store_idx = 0; 1278} 1279 1280template <class Impl> 1281inline void 1282LSQUnit<Impl>::decrStIdx(int &store_idx) const 1283{ 1284 if (--store_idx < 0) 1285 store_idx += SQEntries; 1286} 1287 1288template <class Impl> 1289inline void 1290LSQUnit<Impl>::incrLdIdx(int &load_idx) const 1291{ 1292 if (++load_idx >= LQEntries) 1293 load_idx = 0; 1294} 1295 1296template <class Impl> 1297inline void 1298LSQUnit<Impl>::decrLdIdx(int &load_idx) const 1299{ 1300 if (--load_idx < 0) 1301 load_idx += LQEntries; 1302} 1303 1304template <class Impl> 1305void 1306LSQUnit<Impl>::dumpInsts() const 1307{ 1308 cprintf("Load store queue: Dumping instructions.\n"); 1309 cprintf("Load queue size: %i\n", loads); 1310 cprintf("Load queue: "); 1311 1312 int load_idx = loadHead; 1313 1314 while (load_idx != loadTail && loadQueue[load_idx]) { 1315 const DynInstPtr &inst(loadQueue[load_idx]); 1316 cprintf("%s.[sn:%i] ", inst->pcState(), inst->seqNum); 1317 1318 incrLdIdx(load_idx); 1319 } 1320 cprintf("\n"); 1321 1322 cprintf("Store queue size: %i\n", stores); 1323 cprintf("Store queue: "); 1324 1325 int store_idx = storeHead; 1326 1327 while (store_idx != storeTail && storeQueue[store_idx].inst) { 1328 const DynInstPtr &inst(storeQueue[store_idx].inst); 1329 cprintf("%s.[sn:%i] ", inst->pcState(), inst->seqNum); 1330 1331 incrStIdx(store_idx); 1332 } 1333 1334 cprintf("\n"); 1335} 1336 1337#endif//__CPU_O3_LSQ_UNIT_IMPL_HH__
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