1 |
2/* 3 * Copyright (c) 2010-2012 ARM Limited 4 * All rights reserved 5 * 6 * The license below extends only to copyright in the software and shall 7 * not be construed as granting a license to any other intellectual 8 * property including but not limited to intellectual property relating 9 * to a hardware implementation of the functionality of the software --- 176 unchanged lines hidden (view full) --- 186 memDepViolator = NULL; 187 188 blockedLoadSeqNum = 0; 189 190 stalled = false; 191 isLoadBlocked = false; 192 loadBlockedHandled = false; 193 |
194 cacheBlockMask = ~(cpu->cacheLineSize() - 1); |
195} 196 197template<class Impl> 198std::string 199LSQUnit<Impl>::name() const 200{ 201 if (Impl::MaxThreads == 1) { 202 return iewStage->name() + ".lsq"; --- 212 unchanged lines hidden (view full) --- 415} 416 417template <class Impl> 418void 419LSQUnit<Impl>::checkSnoop(PacketPtr pkt) 420{ 421 int load_idx = loadHead; 422 |
423 // Unlock the cpu-local monitor when the CPU sees a snoop to a locked 424 // address. The CPU can speculatively execute a LL operation after a pending 425 // SC operation in the pipeline and that can make the cache monitor the CPU 426 // is connected to valid while it really shouldn't be. 427 for (int x = 0; x < cpu->numActiveThreads(); x++) { 428 ThreadContext *tc = cpu->getContext(x); 429 bool no_squash = cpu->thread[x]->noSquashFromTC; 430 cpu->thread[x]->noSquashFromTC = true; --- 854 unchanged lines hidden --- |