1/* 2 * Copyright (c) 2010-2011 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 1166 unchanged lines hidden (view full) --- 1175 cpu->checker->verify(storeQueue[store_idx].inst); 1176 } 1177} 1178 1179template <class Impl> 1180bool 1181LSQUnit<Impl>::sendStore(PacketPtr data_pkt) 1182{ |
1183 if (!dcachePort->sendTimingReq(data_pkt)) { |
1184 // Need to handle becoming blocked on a store. 1185 isStoreBlocked = true; 1186 ++lsqCacheBlocked; 1187 assert(retryPkt == NULL); 1188 retryPkt = data_pkt; 1189 lsq->setRetryTid(lsqID); 1190 return false; 1191 } --- 6 unchanged lines hidden (view full) --- 1198{ 1199 if (isStoreBlocked) { 1200 DPRINTF(LSQUnit, "Receiving retry: store blocked\n"); 1201 assert(retryPkt != NULL); 1202 1203 LSQSenderState *state = 1204 dynamic_cast<LSQSenderState *>(retryPkt->senderState); 1205 |
1206 if (dcachePort->sendTimingReq(retryPkt)) { |
1207 // Don't finish the store unless this is the last packet. 1208 if (!TheISA::HasUnalignedMemAcc || !state->pktToSend || 1209 state->pendingPacket == retryPkt) { 1210 state->pktToSend = false; 1211 storePostSend(retryPkt); 1212 } 1213 retryPkt = NULL; 1214 isStoreBlocked = false; --- 83 unchanged lines hidden --- |