1/* 2 * Copyright (c) 2004-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 17 unchanged lines hidden (view full) --- 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Kevin Lim 29 * Korey Sewell 30 */ 31 32#include "config/use_checker.hh" 33 |
34#include "cpu/o3/lsq.hh" |
35#include "cpu/o3/lsq_unit.hh" 36#include "base/str.hh" 37#include "mem/packet.hh" 38#include "mem/request.hh" 39 40#if USE_CHECKER 41#include "cpu/checker/cpu.hh" 42#endif --- 49 unchanged lines hidden (view full) --- 92 } 93 } 94 95 delete state; 96 delete pkt; 97} 98 99template <class Impl> |
100LSQUnit<Impl>::LSQUnit() 101 : loads(0), stores(0), storesToWB(0), stalled(false), 102 isStoreBlocked(false), isLoadBlocked(false), 103 loadBlockedHandled(false) 104{ 105} 106 107template<class Impl> 108void |
109LSQUnit<Impl>::init(Params *params, LSQ *lsq_ptr, unsigned maxLQEntries, |
110 unsigned maxSQEntries, unsigned id) 111{ 112 DPRINTF(LSQUnit, "Creating LSQUnit%i object.\n",id); 113 114 switchedOut = false; 115 |
116 lsq = lsq_ptr; 117 |
118 lsqID = id; 119 120 // Add 1 for the sentinel entry (they are circular queues). 121 LQEntries = maxLQEntries + 1; 122 SQEntries = maxSQEntries + 1; 123 124 loadQueue.resize(LQEntries); 125 storeQueue.resize(SQEntries); 126 127 loadHead = loadTail = 0; 128 129 storeHead = storeWBIdx = storeTail = 0; 130 131 usedPorts = 0; 132 cachePorts = params->cachePorts; 133 |
134 memDepViolator = NULL; 135 136 blockedLoadSeqNum = 0; 137} 138 139template<class Impl> 140void 141LSQUnit<Impl>::setCPU(O3CPU *cpu_ptr) 142{ 143 cpu = cpu_ptr; |
144 145#if USE_CHECKER 146 if (cpu->checker) { 147 cpu->checker->setDcachePort(dcachePort); 148 } 149#endif 150} 151 --- 391 unchanged lines hidden (view full) --- 543LSQUnit<Impl>::writebackStores() 544{ 545 while (storesToWB > 0 && 546 storeWBIdx != storeTail && 547 storeQueue[storeWBIdx].inst && 548 storeQueue[storeWBIdx].canWB && 549 usedPorts < cachePorts) { 550 |
551 if (isStoreBlocked || lsq->cacheBlocked()) { |
552 DPRINTF(LSQUnit, "Unable to write back any more stores, cache" 553 " is blocked!\n"); 554 break; 555 } 556 557 // Store didn't write any data so no need to write it back to 558 // memory. 559 if (storeQueue[storeWBIdx].size == 0) { --- 306 unchanged lines hidden (view full) --- 866 867 if (dcachePort->sendTiming(retryPkt)) { 868 storePostSend(retryPkt); 869 retryPkt = NULL; 870 isStoreBlocked = false; 871 } else { 872 // Still blocked! 873 ++lsqCacheBlocked; |
874 lsq->setRetryTid(lsqID); |
875 } 876 } else if (isLoadBlocked) { 877 DPRINTF(LSQUnit, "Loads squash themselves and all younger insts, " 878 "no need to resend packet.\n"); 879 } else { 880 DPRINTF(LSQUnit, "Retry received but LSQ is no longer blocked.\n"); 881 } 882} --- 62 unchanged lines hidden --- |