1 2/* 3 * Copyright (c) 2010-2014, 2017-2018 ARM Limited 4 * Copyright (c) 2013 Advanced Micro Devices, Inc. 5 * All rights reserved 6 * 7 * The license below extends only to copyright in the software and shall 8 * not be construed as granting a license to any other intellectual --- 694 unchanged lines hidden (view full) --- 703 writebackBlockedStore(); 704 } 705 706 while (storesToWB > 0 && 707 storeWBIt.dereferenceable() && 708 storeWBIt->valid() && 709 storeWBIt->canWB() && 710 ((!needsTSO) || (!storeInFlight)) && |
711 lsq->cachePortAvailable(false)) { |
712 713 if (isStoreBlocked) { 714 DPRINTF(LSQUnit, "Unable to write back any more stores, cache" 715 " is blocked!\n"); 716 break; 717 } 718 719 // Store didn't write any data so no need to write it back to --- 315 unchanged lines hidden (view full) --- 1035bool 1036LSQUnit<Impl>::trySendPacket(bool isLoad, PacketPtr data_pkt) 1037{ 1038 bool ret = true; 1039 bool cache_got_blocked = false; 1040 1041 auto state = dynamic_cast<LSQSenderState*>(data_pkt->senderState); 1042 |
1043 if (!lsq->cacheBlocked() && 1044 lsq->cachePortAvailable(isLoad)) { |
1045 if (!dcachePort->sendTimingReq(data_pkt)) { 1046 ret = false; 1047 cache_got_blocked = true; 1048 } 1049 } else { 1050 ret = false; 1051 } 1052 1053 if (ret) { 1054 if (!isLoad) { |
1055 isStoreBlocked = false; 1056 } |
1057 lsq->cachePortBusy(isLoad); |
1058 state->outstanding++; 1059 state->request()->packetSent(); 1060 } else { 1061 if (cache_got_blocked) { 1062 lsq->cacheBlocked(true); 1063 ++lsqCacheBlocked; 1064 } 1065 if (!isLoad) { 1066 assert(state->request() == storeWBIt->request()); 1067 isStoreBlocked = true; 1068 } 1069 state->request()->packetNotSent(); 1070 } |
1071 return ret; 1072} 1073 1074template <class Impl> 1075void 1076LSQUnit<Impl>::recvRetry() 1077{ 1078 if (isStoreBlocked) { --- 38 unchanged lines hidden --- |