1 2/* 3 * Copyright (c) 2010-2014, 2017 ARM Limited 4 * Copyright (c) 2013 Advanced Micro Devices, Inc. 5 * All rights reserved 6 * 7 * The license below extends only to copyright in the software and shall 8 * not be construed as granting a license to any other intellectual --- 128 unchanged lines hidden (view full) --- 137 138 pkt->req->setAccessLatency(); 139 cpu->ppDataAccessComplete->notify(std::make_pair(inst, pkt)); 140 141 delete state; 142} 143 144template <class Impl> |
145LSQUnit<Impl>::LSQUnit(uint32_t lqEntries, uint32_t sqEntries) 146 : lsqID(-1), storeQueue(sqEntries+1), loadQueue(lqEntries+1), 147 LQEntries(lqEntries+1), SQEntries(lqEntries+1), 148 loads(0), stores(0), storesToWB(0), cacheBlockMask(0), stalled(false), |
149 isStoreBlocked(false), storeInFlight(false), hasPendingPkt(false), 150 pendingPkt(nullptr) 151{ 152} 153 154template<class Impl> 155void 156LSQUnit<Impl>::init(O3CPU *cpu_ptr, IEW *iew_ptr, DerivO3CPUParams *params, |
157 LSQ *lsq_ptr, unsigned id) |
158{ |
159 lsqID = id; 160 |
161 cpu = cpu_ptr; 162 iewStage = iew_ptr; 163 164 lsq = lsq_ptr; 165 |
166 DPRINTF(LSQUnit, "Creating LSQUnit%i object.\n",lsqID); |
167 |
168 depCheckShift = params->LSQDepCheckShift; 169 checkLoads = params->LSQCheckLoads; 170 cacheStorePorts = params->cacheStorePorts; 171 needsTSO = params->needsTSO; 172 173 resetState(); 174} 175 --- 1140 unchanged lines hidden --- |