1 2/* |
3 * Copyright (c) 2010-2014 ARM Limited |
4 * Copyright (c) 2013 Advanced Micro Devices, Inc. 5 * All rights reserved 6 * 7 * The license below extends only to copyright in the software and shall 8 * not be construed as granting a license to any other intellectual 9 * property including but not limited to intellectual property relating 10 * to a hardware implementation of the functionality of the software 11 * licensed hereunder. You may use the software subject to the license --- 82 unchanged lines hidden (view full) --- 94void 95LSQUnit<Impl>::completeDataAccess(PacketPtr pkt) 96{ 97 LSQSenderState *state = dynamic_cast<LSQSenderState *>(pkt->senderState); 98 DynInstPtr inst = state->inst; 99 DPRINTF(IEW, "Writeback event [sn:%lli].\n", inst->seqNum); 100 DPRINTF(Activity, "Activity: Writeback event [sn:%lli].\n", inst->seqNum); 101 |
102 if (state->cacheBlocked) { 103 // This is the first half of a previous split load, 104 // where the 2nd half blocked, ignore this response 105 DPRINTF(IEW, "[sn:%lli]: Response from first half of earlier " 106 "blocked split load recieved. Ignoring.\n", inst->seqNum); 107 delete state; 108 delete pkt->req; 109 delete pkt; 110 return; 111 } |
112 113 // If this is a split access, wait until all packets are received. 114 if (TheISA::HasUnalignedMemAcc && !state->complete()) { 115 delete pkt->req; 116 delete pkt; 117 return; 118 } 119 --- 24 unchanged lines hidden (view full) --- 144 delete state; 145 delete pkt->req; 146 delete pkt; 147} 148 149template <class Impl> 150LSQUnit<Impl>::LSQUnit() 151 : loads(0), stores(0), storesToWB(0), cacheBlockMask(0), stalled(false), |
152 isStoreBlocked(false), storeInFlight(false), hasPendingPkt(false) |
153{ 154} 155 156template<class Impl> 157void 158LSQUnit<Impl>::init(O3CPU *cpu_ptr, IEW *iew_ptr, DerivO3CPUParams *params, 159 LSQ *lsq_ptr, unsigned maxLQEntries, unsigned maxSQEntries, 160 unsigned id) --- 37 unchanged lines hidden (view full) --- 198 199 storeHead = storeWBIdx = storeTail = 0; 200 201 usedPorts = 0; 202 203 retryPkt = NULL; 204 memDepViolator = NULL; 205 |
206 stalled = false; |
207 208 cacheBlockMask = ~(cpu->cacheLineSize() - 1); 209} 210 211template<class Impl> 212std::string 213LSQUnit<Impl>::name() const 214{ --- 416 unchanged lines hidden (view full) --- 631 inst->seqNum, 632 (load_fault != NoFault ? "fault" : "predication")); 633 if (!(inst->hasRequest() && inst->uncacheable()) || 634 inst->isAtCommit()) { 635 inst->setExecuted(); 636 } 637 iewStage->instToCommit(inst); 638 iewStage->activityThisCycle(); |
639 } else { |
640 assert(inst->effAddrValid()); 641 int load_idx = inst->lqIdx; 642 incrLdIdx(load_idx); 643 644 if (checkLoads) 645 return checkViolations(load_idx, inst); 646 } 647 --- 138 unchanged lines hidden (view full) --- 786 787 while (storesToWB > 0 && 788 storeWBIdx != storeTail && 789 storeQueue[storeWBIdx].inst && 790 storeQueue[storeWBIdx].canWB && 791 ((!needsTSO) || (!storeInFlight)) && 792 usedPorts < cachePorts) { 793 |
794 if (isStoreBlocked) { |
795 DPRINTF(LSQUnit, "Unable to write back any more stores, cache" 796 " is blocked!\n"); 797 break; 798 } 799 800 // Store didn't write any data so no need to write it back to 801 // memory. 802 if (storeQueue[storeWBIdx].size == 0) { --- 220 unchanged lines hidden (view full) --- 1023 1024 // Inefficient! 1025 loadTail = load_idx; 1026 1027 decrLdIdx(load_idx); 1028 ++lsqSquashedLoads; 1029 } 1030 |
1031 if (memDepViolator && squashed_num < memDepViolator->seqNum) { 1032 memDepViolator = NULL; 1033 } 1034 1035 int store_idx = storeTail; 1036 decrStIdx(store_idx); 1037 1038 while (stores != 0 && --- 170 unchanged lines hidden (view full) --- 1209LSQUnit<Impl>::sendStore(PacketPtr data_pkt) 1210{ 1211 if (!dcachePort->sendTimingReq(data_pkt)) { 1212 // Need to handle becoming blocked on a store. 1213 isStoreBlocked = true; 1214 ++lsqCacheBlocked; 1215 assert(retryPkt == NULL); 1216 retryPkt = data_pkt; |
1217 return false; 1218 } 1219 return true; 1220} 1221 1222template <class Impl> 1223void 1224LSQUnit<Impl>::recvRetry() --- 9 unchanged lines hidden (view full) --- 1234 // Don't finish the store unless this is the last packet. 1235 if (!TheISA::HasUnalignedMemAcc || !state->pktToSend || 1236 state->pendingPacket == retryPkt) { 1237 state->pktToSend = false; 1238 storePostSend(retryPkt); 1239 } 1240 retryPkt = NULL; 1241 isStoreBlocked = false; |
1242 1243 // Send any outstanding packet. 1244 if (TheISA::HasUnalignedMemAcc && state->pktToSend) { 1245 assert(state->pendingPacket); 1246 if (sendStore(state->pendingPacket)) { 1247 storePostSend(state->pendingPacket); 1248 } 1249 } 1250 } else { 1251 // Still blocked! 1252 ++lsqCacheBlocked; |
1253 } |
1254 } 1255} 1256 1257template <class Impl> 1258inline void 1259LSQUnit<Impl>::incrStIdx(int &store_idx) const 1260{ 1261 if (++store_idx >= SQEntries) --- 61 unchanged lines hidden --- |