69,71c69
< if (!lsqPtr->isSwitchedOut()) {
< lsqPtr->writeback(inst, pkt);
< }
---
> assert(!lsqPtr->cpu->switchedOut());
72a71,72
> lsqPtr->writeback(inst, pkt);
>
105c105,106
< if (isSwitchedOut() || inst->isSquashed()) {
---
> assert(!cpu->switchedOut());
> if (inst->isSquashed()) {
150,153d150
< switchedOut = false;
<
< cacheBlockMask = 0;
<
166a164,165
> cachePorts = params->cachePorts;
> needsTSO = params->needsTSO;
167a167,176
> resetState();
> }
>
>
> template<class Impl>
> void
> LSQUnit<Impl>::resetState()
> {
> loads = stores = storesToWB = 0;
>
173d181
< cachePorts = params->cachePorts;
179c187,192
< needsTSO = params->needsTSO;
---
>
> stalled = false;
> isLoadBlocked = false;
> loadBlockedHandled = false;
>
> cacheBlockMask = 0;
261c274
< LSQUnit<Impl>::switchOut()
---
> LSQUnit<Impl>::drainSanityCheck() const
263,264c276
< switchedOut = true;
< for (int i = 0; i < loadQueue.size(); ++i) {
---
> for (int i = 0; i < loadQueue.size(); ++i)
266,267d277
< loadQueue[i] = NULL;
< }
269a280
> assert(!retryPkt);
276,294c287
< switchedOut = false;
< loads = stores = storesToWB = 0;
<
< loadHead = loadTail = 0;
<
< storeHead = storeWBIdx = storeTail = 0;
<
< usedPorts = 0;
<
< memDepViolator = NULL;
<
< blockedLoadSeqNum = 0;
<
< stalled = false;
< isLoadBlocked = false;
< loadBlockedHandled = false;
<
< // Just incase the memory system changed out from under us
< cacheBlockMask = 0;
---
> resetState();