718a719,721
> RequestPtr sreqLow = storeQueue[storeWBIdx].sreqLow;
> RequestPtr sreqHigh = storeQueue[storeWBIdx].sreqHigh;
>
744,746d746
< RequestPtr sreqLow = storeQueue[storeWBIdx].sreqLow;
< RequestPtr sreqHigh = storeQueue[storeWBIdx].sreqHigh;
<
797c797,817
< if (!sendStore(data_pkt)) {
---
> bool split =
> TheISA::HasUnalignedMemAcc && storeQueue[storeWBIdx].isSplit;
>
> ThreadContext *thread = cpu->tcBase(lsqID);
>
> if (req->isMmappedIpr()) {
> assert(!inst->isStoreConditional());
> TheISA::handleIprWrite(thread, data_pkt);
> delete data_pkt;
> if (split) {
> assert(snd_data_pkt->req->isMmappedIpr());
> TheISA::handleIprWrite(thread, snd_data_pkt);
> delete snd_data_pkt;
> delete sreqLow;
> delete sreqHigh;
> }
> delete state;
> delete req;
> completeStore(storeWBIdx);
> incrStIdx(storeWBIdx);
> } else if (!sendStore(data_pkt)) {
803c823
< if (TheISA::HasUnalignedMemAcc && storeQueue[storeWBIdx].isSplit) {
---
> if (split) {
810c830
< if (TheISA::HasUnalignedMemAcc && storeQueue[storeWBIdx].isSplit) {
---
> if (split) {