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> LSQUnit<Impl>::regStats()
> {
> lsqForwLoads
> .name(name() + ".forwLoads")
> .desc("Number of loads that had data forwarded from stores");
>
> invAddrLoads
> .name(name() + ".invAddrLoads")
> .desc("Number of loads ignored due to an invalid address");
>
> lsqSquashedLoads
> .name(name() + ".squashedLoads")
> .desc("Number of loads squashed");
>
> lsqIgnoredResponses
> .name(name() + ".ignoredResponses")
> .desc("Number of memory responses ignored because the instruction is squashed");
>
> lsqSquashedStores
> .name(name() + ".squashedStores")
> .desc("Number of stores squashed");
>
> invAddrSwpfs
> .name(name() + ".invAddrSwpfs")
> .desc("Number of software prefetches ignored due to an invalid address");
>
> lsqBlockedLoads
> .name(name() + ".blockedLoads")
> .desc("Number of blocked loads due to partial load-store forwarding");
>
> lsqRescheduledLoads
> .name(name() + ".rescheduledLoads")
> .desc("Number of loads that were rescheduled");
>
> lsqCacheBlocked
> .name(name() + ".cacheBlocked")
> .desc("Number of times an access to memory failed due to the cache being blocked");
> }
>
> template<class Impl>
> void
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<
---
> ++lsqCacheBlocked;
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> ++lsqSquashedLoads;
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> ++lsqSquashedStores;
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> ++lsqIgnoredResponses;
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> ++lsqCacheBlocked;