128,139c128
< panic("Retry unsupported for now!");
< // we shouldn't get a retry unless we have a packet that we're
< // waiting to transmit
< /*
< assert(cpu->dcache_pkt != NULL);
< assert(cpu->_status == DcacheRetry);
< PacketPtr tmp = cpu->dcache_pkt;
< if (sendTiming(tmp)) {
< cpu->_status = DcacheWaitResponse;
< cpu->dcache_pkt = NULL;
< }
< */
---
> lsq->recvRetry();
617a607,626
> // @todo: Remove this SC hack once the memory system handles it.
> if (req->getFlags() & LOCKED) {
> if (req->getFlags() & UNCACHEABLE) {
> req->setScResult(2);
> } else {
> if (cpu->lockFlag) {
> req->setScResult(1);
> } else {
> req->setScResult(0);
> // Hack: Instantly complete this store.
> completeDataAccess(data_pkt);
> incrStIdx(storeWBIdx);
> continue;
> }
> }
> } else {
> // Non-store conditionals do not need a writeback.
> state->noWB = true;
> }
>
621,630d629
< } else {
< if (isStalled() &&
< storeQueue[storeWBIdx].inst->seqNum == stallingStoreIsn) {
< DPRINTF(LSQUnit, "Unstalling, stalling store [sn:%lli] "
< "load idx:%i\n",
< stallingStoreIsn, stallingLoadIdx);
< stalled = false;
< stallingStoreIsn = 0;
< iewStage->replayMemInst(loadQueue[stallingLoadIdx]);
< }
632,666c631,634
< if (!(req->getFlags() & LOCKED)) {
< assert(!storeQueue[storeWBIdx].inst->isStoreConditional());
< // Non-store conditionals do not need a writeback.
< state->noWB = true;
<
< // The store is basically completed at this time. This
< // only works so long as the checker doesn't try to
< // verify the value in memory for stores.
< storeQueue[storeWBIdx].inst->setCompleted();
< if (cpu->checker) {
< cpu->checker->tick(storeQueue[storeWBIdx].inst);
< }
< }
<
< if (data_pkt->result != Packet::Success) {
< DPRINTF(LSQUnit,"D-Cache Write Miss on idx:%i!\n",
< storeWBIdx);
<
< DPRINTF(Activity, "Active st accessing mem miss [sn:%lli]\n",
< storeQueue[storeWBIdx].inst->seqNum);
<
< //mshrSeqNums.push_back(storeQueue[storeWBIdx].inst->seqNum);
<
< //DPRINTF(LSQUnit, "Added MSHR. count = %i\n",mshrSeqNums.size());
<
< // @todo: Increment stat here.
< } else {
< DPRINTF(LSQUnit,"D-Cache: Write Hit on idx:%i !\n",
< storeWBIdx);
<
< DPRINTF(Activity, "Active st accessing mem hit [sn:%lli]\n",
< storeQueue[storeWBIdx].inst->seqNum);
< }
<
< incrStIdx(storeWBIdx);
---
> assert(sendingPkt == NULL);
> sendingPkt = data_pkt;
> } else {
> storePostSend(data_pkt);
771a740,786
> LSQUnit<Impl>::storePostSend(Packet *pkt)
> {
> if (isStalled() &&
> storeQueue[storeWBIdx].inst->seqNum == stallingStoreIsn) {
> DPRINTF(LSQUnit, "Unstalling, stalling store [sn:%lli] "
> "load idx:%i\n",
> stallingStoreIsn, stallingLoadIdx);
> stalled = false;
> stallingStoreIsn = 0;
> iewStage->replayMemInst(loadQueue[stallingLoadIdx]);
> }
>
> if (!storeQueue[storeWBIdx].inst->isStoreConditional()) {
> // The store is basically completed at this time. This
> // only works so long as the checker doesn't try to
> // verify the value in memory for stores.
> storeQueue[storeWBIdx].inst->setCompleted();
> if (cpu->checker) {
> cpu->checker->tick(storeQueue[storeWBIdx].inst);
> }
> }
>
> if (pkt->result != Packet::Success) {
> DPRINTF(LSQUnit,"D-Cache Write Miss on idx:%i!\n",
> storeWBIdx);
>
> DPRINTF(Activity, "Active st accessing mem miss [sn:%lli]\n",
> storeQueue[storeWBIdx].inst->seqNum);
>
> //mshrSeqNums.push_back(storeQueue[storeWBIdx].inst->seqNum);
>
> //DPRINTF(LSQUnit, "Added MSHR. count = %i\n",mshrSeqNums.size());
>
> // @todo: Increment stat here.
> } else {
> DPRINTF(LSQUnit,"D-Cache: Write Hit on idx:%i !\n",
> storeWBIdx);
>
> DPRINTF(Activity, "Active st accessing mem hit [sn:%lli]\n",
> storeQueue[storeWBIdx].inst->seqNum);
> }
>
> incrStIdx(storeWBIdx);
> }
>
> template <class Impl>
> void
842a858,879
> void
> LSQUnit<Impl>::recvRetry()
> {
> assert(sendingPkt != NULL);
>
> if (isStoreBlocked) {
> if (dcachePort->sendTiming(sendingPkt)) {
> storePostSend(sendingPkt);
> sendingPkt = NULL;
> isStoreBlocked = false;
> } else {
> // Still blocked!
> }
> } else if (isLoadBlocked) {
> DPRINTF(LSQUnit, "Loads squash themselves and all younger insts, "
> "no need to resend packet.\n");
> } else {
> DPRINTF(LSQUnit, "Retry received but LSQ is no longer blocked.\n");
> }
> }
>
> template <class Impl>