35,36c35,37
< void
< LSQUnit<Impl>::completeDataAccess(PacketPtr pkt)
---
> LSQUnit<Impl>::WritebackEvent::WritebackEvent(DynInstPtr &_inst, PacketPtr _pkt,
> LSQUnit *lsq_ptr)
> : Event(&mainEventQueue), inst(_inst), pkt(_pkt), lsqPtr(lsq_ptr)
38,40c39,40
< /*
< DPRINTF(IEW, "Load writeback event [sn:%lli]\n", inst->seqNum);
< DPRINTF(Activity, "Activity: Ld Writeback event [sn:%lli]\n", inst->seqNum);
---
> this->setFlags(Event::AutoDelete);
> }
42,50c42,47
< //iewStage->ldstQueue.removeMSHR(inst->threadNumber,inst->seqNum);
<
< if (iewStage->isSwitchedOut()) {
< inst = NULL;
< return;
< } else if (inst->isSquashed()) {
< iewStage->wakeCPU();
< inst = NULL;
< return;
---
> template<class Impl>
> void
> LSQUnit<Impl>::WritebackEvent::process()
> {
> if (!lsqPtr->isSwitchedOut()) {
> lsqPtr->writeback(inst, pkt);
51a49,50
> delete pkt;
> }
53,68c52,56
< iewStage->wakeCPU();
<
< if (!inst->isExecuted()) {
< inst->setExecuted();
<
< // Complete access to copy data to proper place.
< inst->completeAcc();
< }
<
< // Need to insert instruction into queue to commit
< iewStage->instToCommit(inst);
<
< iewStage->activityThisCycle();
<
< inst = NULL;
< */
---
> template<class Impl>
> const char *
> LSQUnit<Impl>::WritebackEvent::description()
> {
> return "Store writeback event";
73c61
< LSQUnit<Impl>::completeStoreDataAccess(DynInstPtr &inst)
---
> LSQUnit<Impl>::completeDataAccess(PacketPtr pkt)
75,77c63,66
< /*
< DPRINTF(LSQ, "Cache miss complete for store idx:%i\n", storeIdx);
< DPRINTF(Activity, "Activity: st writeback event idx:%i\n", storeIdx);
---
> LSQSenderState *state = dynamic_cast<LSQSenderState *>(pkt->senderState);
> DynInstPtr inst = state->inst;
> DPRINTF(IEW, "Writeback event [sn:%lli]\n", inst->seqNum);
> // DPRINTF(Activity, "Activity: Ld Writeback event [sn:%lli]\n", inst->seqNum);
79c68
< //lsqPtr->removeMSHR(lsqPtr->storeQueue[storeIdx].inst->seqNum);
---
> //iewStage->ldstQueue.removeMSHR(inst->threadNumber,inst->seqNum);
81,84c70,72
< if (lsqPtr->isSwitchedOut()) {
< if (wbEvent)
< delete wbEvent;
<
---
> if (isSwitchedOut() || inst->isSquashed()) {
> delete state;
> delete pkt;
85a74,81
> } else {
> if (!state->noWB) {
> writeback(inst, pkt);
> }
>
> if (inst->isStore()) {
> completeStore(state->idx);
> }
88,93c84,85
< lsqPtr->cpu->wakeCPU();
<
< if (wb)
< lsqPtr->completeDataAccess(storeIdx);
< lsqPtr->completeStore(storeIdx);
< */
---
> delete state;
> delete pkt;
149c141,142
< : loads(0), stores(0), storesToWB(0), stalled(false), isLoadBlocked(false),
---
> : loads(0), stores(0), storesToWB(0), stalled(false),
> isStoreBlocked(false), isLoadBlocked(false),
179,181c172
< Port *mem_dport = params->mem->getPort("");
< dcachePort->setPeer(mem_dport);
< mem_dport->setPeer(dcachePort);
---
> mem = params->mem;
193a185,188
>
> Port *mem_dport = mem->getPort("");
> dcachePort->setPeer(mem_dport);
> mem_dport->setPeer(dcachePort);
449d443
< // Fault store_fault = store_inst->execute();
564a559,564
> if (isStoreBlocked) {
> DPRINTF(LSQUnit, "Unable to write back any more stores, cache"
> " is blocked!\n");
> break;
> }
>
574,580c574
< /*
< if (dcacheInterface && dcacheInterface->isBlocked()) {
< DPRINTF(LSQUnit, "Unable to write back any more stores, cache"
< " is blocked!\n");
< break;
< }
< */
---
>
599c593,594
< memcpy(inst->memData, (uint8_t *)&storeQueue[storeWBIdx].data, req->getSize());
---
> memcpy(inst->memData, (uint8_t *)&storeQueue[storeWBIdx].data,
> req->getSize());
603a599,604
> LSQSenderState *state = new LSQSenderState;
> state->isLoad = false;
> state->idx = storeWBIdx;
> state->inst = inst;
> data_pkt->senderState = state;
>
611a613
> isStoreBlocked = true;
613,616d614
< /*
< StoreCompletionEvent *store_event = new
< StoreCompletionEvent(storeWBIdx, NULL, this);
< */
626,635c624,628
< /*
< typename LdWritebackEvent *wb = NULL;
< if (req->flags & LOCKED) {
< // Stx_C should not generate a system port transaction
< // if it misses in the cache, but that might be hard
< // to accomplish without explicit cache support.
< wb = new typename
< LdWritebackEvent(storeQueue[storeWBIdx].inst,
< iewStage);
< store_event->wbEvent = wb;
---
>
> if (!(req->getFlags() & LOCKED)) {
> assert(!storeQueue[storeWBIdx].inst->isStoreConditional());
> // Non-store conditionals do not need a writeback.
> state->noWB = true;
637c630
< */
---
>
763a757,781
> LSQUnit<Impl>::writeback(DynInstPtr &inst, PacketPtr pkt)
> {
> iewStage->wakeCPU();
>
> // Squashed instructions do not need to complete their access.
> if (inst->isSquashed()) {
> assert(!inst->isStore());
> return;
> }
>
> if (!inst->isExecuted()) {
> inst->setExecuted();
>
> // Complete access to copy data to proper place.
> inst->completeAcc(pkt);
> }
>
> // Need to insert instruction into queue to commit
> iewStage->instToCommit(inst);
>
> iewStage->activityThisCycle();
> }
>
> template <class Impl>
> void