3c3
< * Copyright (c) 2010-2014 ARM Limited
---
> * Copyright (c) 2010-2014, 2017 ARM Limited
118a119,121
> // Only loads and store conditionals perform the writeback
> // after receving the response from the memory
> assert(inst->isLoad() || inst->isStoreConditional());
901,906d903
< if (cpu->checker) {
< // Make sure to set the LLSC data for verification
< // if checker is loaded
< inst->reqToVerify->setExtraData(0);
< inst->completeAcc(data_pkt);
< }
1214c1211,1215
< if (cpu->checker) {
---
>
> // Store conditionals cannot be sent to the checker yet, they have
> // to update the misc registers first which should take place
> // when they commit
> if (cpu->checker && !storeQueue[store_idx].inst->isStoreConditional()) {