54#include "mem/packet.hh" 55#include "mem/request.hh" 56 57template<class Impl> 58LSQUnit<Impl>::WritebackEvent::WritebackEvent(DynInstPtr &_inst, PacketPtr _pkt, 59 LSQUnit *lsq_ptr) 60 : Event(Default_Pri, AutoDelete), 61 inst(_inst), pkt(_pkt), lsqPtr(lsq_ptr) 62{ 63} 64 65template<class Impl> 66void 67LSQUnit<Impl>::WritebackEvent::process() 68{ 69 assert(!lsqPtr->cpu->switchedOut()); 70 71 lsqPtr->writeback(inst, pkt); 72 73 if (pkt->senderState) 74 delete pkt->senderState; 75 76 delete pkt->req; 77 delete pkt; 78} 79 80template<class Impl> 81const char * 82LSQUnit<Impl>::WritebackEvent::description() const 83{ 84 return "Store writeback"; 85} 86 87template<class Impl> 88void 89LSQUnit<Impl>::completeDataAccess(PacketPtr pkt) 90{ 91 LSQSenderState *state = dynamic_cast<LSQSenderState *>(pkt->senderState); 92 DynInstPtr inst = state->inst; 93 DPRINTF(IEW, "Writeback event [sn:%lli].\n", inst->seqNum); 94 DPRINTF(Activity, "Activity: Writeback event [sn:%lli].\n", inst->seqNum); 95 96 //iewStage->ldstQueue.removeMSHR(inst->threadNumber,inst->seqNum); 97 98 // If this is a split access, wait until all packets are received. 99 if (TheISA::HasUnalignedMemAcc && !state->complete()) { 100 delete pkt->req; 101 delete pkt; 102 return; 103 } 104 105 assert(!cpu->switchedOut()); 106 if (inst->isSquashed()) { 107 iewStage->decrWb(inst->seqNum); 108 } else { 109 if (!state->noWB) { 110 if (!TheISA::HasUnalignedMemAcc || !state->isSplit || 111 !state->isLoad) { 112 writeback(inst, pkt); 113 } else { 114 writeback(inst, state->mainPkt); 115 } 116 } 117 118 if (inst->isStore()) { 119 completeStore(state->idx); 120 } 121 } 122 123 if (TheISA::HasUnalignedMemAcc && state->isSplit && state->isLoad) { 124 delete state->mainPkt->req; 125 delete state->mainPkt; 126 } 127 delete state; 128 delete pkt->req; 129 delete pkt; 130} 131 132template <class Impl> 133LSQUnit<Impl>::LSQUnit() 134 : loads(0), stores(0), storesToWB(0), cacheBlockMask(0), stalled(false), 135 isStoreBlocked(false), isLoadBlocked(false), 136 loadBlockedHandled(false), storeInFlight(false), hasPendingPkt(false) 137{ 138} 139 140template<class Impl> 141void 142LSQUnit<Impl>::init(O3CPU *cpu_ptr, IEW *iew_ptr, DerivO3CPUParams *params, 143 LSQ *lsq_ptr, unsigned maxLQEntries, unsigned maxSQEntries, 144 unsigned id) 145{ 146 cpu = cpu_ptr; 147 iewStage = iew_ptr; 148 149 DPRINTF(LSQUnit, "Creating LSQUnit%i object.\n",id); 150 151 lsq = lsq_ptr; 152 153 lsqID = id; 154 155 // Add 1 for the sentinel entry (they are circular queues). 156 LQEntries = maxLQEntries + 1; 157 SQEntries = maxSQEntries + 1; 158 159 loadQueue.resize(LQEntries); 160 storeQueue.resize(SQEntries); 161 162 depCheckShift = params->LSQDepCheckShift; 163 checkLoads = params->LSQCheckLoads; 164 cachePorts = params->cachePorts; 165 needsTSO = params->needsTSO; 166 167 resetState(); 168} 169 170 171template<class Impl> 172void 173LSQUnit<Impl>::resetState() 174{ 175 loads = stores = storesToWB = 0; 176 177 loadHead = loadTail = 0; 178 179 storeHead = storeWBIdx = storeTail = 0; 180 181 usedPorts = 0; 182 183 retryPkt = NULL; 184 memDepViolator = NULL; 185 186 blockedLoadSeqNum = 0; 187 188 stalled = false; 189 isLoadBlocked = false; 190 loadBlockedHandled = false; 191 192 cacheBlockMask = 0; 193} 194 195template<class Impl> 196std::string 197LSQUnit<Impl>::name() const 198{ 199 if (Impl::MaxThreads == 1) { 200 return iewStage->name() + ".lsq"; 201 } else { 202 return iewStage->name() + ".lsq.thread" + to_string(lsqID); 203 } 204} 205 206template<class Impl> 207void 208LSQUnit<Impl>::regStats() 209{ 210 lsqForwLoads 211 .name(name() + ".forwLoads") 212 .desc("Number of loads that had data forwarded from stores"); 213 214 invAddrLoads 215 .name(name() + ".invAddrLoads") 216 .desc("Number of loads ignored due to an invalid address"); 217 218 lsqSquashedLoads 219 .name(name() + ".squashedLoads") 220 .desc("Number of loads squashed"); 221 222 lsqIgnoredResponses 223 .name(name() + ".ignoredResponses") 224 .desc("Number of memory responses ignored because the instruction is squashed"); 225 226 lsqMemOrderViolation 227 .name(name() + ".memOrderViolation") 228 .desc("Number of memory ordering violations"); 229 230 lsqSquashedStores 231 .name(name() + ".squashedStores") 232 .desc("Number of stores squashed"); 233 234 invAddrSwpfs 235 .name(name() + ".invAddrSwpfs") 236 .desc("Number of software prefetches ignored due to an invalid address"); 237 238 lsqBlockedLoads 239 .name(name() + ".blockedLoads") 240 .desc("Number of blocked loads due to partial load-store forwarding"); 241 242 lsqRescheduledLoads 243 .name(name() + ".rescheduledLoads") 244 .desc("Number of loads that were rescheduled"); 245 246 lsqCacheBlocked 247 .name(name() + ".cacheBlocked") 248 .desc("Number of times an access to memory failed due to the cache being blocked"); 249} 250 251template<class Impl> 252void 253LSQUnit<Impl>::setDcachePort(MasterPort *dcache_port) 254{ 255 dcachePort = dcache_port; 256} 257 258template<class Impl> 259void 260LSQUnit<Impl>::clearLQ() 261{ 262 loadQueue.clear(); 263} 264 265template<class Impl> 266void 267LSQUnit<Impl>::clearSQ() 268{ 269 storeQueue.clear(); 270} 271 272template<class Impl> 273void 274LSQUnit<Impl>::drainSanityCheck() const 275{ 276 for (int i = 0; i < loadQueue.size(); ++i) 277 assert(!loadQueue[i]); 278 279 assert(storesToWB == 0); 280 assert(!retryPkt); 281} 282 283template<class Impl> 284void 285LSQUnit<Impl>::takeOverFrom() 286{ 287 resetState(); 288} 289 290template<class Impl> 291void 292LSQUnit<Impl>::resizeLQ(unsigned size) 293{ 294 unsigned size_plus_sentinel = size + 1; 295 assert(size_plus_sentinel >= LQEntries); 296 297 if (size_plus_sentinel > LQEntries) { 298 while (size_plus_sentinel > loadQueue.size()) { 299 DynInstPtr dummy; 300 loadQueue.push_back(dummy); 301 LQEntries++; 302 } 303 } else { 304 LQEntries = size_plus_sentinel; 305 } 306 307} 308 309template<class Impl> 310void 311LSQUnit<Impl>::resizeSQ(unsigned size) 312{ 313 unsigned size_plus_sentinel = size + 1; 314 if (size_plus_sentinel > SQEntries) { 315 while (size_plus_sentinel > storeQueue.size()) { 316 SQEntry dummy; 317 storeQueue.push_back(dummy); 318 SQEntries++; 319 } 320 } else { 321 SQEntries = size_plus_sentinel; 322 } 323} 324 325template <class Impl> 326void 327LSQUnit<Impl>::insert(DynInstPtr &inst) 328{ 329 assert(inst->isMemRef()); 330 331 assert(inst->isLoad() || inst->isStore()); 332 333 if (inst->isLoad()) { 334 insertLoad(inst); 335 } else { 336 insertStore(inst); 337 } 338 339 inst->setInLSQ(); 340} 341 342template <class Impl> 343void 344LSQUnit<Impl>::insertLoad(DynInstPtr &load_inst) 345{ 346 assert((loadTail + 1) % LQEntries != loadHead); 347 assert(loads < LQEntries); 348 349 DPRINTF(LSQUnit, "Inserting load PC %s, idx:%i [sn:%lli]\n", 350 load_inst->pcState(), loadTail, load_inst->seqNum); 351 352 load_inst->lqIdx = loadTail; 353 354 if (stores == 0) { 355 load_inst->sqIdx = -1; 356 } else { 357 load_inst->sqIdx = storeTail; 358 } 359 360 loadQueue[loadTail] = load_inst; 361 362 incrLdIdx(loadTail); 363 364 ++loads; 365} 366 367template <class Impl> 368void 369LSQUnit<Impl>::insertStore(DynInstPtr &store_inst) 370{ 371 // Make sure it is not full before inserting an instruction. 372 assert((storeTail + 1) % SQEntries != storeHead); 373 assert(stores < SQEntries); 374 375 DPRINTF(LSQUnit, "Inserting store PC %s, idx:%i [sn:%lli]\n", 376 store_inst->pcState(), storeTail, store_inst->seqNum); 377 378 store_inst->sqIdx = storeTail; 379 store_inst->lqIdx = loadTail; 380 381 storeQueue[storeTail] = SQEntry(store_inst); 382 383 incrStIdx(storeTail); 384 385 ++stores; 386} 387 388template <class Impl> 389typename Impl::DynInstPtr 390LSQUnit<Impl>::getMemDepViolator() 391{ 392 DynInstPtr temp = memDepViolator; 393 394 memDepViolator = NULL; 395 396 return temp; 397} 398 399template <class Impl> 400unsigned 401LSQUnit<Impl>::numFreeEntries() 402{ 403 unsigned free_lq_entries = LQEntries - loads; 404 unsigned free_sq_entries = SQEntries - stores; 405 406 // Both the LQ and SQ entries have an extra dummy entry to differentiate 407 // empty/full conditions. Subtract 1 from the free entries. 408 if (free_lq_entries < free_sq_entries) { 409 return free_lq_entries - 1; 410 } else { 411 return free_sq_entries - 1; 412 } 413} 414 415template <class Impl> 416void 417LSQUnit<Impl>::checkSnoop(PacketPtr pkt) 418{ 419 int load_idx = loadHead; 420 421 if (!cacheBlockMask) { 422 assert(dcachePort); 423 Addr bs = dcachePort->peerBlockSize(); 424 425 // Make sure we actually got a size 426 assert(bs != 0); 427 428 cacheBlockMask = ~(bs - 1); 429 } 430 431 // Unlock the cpu-local monitor when the CPU sees a snoop to a locked 432 // address. The CPU can speculatively execute a LL operation after a pending 433 // SC operation in the pipeline and that can make the cache monitor the CPU 434 // is connected to valid while it really shouldn't be. 435 for (int x = 0; x < cpu->numActiveThreads(); x++) { 436 ThreadContext *tc = cpu->getContext(x); 437 bool no_squash = cpu->thread[x]->noSquashFromTC; 438 cpu->thread[x]->noSquashFromTC = true; 439 TheISA::handleLockedSnoop(tc, pkt, cacheBlockMask); 440 cpu->thread[x]->noSquashFromTC = no_squash; 441 } 442 443 // If this is the only load in the LSQ we don't care 444 if (load_idx == loadTail) 445 return; 446 incrLdIdx(load_idx); 447 448 DPRINTF(LSQUnit, "Got snoop for address %#x\n", pkt->getAddr()); 449 Addr invalidate_addr = pkt->getAddr() & cacheBlockMask; 450 while (load_idx != loadTail) { 451 DynInstPtr ld_inst = loadQueue[load_idx]; 452 453 if (!ld_inst->effAddrValid() || ld_inst->uncacheable()) { 454 incrLdIdx(load_idx); 455 continue; 456 } 457 458 Addr load_addr = ld_inst->physEffAddr & cacheBlockMask; 459 DPRINTF(LSQUnit, "-- inst [sn:%lli] load_addr: %#x to pktAddr:%#x\n", 460 ld_inst->seqNum, load_addr, invalidate_addr); 461 462 if (load_addr == invalidate_addr) { 463 if (ld_inst->possibleLoadViolation()) { 464 DPRINTF(LSQUnit, "Conflicting load at addr %#x [sn:%lli]\n", 465 ld_inst->physEffAddr, pkt->getAddr(), ld_inst->seqNum); 466 467 // Mark the load for re-execution 468 ld_inst->fault = new ReExec; 469 } else { 470 // If a older load checks this and it's true 471 // then we might have missed the snoop 472 // in which case we need to invalidate to be sure 473 ld_inst->hitExternalSnoop(true); 474 } 475 } 476 incrLdIdx(load_idx); 477 } 478 return; 479} 480 481template <class Impl> 482Fault 483LSQUnit<Impl>::checkViolations(int load_idx, DynInstPtr &inst) 484{ 485 Addr inst_eff_addr1 = inst->effAddr >> depCheckShift; 486 Addr inst_eff_addr2 = (inst->effAddr + inst->effSize - 1) >> depCheckShift; 487 488 /** @todo in theory you only need to check an instruction that has executed 489 * however, there isn't a good way in the pipeline at the moment to check 490 * all instructions that will execute before the store writes back. Thus, 491 * like the implementation that came before it, we're overly conservative. 492 */ 493 while (load_idx != loadTail) { 494 DynInstPtr ld_inst = loadQueue[load_idx]; 495 if (!ld_inst->effAddrValid() || ld_inst->uncacheable()) { 496 incrLdIdx(load_idx); 497 continue; 498 } 499 500 Addr ld_eff_addr1 = ld_inst->effAddr >> depCheckShift; 501 Addr ld_eff_addr2 = 502 (ld_inst->effAddr + ld_inst->effSize - 1) >> depCheckShift; 503 504 if (inst_eff_addr2 >= ld_eff_addr1 && inst_eff_addr1 <= ld_eff_addr2) { 505 if (inst->isLoad()) { 506 // If this load is to the same block as an external snoop 507 // invalidate that we've observed then the load needs to be 508 // squashed as it could have newer data 509 if (ld_inst->hitExternalSnoop()) { 510 if (!memDepViolator || 511 ld_inst->seqNum < memDepViolator->seqNum) { 512 DPRINTF(LSQUnit, "Detected fault with inst [sn:%lli] " 513 "and [sn:%lli] at address %#x\n", 514 inst->seqNum, ld_inst->seqNum, ld_eff_addr1); 515 memDepViolator = ld_inst; 516 517 ++lsqMemOrderViolation; 518 519 return new GenericISA::M5PanicFault( 520 "Detected fault with inst [sn:%lli] and " 521 "[sn:%lli] at address %#x\n", 522 inst->seqNum, ld_inst->seqNum, ld_eff_addr1); 523 } 524 } 525 526 // Otherwise, mark the load has a possible load violation 527 // and if we see a snoop before it's commited, we need to squash 528 ld_inst->possibleLoadViolation(true); 529 DPRINTF(LSQUnit, "Found possible load violaiton at addr: %#x" 530 " between instructions [sn:%lli] and [sn:%lli]\n", 531 inst_eff_addr1, inst->seqNum, ld_inst->seqNum); 532 } else { 533 // A load/store incorrectly passed this store. 534 // Check if we already have a violator, or if it's newer 535 // squash and refetch. 536 if (memDepViolator && ld_inst->seqNum > memDepViolator->seqNum) 537 break; 538 539 DPRINTF(LSQUnit, "Detected fault with inst [sn:%lli] and " 540 "[sn:%lli] at address %#x\n", 541 inst->seqNum, ld_inst->seqNum, ld_eff_addr1); 542 memDepViolator = ld_inst; 543 544 ++lsqMemOrderViolation; 545 546 return new GenericISA::M5PanicFault("Detected fault with " 547 "inst [sn:%lli] and [sn:%lli] at address %#x\n", 548 inst->seqNum, ld_inst->seqNum, ld_eff_addr1); 549 } 550 } 551 552 incrLdIdx(load_idx); 553 } 554 return NoFault; 555} 556 557 558 559 560template <class Impl> 561Fault 562LSQUnit<Impl>::executeLoad(DynInstPtr &inst) 563{ 564 using namespace TheISA; 565 // Execute a specific load. 566 Fault load_fault = NoFault; 567 568 DPRINTF(LSQUnit, "Executing load PC %s, [sn:%lli]\n", 569 inst->pcState(), inst->seqNum); 570 571 assert(!inst->isSquashed()); 572 573 load_fault = inst->initiateAcc(); 574 575 if (inst->isTranslationDelayed() && 576 load_fault == NoFault) 577 return load_fault; 578 579 // If the instruction faulted or predicated false, then we need to send it 580 // along to commit without the instruction completing. 581 if (load_fault != NoFault || inst->readPredicate() == false) { 582 // Send this instruction to commit, also make sure iew stage 583 // realizes there is activity. 584 // Mark it as executed unless it is an uncached load that 585 // needs to hit the head of commit. 586 if (inst->readPredicate() == false) 587 inst->forwardOldRegs(); 588 DPRINTF(LSQUnit, "Load [sn:%lli] not executed from %s\n", 589 inst->seqNum, 590 (load_fault != NoFault ? "fault" : "predication")); 591 if (!(inst->hasRequest() && inst->uncacheable()) || 592 inst->isAtCommit()) { 593 inst->setExecuted(); 594 } 595 iewStage->instToCommit(inst); 596 iewStage->activityThisCycle(); 597 } else if (!loadBlocked()) { 598 assert(inst->effAddrValid()); 599 int load_idx = inst->lqIdx; 600 incrLdIdx(load_idx); 601 602 if (checkLoads) 603 return checkViolations(load_idx, inst); 604 } 605 606 return load_fault; 607} 608 609template <class Impl> 610Fault 611LSQUnit<Impl>::executeStore(DynInstPtr &store_inst) 612{ 613 using namespace TheISA; 614 // Make sure that a store exists. 615 assert(stores != 0); 616 617 int store_idx = store_inst->sqIdx; 618 619 DPRINTF(LSQUnit, "Executing store PC %s [sn:%lli]\n", 620 store_inst->pcState(), store_inst->seqNum); 621 622 assert(!store_inst->isSquashed()); 623 624 // Check the recently completed loads to see if any match this store's 625 // address. If so, then we have a memory ordering violation. 626 int load_idx = store_inst->lqIdx; 627 628 Fault store_fault = store_inst->initiateAcc(); 629 630 if (store_inst->isTranslationDelayed() && 631 store_fault == NoFault) 632 return store_fault; 633 634 if (store_inst->readPredicate() == false) 635 store_inst->forwardOldRegs(); 636 637 if (storeQueue[store_idx].size == 0) { 638 DPRINTF(LSQUnit,"Fault on Store PC %s, [sn:%lli], Size = 0\n", 639 store_inst->pcState(), store_inst->seqNum); 640 641 return store_fault; 642 } else if (store_inst->readPredicate() == false) { 643 DPRINTF(LSQUnit, "Store [sn:%lli] not executed from predication\n", 644 store_inst->seqNum); 645 return store_fault; 646 } 647 648 assert(store_fault == NoFault); 649 650 if (store_inst->isStoreConditional()) { 651 // Store conditionals need to set themselves as able to 652 // writeback if we haven't had a fault by here. 653 storeQueue[store_idx].canWB = true; 654 655 ++storesToWB; 656 } 657 658 return checkViolations(load_idx, store_inst); 659 660} 661 662template <class Impl> 663void 664LSQUnit<Impl>::commitLoad() 665{ 666 assert(loadQueue[loadHead]); 667 668 DPRINTF(LSQUnit, "Committing head load instruction, PC %s\n", 669 loadQueue[loadHead]->pcState()); 670 671 loadQueue[loadHead] = NULL; 672 673 incrLdIdx(loadHead); 674 675 --loads; 676} 677 678template <class Impl> 679void 680LSQUnit<Impl>::commitLoads(InstSeqNum &youngest_inst) 681{ 682 assert(loads == 0 || loadQueue[loadHead]); 683 684 while (loads != 0 && loadQueue[loadHead]->seqNum <= youngest_inst) { 685 commitLoad(); 686 } 687} 688 689template <class Impl> 690void 691LSQUnit<Impl>::commitStores(InstSeqNum &youngest_inst) 692{ 693 assert(stores == 0 || storeQueue[storeHead].inst); 694 695 int store_idx = storeHead; 696 697 while (store_idx != storeTail) { 698 assert(storeQueue[store_idx].inst); 699 // Mark any stores that are now committed and have not yet 700 // been marked as able to write back. 701 if (!storeQueue[store_idx].canWB) { 702 if (storeQueue[store_idx].inst->seqNum > youngest_inst) { 703 break; 704 } 705 DPRINTF(LSQUnit, "Marking store as able to write back, PC " 706 "%s [sn:%lli]\n", 707 storeQueue[store_idx].inst->pcState(), 708 storeQueue[store_idx].inst->seqNum); 709 710 storeQueue[store_idx].canWB = true; 711 712 ++storesToWB; 713 } 714 715 incrStIdx(store_idx); 716 } 717} 718 719template <class Impl> 720void 721LSQUnit<Impl>::writebackPendingStore() 722{ 723 if (hasPendingPkt) { 724 assert(pendingPkt != NULL); 725 726 // If the cache is blocked, this will store the packet for retry. 727 if (sendStore(pendingPkt)) { 728 storePostSend(pendingPkt); 729 } 730 pendingPkt = NULL; 731 hasPendingPkt = false; 732 } 733} 734 735template <class Impl> 736void 737LSQUnit<Impl>::writebackStores() 738{ 739 // First writeback the second packet from any split store that didn't 740 // complete last cycle because there weren't enough cache ports available. 741 if (TheISA::HasUnalignedMemAcc) { 742 writebackPendingStore(); 743 } 744 745 while (storesToWB > 0 && 746 storeWBIdx != storeTail && 747 storeQueue[storeWBIdx].inst && 748 storeQueue[storeWBIdx].canWB && 749 ((!needsTSO) || (!storeInFlight)) && 750 usedPorts < cachePorts) { 751 752 if (isStoreBlocked || lsq->cacheBlocked()) { 753 DPRINTF(LSQUnit, "Unable to write back any more stores, cache" 754 " is blocked!\n"); 755 break; 756 } 757 758 // Store didn't write any data so no need to write it back to 759 // memory. 760 if (storeQueue[storeWBIdx].size == 0) { 761 completeStore(storeWBIdx); 762 763 incrStIdx(storeWBIdx); 764 765 continue; 766 } 767 768 ++usedPorts; 769 770 if (storeQueue[storeWBIdx].inst->isDataPrefetch()) { 771 incrStIdx(storeWBIdx); 772 773 continue; 774 } 775 776 assert(storeQueue[storeWBIdx].req); 777 assert(!storeQueue[storeWBIdx].committed); 778 779 if (TheISA::HasUnalignedMemAcc && storeQueue[storeWBIdx].isSplit) { 780 assert(storeQueue[storeWBIdx].sreqLow); 781 assert(storeQueue[storeWBIdx].sreqHigh); 782 } 783 784 DynInstPtr inst = storeQueue[storeWBIdx].inst; 785 786 Request *req = storeQueue[storeWBIdx].req; 787 RequestPtr sreqLow = storeQueue[storeWBIdx].sreqLow; 788 RequestPtr sreqHigh = storeQueue[storeWBIdx].sreqHigh; 789 790 storeQueue[storeWBIdx].committed = true; 791 792 assert(!inst->memData); 793 inst->memData = new uint8_t[64]; 794 795 memcpy(inst->memData, storeQueue[storeWBIdx].data, req->getSize()); 796 797 MemCmd command = 798 req->isSwap() ? MemCmd::SwapReq : 799 (req->isLLSC() ? MemCmd::StoreCondReq : MemCmd::WriteReq); 800 PacketPtr data_pkt; 801 PacketPtr snd_data_pkt = NULL; 802 803 LSQSenderState *state = new LSQSenderState; 804 state->isLoad = false; 805 state->idx = storeWBIdx; 806 state->inst = inst; 807 808 if (!TheISA::HasUnalignedMemAcc || !storeQueue[storeWBIdx].isSplit) { 809 810 // Build a single data packet if the store isn't split. 811 data_pkt = new Packet(req, command); 812 data_pkt->dataStatic(inst->memData); 813 data_pkt->senderState = state; 814 } else { 815 // Create two packets if the store is split in two. 816 data_pkt = new Packet(sreqLow, command); 817 snd_data_pkt = new Packet(sreqHigh, command); 818 819 data_pkt->dataStatic(inst->memData); 820 snd_data_pkt->dataStatic(inst->memData + sreqLow->getSize()); 821 822 data_pkt->senderState = state; 823 snd_data_pkt->senderState = state; 824 825 state->isSplit = true; 826 state->outstanding = 2; 827 828 // Can delete the main request now. 829 delete req; 830 req = sreqLow; 831 } 832 833 DPRINTF(LSQUnit, "D-Cache: Writing back store idx:%i PC:%s " 834 "to Addr:%#x, data:%#x [sn:%lli]\n", 835 storeWBIdx, inst->pcState(), 836 req->getPaddr(), (int)*(inst->memData), 837 inst->seqNum); 838 839 // @todo: Remove this SC hack once the memory system handles it. 840 if (inst->isStoreConditional()) { 841 assert(!storeQueue[storeWBIdx].isSplit); 842 // Disable recording the result temporarily. Writing to 843 // misc regs normally updates the result, but this is not 844 // the desired behavior when handling store conditionals. 845 inst->recordResult(false); 846 bool success = TheISA::handleLockedWrite(inst.get(), req); 847 inst->recordResult(true); 848 849 if (!success) { 850 // Instantly complete this store. 851 DPRINTF(LSQUnit, "Store conditional [sn:%lli] failed. " 852 "Instantly completing it.\n", 853 inst->seqNum); 854 WritebackEvent *wb = new WritebackEvent(inst, data_pkt, this); 855 cpu->schedule(wb, curTick() + 1); 856 if (cpu->checker) { 857 // Make sure to set the LLSC data for verification 858 // if checker is loaded 859 inst->reqToVerify->setExtraData(0); 860 inst->completeAcc(data_pkt); 861 } 862 completeStore(storeWBIdx); 863 incrStIdx(storeWBIdx); 864 continue; 865 } 866 } else { 867 // Non-store conditionals do not need a writeback. 868 state->noWB = true; 869 } 870 871 bool split = 872 TheISA::HasUnalignedMemAcc && storeQueue[storeWBIdx].isSplit; 873 874 ThreadContext *thread = cpu->tcBase(lsqID); 875 876 if (req->isMmappedIpr()) { 877 assert(!inst->isStoreConditional()); 878 TheISA::handleIprWrite(thread, data_pkt); 879 delete data_pkt; 880 if (split) { 881 assert(snd_data_pkt->req->isMmappedIpr()); 882 TheISA::handleIprWrite(thread, snd_data_pkt); 883 delete snd_data_pkt; 884 delete sreqLow; 885 delete sreqHigh; 886 } 887 delete state; 888 delete req; 889 completeStore(storeWBIdx); 890 incrStIdx(storeWBIdx); 891 } else if (!sendStore(data_pkt)) { 892 DPRINTF(IEW, "D-Cache became blocked when writing [sn:%lli], will" 893 "retry later\n", 894 inst->seqNum); 895 896 // Need to store the second packet, if split. 897 if (split) { 898 state->pktToSend = true; 899 state->pendingPacket = snd_data_pkt; 900 } 901 } else { 902 903 // If split, try to send the second packet too 904 if (split) { 905 assert(snd_data_pkt); 906 907 // Ensure there are enough ports to use. 908 if (usedPorts < cachePorts) { 909 ++usedPorts; 910 if (sendStore(snd_data_pkt)) { 911 storePostSend(snd_data_pkt); 912 } else { 913 DPRINTF(IEW, "D-Cache became blocked when writing" 914 " [sn:%lli] second packet, will retry later\n", 915 inst->seqNum); 916 } 917 } else { 918 919 // Store the packet for when there's free ports. 920 assert(pendingPkt == NULL); 921 pendingPkt = snd_data_pkt; 922 hasPendingPkt = true; 923 } 924 } else { 925 926 // Not a split store. 927 storePostSend(data_pkt); 928 } 929 } 930 } 931 932 // Not sure this should set it to 0. 933 usedPorts = 0; 934 935 assert(stores >= 0 && storesToWB >= 0); 936} 937 938/*template <class Impl> 939void 940LSQUnit<Impl>::removeMSHR(InstSeqNum seqNum) 941{ 942 list<InstSeqNum>::iterator mshr_it = find(mshrSeqNums.begin(), 943 mshrSeqNums.end(), 944 seqNum); 945 946 if (mshr_it != mshrSeqNums.end()) { 947 mshrSeqNums.erase(mshr_it); 948 DPRINTF(LSQUnit, "Removing MSHR. count = %i\n",mshrSeqNums.size()); 949 } 950}*/ 951 952template <class Impl> 953void 954LSQUnit<Impl>::squash(const InstSeqNum &squashed_num) 955{ 956 DPRINTF(LSQUnit, "Squashing until [sn:%lli]!" 957 "(Loads:%i Stores:%i)\n", squashed_num, loads, stores); 958 959 int load_idx = loadTail; 960 decrLdIdx(load_idx); 961 962 while (loads != 0 && loadQueue[load_idx]->seqNum > squashed_num) { 963 DPRINTF(LSQUnit,"Load Instruction PC %s squashed, " 964 "[sn:%lli]\n", 965 loadQueue[load_idx]->pcState(), 966 loadQueue[load_idx]->seqNum); 967 968 if (isStalled() && load_idx == stallingLoadIdx) { 969 stalled = false; 970 stallingStoreIsn = 0; 971 stallingLoadIdx = 0; 972 } 973 974 // Clear the smart pointer to make sure it is decremented. 975 loadQueue[load_idx]->setSquashed(); 976 loadQueue[load_idx] = NULL; 977 --loads; 978 979 // Inefficient! 980 loadTail = load_idx; 981 982 decrLdIdx(load_idx); 983 ++lsqSquashedLoads; 984 } 985 986 if (isLoadBlocked) { 987 if (squashed_num < blockedLoadSeqNum) { 988 isLoadBlocked = false; 989 loadBlockedHandled = false; 990 blockedLoadSeqNum = 0; 991 } 992 } 993 994 if (memDepViolator && squashed_num < memDepViolator->seqNum) { 995 memDepViolator = NULL; 996 } 997 998 int store_idx = storeTail; 999 decrStIdx(store_idx); 1000 1001 while (stores != 0 && 1002 storeQueue[store_idx].inst->seqNum > squashed_num) { 1003 // Instructions marked as can WB are already committed. 1004 if (storeQueue[store_idx].canWB) { 1005 break; 1006 } 1007 1008 DPRINTF(LSQUnit,"Store Instruction PC %s squashed, " 1009 "idx:%i [sn:%lli]\n", 1010 storeQueue[store_idx].inst->pcState(), 1011 store_idx, storeQueue[store_idx].inst->seqNum); 1012 1013 // I don't think this can happen. It should have been cleared 1014 // by the stalling load. 1015 if (isStalled() && 1016 storeQueue[store_idx].inst->seqNum == stallingStoreIsn) { 1017 panic("Is stalled should have been cleared by stalling load!\n"); 1018 stalled = false; 1019 stallingStoreIsn = 0; 1020 } 1021 1022 // Clear the smart pointer to make sure it is decremented. 1023 storeQueue[store_idx].inst->setSquashed(); 1024 storeQueue[store_idx].inst = NULL; 1025 storeQueue[store_idx].canWB = 0; 1026 1027 // Must delete request now that it wasn't handed off to 1028 // memory. This is quite ugly. @todo: Figure out the proper 1029 // place to really handle request deletes. 1030 delete storeQueue[store_idx].req; 1031 if (TheISA::HasUnalignedMemAcc && storeQueue[store_idx].isSplit) { 1032 delete storeQueue[store_idx].sreqLow; 1033 delete storeQueue[store_idx].sreqHigh; 1034 1035 storeQueue[store_idx].sreqLow = NULL; 1036 storeQueue[store_idx].sreqHigh = NULL; 1037 } 1038 1039 storeQueue[store_idx].req = NULL; 1040 --stores; 1041 1042 // Inefficient! 1043 storeTail = store_idx; 1044 1045 decrStIdx(store_idx); 1046 ++lsqSquashedStores; 1047 } 1048} 1049 1050template <class Impl> 1051void 1052LSQUnit<Impl>::storePostSend(PacketPtr pkt) 1053{ 1054 if (isStalled() && 1055 storeQueue[storeWBIdx].inst->seqNum == stallingStoreIsn) { 1056 DPRINTF(LSQUnit, "Unstalling, stalling store [sn:%lli] " 1057 "load idx:%i\n", 1058 stallingStoreIsn, stallingLoadIdx); 1059 stalled = false; 1060 stallingStoreIsn = 0; 1061 iewStage->replayMemInst(loadQueue[stallingLoadIdx]); 1062 } 1063 1064 if (!storeQueue[storeWBIdx].inst->isStoreConditional()) { 1065 // The store is basically completed at this time. This 1066 // only works so long as the checker doesn't try to 1067 // verify the value in memory for stores. 1068 storeQueue[storeWBIdx].inst->setCompleted(); 1069 1070 if (cpu->checker) { 1071 cpu->checker->verify(storeQueue[storeWBIdx].inst); 1072 } 1073 } 1074 1075 if (needsTSO) { 1076 storeInFlight = true; 1077 } 1078 1079 incrStIdx(storeWBIdx); 1080} 1081 1082template <class Impl> 1083void 1084LSQUnit<Impl>::writeback(DynInstPtr &inst, PacketPtr pkt) 1085{ 1086 iewStage->wakeCPU(); 1087 1088 // Squashed instructions do not need to complete their access. 1089 if (inst->isSquashed()) { 1090 iewStage->decrWb(inst->seqNum); 1091 assert(!inst->isStore()); 1092 ++lsqIgnoredResponses; 1093 return; 1094 } 1095 1096 if (!inst->isExecuted()) { 1097 inst->setExecuted(); 1098 1099 // Complete access to copy data to proper place. 1100 inst->completeAcc(pkt); 1101 } 1102 1103 // Need to insert instruction into queue to commit 1104 iewStage->instToCommit(inst); 1105 1106 iewStage->activityThisCycle(); 1107 1108 // see if this load changed the PC 1109 iewStage->checkMisprediction(inst); 1110} 1111 1112template <class Impl> 1113void 1114LSQUnit<Impl>::completeStore(int store_idx) 1115{ 1116 assert(storeQueue[store_idx].inst); 1117 storeQueue[store_idx].completed = true; 1118 --storesToWB; 1119 // A bit conservative because a store completion may not free up entries, 1120 // but hopefully avoids two store completions in one cycle from making 1121 // the CPU tick twice. 1122 cpu->wakeCPU(); 1123 cpu->activityThisCycle(); 1124 1125 if (store_idx == storeHead) { 1126 do { 1127 incrStIdx(storeHead); 1128 1129 --stores; 1130 } while (storeQueue[storeHead].completed && 1131 storeHead != storeTail); 1132 1133 iewStage->updateLSQNextCycle = true; 1134 } 1135 1136 DPRINTF(LSQUnit, "Completing store [sn:%lli], idx:%i, store head " 1137 "idx:%i\n", 1138 storeQueue[store_idx].inst->seqNum, store_idx, storeHead); 1139
| 55#include "mem/packet.hh" 56#include "mem/request.hh" 57 58template<class Impl> 59LSQUnit<Impl>::WritebackEvent::WritebackEvent(DynInstPtr &_inst, PacketPtr _pkt, 60 LSQUnit *lsq_ptr) 61 : Event(Default_Pri, AutoDelete), 62 inst(_inst), pkt(_pkt), lsqPtr(lsq_ptr) 63{ 64} 65 66template<class Impl> 67void 68LSQUnit<Impl>::WritebackEvent::process() 69{ 70 assert(!lsqPtr->cpu->switchedOut()); 71 72 lsqPtr->writeback(inst, pkt); 73 74 if (pkt->senderState) 75 delete pkt->senderState; 76 77 delete pkt->req; 78 delete pkt; 79} 80 81template<class Impl> 82const char * 83LSQUnit<Impl>::WritebackEvent::description() const 84{ 85 return "Store writeback"; 86} 87 88template<class Impl> 89void 90LSQUnit<Impl>::completeDataAccess(PacketPtr pkt) 91{ 92 LSQSenderState *state = dynamic_cast<LSQSenderState *>(pkt->senderState); 93 DynInstPtr inst = state->inst; 94 DPRINTF(IEW, "Writeback event [sn:%lli].\n", inst->seqNum); 95 DPRINTF(Activity, "Activity: Writeback event [sn:%lli].\n", inst->seqNum); 96 97 //iewStage->ldstQueue.removeMSHR(inst->threadNumber,inst->seqNum); 98 99 // If this is a split access, wait until all packets are received. 100 if (TheISA::HasUnalignedMemAcc && !state->complete()) { 101 delete pkt->req; 102 delete pkt; 103 return; 104 } 105 106 assert(!cpu->switchedOut()); 107 if (inst->isSquashed()) { 108 iewStage->decrWb(inst->seqNum); 109 } else { 110 if (!state->noWB) { 111 if (!TheISA::HasUnalignedMemAcc || !state->isSplit || 112 !state->isLoad) { 113 writeback(inst, pkt); 114 } else { 115 writeback(inst, state->mainPkt); 116 } 117 } 118 119 if (inst->isStore()) { 120 completeStore(state->idx); 121 } 122 } 123 124 if (TheISA::HasUnalignedMemAcc && state->isSplit && state->isLoad) { 125 delete state->mainPkt->req; 126 delete state->mainPkt; 127 } 128 delete state; 129 delete pkt->req; 130 delete pkt; 131} 132 133template <class Impl> 134LSQUnit<Impl>::LSQUnit() 135 : loads(0), stores(0), storesToWB(0), cacheBlockMask(0), stalled(false), 136 isStoreBlocked(false), isLoadBlocked(false), 137 loadBlockedHandled(false), storeInFlight(false), hasPendingPkt(false) 138{ 139} 140 141template<class Impl> 142void 143LSQUnit<Impl>::init(O3CPU *cpu_ptr, IEW *iew_ptr, DerivO3CPUParams *params, 144 LSQ *lsq_ptr, unsigned maxLQEntries, unsigned maxSQEntries, 145 unsigned id) 146{ 147 cpu = cpu_ptr; 148 iewStage = iew_ptr; 149 150 DPRINTF(LSQUnit, "Creating LSQUnit%i object.\n",id); 151 152 lsq = lsq_ptr; 153 154 lsqID = id; 155 156 // Add 1 for the sentinel entry (they are circular queues). 157 LQEntries = maxLQEntries + 1; 158 SQEntries = maxSQEntries + 1; 159 160 loadQueue.resize(LQEntries); 161 storeQueue.resize(SQEntries); 162 163 depCheckShift = params->LSQDepCheckShift; 164 checkLoads = params->LSQCheckLoads; 165 cachePorts = params->cachePorts; 166 needsTSO = params->needsTSO; 167 168 resetState(); 169} 170 171 172template<class Impl> 173void 174LSQUnit<Impl>::resetState() 175{ 176 loads = stores = storesToWB = 0; 177 178 loadHead = loadTail = 0; 179 180 storeHead = storeWBIdx = storeTail = 0; 181 182 usedPorts = 0; 183 184 retryPkt = NULL; 185 memDepViolator = NULL; 186 187 blockedLoadSeqNum = 0; 188 189 stalled = false; 190 isLoadBlocked = false; 191 loadBlockedHandled = false; 192 193 cacheBlockMask = 0; 194} 195 196template<class Impl> 197std::string 198LSQUnit<Impl>::name() const 199{ 200 if (Impl::MaxThreads == 1) { 201 return iewStage->name() + ".lsq"; 202 } else { 203 return iewStage->name() + ".lsq.thread" + to_string(lsqID); 204 } 205} 206 207template<class Impl> 208void 209LSQUnit<Impl>::regStats() 210{ 211 lsqForwLoads 212 .name(name() + ".forwLoads") 213 .desc("Number of loads that had data forwarded from stores"); 214 215 invAddrLoads 216 .name(name() + ".invAddrLoads") 217 .desc("Number of loads ignored due to an invalid address"); 218 219 lsqSquashedLoads 220 .name(name() + ".squashedLoads") 221 .desc("Number of loads squashed"); 222 223 lsqIgnoredResponses 224 .name(name() + ".ignoredResponses") 225 .desc("Number of memory responses ignored because the instruction is squashed"); 226 227 lsqMemOrderViolation 228 .name(name() + ".memOrderViolation") 229 .desc("Number of memory ordering violations"); 230 231 lsqSquashedStores 232 .name(name() + ".squashedStores") 233 .desc("Number of stores squashed"); 234 235 invAddrSwpfs 236 .name(name() + ".invAddrSwpfs") 237 .desc("Number of software prefetches ignored due to an invalid address"); 238 239 lsqBlockedLoads 240 .name(name() + ".blockedLoads") 241 .desc("Number of blocked loads due to partial load-store forwarding"); 242 243 lsqRescheduledLoads 244 .name(name() + ".rescheduledLoads") 245 .desc("Number of loads that were rescheduled"); 246 247 lsqCacheBlocked 248 .name(name() + ".cacheBlocked") 249 .desc("Number of times an access to memory failed due to the cache being blocked"); 250} 251 252template<class Impl> 253void 254LSQUnit<Impl>::setDcachePort(MasterPort *dcache_port) 255{ 256 dcachePort = dcache_port; 257} 258 259template<class Impl> 260void 261LSQUnit<Impl>::clearLQ() 262{ 263 loadQueue.clear(); 264} 265 266template<class Impl> 267void 268LSQUnit<Impl>::clearSQ() 269{ 270 storeQueue.clear(); 271} 272 273template<class Impl> 274void 275LSQUnit<Impl>::drainSanityCheck() const 276{ 277 for (int i = 0; i < loadQueue.size(); ++i) 278 assert(!loadQueue[i]); 279 280 assert(storesToWB == 0); 281 assert(!retryPkt); 282} 283 284template<class Impl> 285void 286LSQUnit<Impl>::takeOverFrom() 287{ 288 resetState(); 289} 290 291template<class Impl> 292void 293LSQUnit<Impl>::resizeLQ(unsigned size) 294{ 295 unsigned size_plus_sentinel = size + 1; 296 assert(size_plus_sentinel >= LQEntries); 297 298 if (size_plus_sentinel > LQEntries) { 299 while (size_plus_sentinel > loadQueue.size()) { 300 DynInstPtr dummy; 301 loadQueue.push_back(dummy); 302 LQEntries++; 303 } 304 } else { 305 LQEntries = size_plus_sentinel; 306 } 307 308} 309 310template<class Impl> 311void 312LSQUnit<Impl>::resizeSQ(unsigned size) 313{ 314 unsigned size_plus_sentinel = size + 1; 315 if (size_plus_sentinel > SQEntries) { 316 while (size_plus_sentinel > storeQueue.size()) { 317 SQEntry dummy; 318 storeQueue.push_back(dummy); 319 SQEntries++; 320 } 321 } else { 322 SQEntries = size_plus_sentinel; 323 } 324} 325 326template <class Impl> 327void 328LSQUnit<Impl>::insert(DynInstPtr &inst) 329{ 330 assert(inst->isMemRef()); 331 332 assert(inst->isLoad() || inst->isStore()); 333 334 if (inst->isLoad()) { 335 insertLoad(inst); 336 } else { 337 insertStore(inst); 338 } 339 340 inst->setInLSQ(); 341} 342 343template <class Impl> 344void 345LSQUnit<Impl>::insertLoad(DynInstPtr &load_inst) 346{ 347 assert((loadTail + 1) % LQEntries != loadHead); 348 assert(loads < LQEntries); 349 350 DPRINTF(LSQUnit, "Inserting load PC %s, idx:%i [sn:%lli]\n", 351 load_inst->pcState(), loadTail, load_inst->seqNum); 352 353 load_inst->lqIdx = loadTail; 354 355 if (stores == 0) { 356 load_inst->sqIdx = -1; 357 } else { 358 load_inst->sqIdx = storeTail; 359 } 360 361 loadQueue[loadTail] = load_inst; 362 363 incrLdIdx(loadTail); 364 365 ++loads; 366} 367 368template <class Impl> 369void 370LSQUnit<Impl>::insertStore(DynInstPtr &store_inst) 371{ 372 // Make sure it is not full before inserting an instruction. 373 assert((storeTail + 1) % SQEntries != storeHead); 374 assert(stores < SQEntries); 375 376 DPRINTF(LSQUnit, "Inserting store PC %s, idx:%i [sn:%lli]\n", 377 store_inst->pcState(), storeTail, store_inst->seqNum); 378 379 store_inst->sqIdx = storeTail; 380 store_inst->lqIdx = loadTail; 381 382 storeQueue[storeTail] = SQEntry(store_inst); 383 384 incrStIdx(storeTail); 385 386 ++stores; 387} 388 389template <class Impl> 390typename Impl::DynInstPtr 391LSQUnit<Impl>::getMemDepViolator() 392{ 393 DynInstPtr temp = memDepViolator; 394 395 memDepViolator = NULL; 396 397 return temp; 398} 399 400template <class Impl> 401unsigned 402LSQUnit<Impl>::numFreeEntries() 403{ 404 unsigned free_lq_entries = LQEntries - loads; 405 unsigned free_sq_entries = SQEntries - stores; 406 407 // Both the LQ and SQ entries have an extra dummy entry to differentiate 408 // empty/full conditions. Subtract 1 from the free entries. 409 if (free_lq_entries < free_sq_entries) { 410 return free_lq_entries - 1; 411 } else { 412 return free_sq_entries - 1; 413 } 414} 415 416template <class Impl> 417void 418LSQUnit<Impl>::checkSnoop(PacketPtr pkt) 419{ 420 int load_idx = loadHead; 421 422 if (!cacheBlockMask) { 423 assert(dcachePort); 424 Addr bs = dcachePort->peerBlockSize(); 425 426 // Make sure we actually got a size 427 assert(bs != 0); 428 429 cacheBlockMask = ~(bs - 1); 430 } 431 432 // Unlock the cpu-local monitor when the CPU sees a snoop to a locked 433 // address. The CPU can speculatively execute a LL operation after a pending 434 // SC operation in the pipeline and that can make the cache monitor the CPU 435 // is connected to valid while it really shouldn't be. 436 for (int x = 0; x < cpu->numActiveThreads(); x++) { 437 ThreadContext *tc = cpu->getContext(x); 438 bool no_squash = cpu->thread[x]->noSquashFromTC; 439 cpu->thread[x]->noSquashFromTC = true; 440 TheISA::handleLockedSnoop(tc, pkt, cacheBlockMask); 441 cpu->thread[x]->noSquashFromTC = no_squash; 442 } 443 444 // If this is the only load in the LSQ we don't care 445 if (load_idx == loadTail) 446 return; 447 incrLdIdx(load_idx); 448 449 DPRINTF(LSQUnit, "Got snoop for address %#x\n", pkt->getAddr()); 450 Addr invalidate_addr = pkt->getAddr() & cacheBlockMask; 451 while (load_idx != loadTail) { 452 DynInstPtr ld_inst = loadQueue[load_idx]; 453 454 if (!ld_inst->effAddrValid() || ld_inst->uncacheable()) { 455 incrLdIdx(load_idx); 456 continue; 457 } 458 459 Addr load_addr = ld_inst->physEffAddr & cacheBlockMask; 460 DPRINTF(LSQUnit, "-- inst [sn:%lli] load_addr: %#x to pktAddr:%#x\n", 461 ld_inst->seqNum, load_addr, invalidate_addr); 462 463 if (load_addr == invalidate_addr) { 464 if (ld_inst->possibleLoadViolation()) { 465 DPRINTF(LSQUnit, "Conflicting load at addr %#x [sn:%lli]\n", 466 ld_inst->physEffAddr, pkt->getAddr(), ld_inst->seqNum); 467 468 // Mark the load for re-execution 469 ld_inst->fault = new ReExec; 470 } else { 471 // If a older load checks this and it's true 472 // then we might have missed the snoop 473 // in which case we need to invalidate to be sure 474 ld_inst->hitExternalSnoop(true); 475 } 476 } 477 incrLdIdx(load_idx); 478 } 479 return; 480} 481 482template <class Impl> 483Fault 484LSQUnit<Impl>::checkViolations(int load_idx, DynInstPtr &inst) 485{ 486 Addr inst_eff_addr1 = inst->effAddr >> depCheckShift; 487 Addr inst_eff_addr2 = (inst->effAddr + inst->effSize - 1) >> depCheckShift; 488 489 /** @todo in theory you only need to check an instruction that has executed 490 * however, there isn't a good way in the pipeline at the moment to check 491 * all instructions that will execute before the store writes back. Thus, 492 * like the implementation that came before it, we're overly conservative. 493 */ 494 while (load_idx != loadTail) { 495 DynInstPtr ld_inst = loadQueue[load_idx]; 496 if (!ld_inst->effAddrValid() || ld_inst->uncacheable()) { 497 incrLdIdx(load_idx); 498 continue; 499 } 500 501 Addr ld_eff_addr1 = ld_inst->effAddr >> depCheckShift; 502 Addr ld_eff_addr2 = 503 (ld_inst->effAddr + ld_inst->effSize - 1) >> depCheckShift; 504 505 if (inst_eff_addr2 >= ld_eff_addr1 && inst_eff_addr1 <= ld_eff_addr2) { 506 if (inst->isLoad()) { 507 // If this load is to the same block as an external snoop 508 // invalidate that we've observed then the load needs to be 509 // squashed as it could have newer data 510 if (ld_inst->hitExternalSnoop()) { 511 if (!memDepViolator || 512 ld_inst->seqNum < memDepViolator->seqNum) { 513 DPRINTF(LSQUnit, "Detected fault with inst [sn:%lli] " 514 "and [sn:%lli] at address %#x\n", 515 inst->seqNum, ld_inst->seqNum, ld_eff_addr1); 516 memDepViolator = ld_inst; 517 518 ++lsqMemOrderViolation; 519 520 return new GenericISA::M5PanicFault( 521 "Detected fault with inst [sn:%lli] and " 522 "[sn:%lli] at address %#x\n", 523 inst->seqNum, ld_inst->seqNum, ld_eff_addr1); 524 } 525 } 526 527 // Otherwise, mark the load has a possible load violation 528 // and if we see a snoop before it's commited, we need to squash 529 ld_inst->possibleLoadViolation(true); 530 DPRINTF(LSQUnit, "Found possible load violaiton at addr: %#x" 531 " between instructions [sn:%lli] and [sn:%lli]\n", 532 inst_eff_addr1, inst->seqNum, ld_inst->seqNum); 533 } else { 534 // A load/store incorrectly passed this store. 535 // Check if we already have a violator, or if it's newer 536 // squash and refetch. 537 if (memDepViolator && ld_inst->seqNum > memDepViolator->seqNum) 538 break; 539 540 DPRINTF(LSQUnit, "Detected fault with inst [sn:%lli] and " 541 "[sn:%lli] at address %#x\n", 542 inst->seqNum, ld_inst->seqNum, ld_eff_addr1); 543 memDepViolator = ld_inst; 544 545 ++lsqMemOrderViolation; 546 547 return new GenericISA::M5PanicFault("Detected fault with " 548 "inst [sn:%lli] and [sn:%lli] at address %#x\n", 549 inst->seqNum, ld_inst->seqNum, ld_eff_addr1); 550 } 551 } 552 553 incrLdIdx(load_idx); 554 } 555 return NoFault; 556} 557 558 559 560 561template <class Impl> 562Fault 563LSQUnit<Impl>::executeLoad(DynInstPtr &inst) 564{ 565 using namespace TheISA; 566 // Execute a specific load. 567 Fault load_fault = NoFault; 568 569 DPRINTF(LSQUnit, "Executing load PC %s, [sn:%lli]\n", 570 inst->pcState(), inst->seqNum); 571 572 assert(!inst->isSquashed()); 573 574 load_fault = inst->initiateAcc(); 575 576 if (inst->isTranslationDelayed() && 577 load_fault == NoFault) 578 return load_fault; 579 580 // If the instruction faulted or predicated false, then we need to send it 581 // along to commit without the instruction completing. 582 if (load_fault != NoFault || inst->readPredicate() == false) { 583 // Send this instruction to commit, also make sure iew stage 584 // realizes there is activity. 585 // Mark it as executed unless it is an uncached load that 586 // needs to hit the head of commit. 587 if (inst->readPredicate() == false) 588 inst->forwardOldRegs(); 589 DPRINTF(LSQUnit, "Load [sn:%lli] not executed from %s\n", 590 inst->seqNum, 591 (load_fault != NoFault ? "fault" : "predication")); 592 if (!(inst->hasRequest() && inst->uncacheable()) || 593 inst->isAtCommit()) { 594 inst->setExecuted(); 595 } 596 iewStage->instToCommit(inst); 597 iewStage->activityThisCycle(); 598 } else if (!loadBlocked()) { 599 assert(inst->effAddrValid()); 600 int load_idx = inst->lqIdx; 601 incrLdIdx(load_idx); 602 603 if (checkLoads) 604 return checkViolations(load_idx, inst); 605 } 606 607 return load_fault; 608} 609 610template <class Impl> 611Fault 612LSQUnit<Impl>::executeStore(DynInstPtr &store_inst) 613{ 614 using namespace TheISA; 615 // Make sure that a store exists. 616 assert(stores != 0); 617 618 int store_idx = store_inst->sqIdx; 619 620 DPRINTF(LSQUnit, "Executing store PC %s [sn:%lli]\n", 621 store_inst->pcState(), store_inst->seqNum); 622 623 assert(!store_inst->isSquashed()); 624 625 // Check the recently completed loads to see if any match this store's 626 // address. If so, then we have a memory ordering violation. 627 int load_idx = store_inst->lqIdx; 628 629 Fault store_fault = store_inst->initiateAcc(); 630 631 if (store_inst->isTranslationDelayed() && 632 store_fault == NoFault) 633 return store_fault; 634 635 if (store_inst->readPredicate() == false) 636 store_inst->forwardOldRegs(); 637 638 if (storeQueue[store_idx].size == 0) { 639 DPRINTF(LSQUnit,"Fault on Store PC %s, [sn:%lli], Size = 0\n", 640 store_inst->pcState(), store_inst->seqNum); 641 642 return store_fault; 643 } else if (store_inst->readPredicate() == false) { 644 DPRINTF(LSQUnit, "Store [sn:%lli] not executed from predication\n", 645 store_inst->seqNum); 646 return store_fault; 647 } 648 649 assert(store_fault == NoFault); 650 651 if (store_inst->isStoreConditional()) { 652 // Store conditionals need to set themselves as able to 653 // writeback if we haven't had a fault by here. 654 storeQueue[store_idx].canWB = true; 655 656 ++storesToWB; 657 } 658 659 return checkViolations(load_idx, store_inst); 660 661} 662 663template <class Impl> 664void 665LSQUnit<Impl>::commitLoad() 666{ 667 assert(loadQueue[loadHead]); 668 669 DPRINTF(LSQUnit, "Committing head load instruction, PC %s\n", 670 loadQueue[loadHead]->pcState()); 671 672 loadQueue[loadHead] = NULL; 673 674 incrLdIdx(loadHead); 675 676 --loads; 677} 678 679template <class Impl> 680void 681LSQUnit<Impl>::commitLoads(InstSeqNum &youngest_inst) 682{ 683 assert(loads == 0 || loadQueue[loadHead]); 684 685 while (loads != 0 && loadQueue[loadHead]->seqNum <= youngest_inst) { 686 commitLoad(); 687 } 688} 689 690template <class Impl> 691void 692LSQUnit<Impl>::commitStores(InstSeqNum &youngest_inst) 693{ 694 assert(stores == 0 || storeQueue[storeHead].inst); 695 696 int store_idx = storeHead; 697 698 while (store_idx != storeTail) { 699 assert(storeQueue[store_idx].inst); 700 // Mark any stores that are now committed and have not yet 701 // been marked as able to write back. 702 if (!storeQueue[store_idx].canWB) { 703 if (storeQueue[store_idx].inst->seqNum > youngest_inst) { 704 break; 705 } 706 DPRINTF(LSQUnit, "Marking store as able to write back, PC " 707 "%s [sn:%lli]\n", 708 storeQueue[store_idx].inst->pcState(), 709 storeQueue[store_idx].inst->seqNum); 710 711 storeQueue[store_idx].canWB = true; 712 713 ++storesToWB; 714 } 715 716 incrStIdx(store_idx); 717 } 718} 719 720template <class Impl> 721void 722LSQUnit<Impl>::writebackPendingStore() 723{ 724 if (hasPendingPkt) { 725 assert(pendingPkt != NULL); 726 727 // If the cache is blocked, this will store the packet for retry. 728 if (sendStore(pendingPkt)) { 729 storePostSend(pendingPkt); 730 } 731 pendingPkt = NULL; 732 hasPendingPkt = false; 733 } 734} 735 736template <class Impl> 737void 738LSQUnit<Impl>::writebackStores() 739{ 740 // First writeback the second packet from any split store that didn't 741 // complete last cycle because there weren't enough cache ports available. 742 if (TheISA::HasUnalignedMemAcc) { 743 writebackPendingStore(); 744 } 745 746 while (storesToWB > 0 && 747 storeWBIdx != storeTail && 748 storeQueue[storeWBIdx].inst && 749 storeQueue[storeWBIdx].canWB && 750 ((!needsTSO) || (!storeInFlight)) && 751 usedPorts < cachePorts) { 752 753 if (isStoreBlocked || lsq->cacheBlocked()) { 754 DPRINTF(LSQUnit, "Unable to write back any more stores, cache" 755 " is blocked!\n"); 756 break; 757 } 758 759 // Store didn't write any data so no need to write it back to 760 // memory. 761 if (storeQueue[storeWBIdx].size == 0) { 762 completeStore(storeWBIdx); 763 764 incrStIdx(storeWBIdx); 765 766 continue; 767 } 768 769 ++usedPorts; 770 771 if (storeQueue[storeWBIdx].inst->isDataPrefetch()) { 772 incrStIdx(storeWBIdx); 773 774 continue; 775 } 776 777 assert(storeQueue[storeWBIdx].req); 778 assert(!storeQueue[storeWBIdx].committed); 779 780 if (TheISA::HasUnalignedMemAcc && storeQueue[storeWBIdx].isSplit) { 781 assert(storeQueue[storeWBIdx].sreqLow); 782 assert(storeQueue[storeWBIdx].sreqHigh); 783 } 784 785 DynInstPtr inst = storeQueue[storeWBIdx].inst; 786 787 Request *req = storeQueue[storeWBIdx].req; 788 RequestPtr sreqLow = storeQueue[storeWBIdx].sreqLow; 789 RequestPtr sreqHigh = storeQueue[storeWBIdx].sreqHigh; 790 791 storeQueue[storeWBIdx].committed = true; 792 793 assert(!inst->memData); 794 inst->memData = new uint8_t[64]; 795 796 memcpy(inst->memData, storeQueue[storeWBIdx].data, req->getSize()); 797 798 MemCmd command = 799 req->isSwap() ? MemCmd::SwapReq : 800 (req->isLLSC() ? MemCmd::StoreCondReq : MemCmd::WriteReq); 801 PacketPtr data_pkt; 802 PacketPtr snd_data_pkt = NULL; 803 804 LSQSenderState *state = new LSQSenderState; 805 state->isLoad = false; 806 state->idx = storeWBIdx; 807 state->inst = inst; 808 809 if (!TheISA::HasUnalignedMemAcc || !storeQueue[storeWBIdx].isSplit) { 810 811 // Build a single data packet if the store isn't split. 812 data_pkt = new Packet(req, command); 813 data_pkt->dataStatic(inst->memData); 814 data_pkt->senderState = state; 815 } else { 816 // Create two packets if the store is split in two. 817 data_pkt = new Packet(sreqLow, command); 818 snd_data_pkt = new Packet(sreqHigh, command); 819 820 data_pkt->dataStatic(inst->memData); 821 snd_data_pkt->dataStatic(inst->memData + sreqLow->getSize()); 822 823 data_pkt->senderState = state; 824 snd_data_pkt->senderState = state; 825 826 state->isSplit = true; 827 state->outstanding = 2; 828 829 // Can delete the main request now. 830 delete req; 831 req = sreqLow; 832 } 833 834 DPRINTF(LSQUnit, "D-Cache: Writing back store idx:%i PC:%s " 835 "to Addr:%#x, data:%#x [sn:%lli]\n", 836 storeWBIdx, inst->pcState(), 837 req->getPaddr(), (int)*(inst->memData), 838 inst->seqNum); 839 840 // @todo: Remove this SC hack once the memory system handles it. 841 if (inst->isStoreConditional()) { 842 assert(!storeQueue[storeWBIdx].isSplit); 843 // Disable recording the result temporarily. Writing to 844 // misc regs normally updates the result, but this is not 845 // the desired behavior when handling store conditionals. 846 inst->recordResult(false); 847 bool success = TheISA::handleLockedWrite(inst.get(), req); 848 inst->recordResult(true); 849 850 if (!success) { 851 // Instantly complete this store. 852 DPRINTF(LSQUnit, "Store conditional [sn:%lli] failed. " 853 "Instantly completing it.\n", 854 inst->seqNum); 855 WritebackEvent *wb = new WritebackEvent(inst, data_pkt, this); 856 cpu->schedule(wb, curTick() + 1); 857 if (cpu->checker) { 858 // Make sure to set the LLSC data for verification 859 // if checker is loaded 860 inst->reqToVerify->setExtraData(0); 861 inst->completeAcc(data_pkt); 862 } 863 completeStore(storeWBIdx); 864 incrStIdx(storeWBIdx); 865 continue; 866 } 867 } else { 868 // Non-store conditionals do not need a writeback. 869 state->noWB = true; 870 } 871 872 bool split = 873 TheISA::HasUnalignedMemAcc && storeQueue[storeWBIdx].isSplit; 874 875 ThreadContext *thread = cpu->tcBase(lsqID); 876 877 if (req->isMmappedIpr()) { 878 assert(!inst->isStoreConditional()); 879 TheISA::handleIprWrite(thread, data_pkt); 880 delete data_pkt; 881 if (split) { 882 assert(snd_data_pkt->req->isMmappedIpr()); 883 TheISA::handleIprWrite(thread, snd_data_pkt); 884 delete snd_data_pkt; 885 delete sreqLow; 886 delete sreqHigh; 887 } 888 delete state; 889 delete req; 890 completeStore(storeWBIdx); 891 incrStIdx(storeWBIdx); 892 } else if (!sendStore(data_pkt)) { 893 DPRINTF(IEW, "D-Cache became blocked when writing [sn:%lli], will" 894 "retry later\n", 895 inst->seqNum); 896 897 // Need to store the second packet, if split. 898 if (split) { 899 state->pktToSend = true; 900 state->pendingPacket = snd_data_pkt; 901 } 902 } else { 903 904 // If split, try to send the second packet too 905 if (split) { 906 assert(snd_data_pkt); 907 908 // Ensure there are enough ports to use. 909 if (usedPorts < cachePorts) { 910 ++usedPorts; 911 if (sendStore(snd_data_pkt)) { 912 storePostSend(snd_data_pkt); 913 } else { 914 DPRINTF(IEW, "D-Cache became blocked when writing" 915 " [sn:%lli] second packet, will retry later\n", 916 inst->seqNum); 917 } 918 } else { 919 920 // Store the packet for when there's free ports. 921 assert(pendingPkt == NULL); 922 pendingPkt = snd_data_pkt; 923 hasPendingPkt = true; 924 } 925 } else { 926 927 // Not a split store. 928 storePostSend(data_pkt); 929 } 930 } 931 } 932 933 // Not sure this should set it to 0. 934 usedPorts = 0; 935 936 assert(stores >= 0 && storesToWB >= 0); 937} 938 939/*template <class Impl> 940void 941LSQUnit<Impl>::removeMSHR(InstSeqNum seqNum) 942{ 943 list<InstSeqNum>::iterator mshr_it = find(mshrSeqNums.begin(), 944 mshrSeqNums.end(), 945 seqNum); 946 947 if (mshr_it != mshrSeqNums.end()) { 948 mshrSeqNums.erase(mshr_it); 949 DPRINTF(LSQUnit, "Removing MSHR. count = %i\n",mshrSeqNums.size()); 950 } 951}*/ 952 953template <class Impl> 954void 955LSQUnit<Impl>::squash(const InstSeqNum &squashed_num) 956{ 957 DPRINTF(LSQUnit, "Squashing until [sn:%lli]!" 958 "(Loads:%i Stores:%i)\n", squashed_num, loads, stores); 959 960 int load_idx = loadTail; 961 decrLdIdx(load_idx); 962 963 while (loads != 0 && loadQueue[load_idx]->seqNum > squashed_num) { 964 DPRINTF(LSQUnit,"Load Instruction PC %s squashed, " 965 "[sn:%lli]\n", 966 loadQueue[load_idx]->pcState(), 967 loadQueue[load_idx]->seqNum); 968 969 if (isStalled() && load_idx == stallingLoadIdx) { 970 stalled = false; 971 stallingStoreIsn = 0; 972 stallingLoadIdx = 0; 973 } 974 975 // Clear the smart pointer to make sure it is decremented. 976 loadQueue[load_idx]->setSquashed(); 977 loadQueue[load_idx] = NULL; 978 --loads; 979 980 // Inefficient! 981 loadTail = load_idx; 982 983 decrLdIdx(load_idx); 984 ++lsqSquashedLoads; 985 } 986 987 if (isLoadBlocked) { 988 if (squashed_num < blockedLoadSeqNum) { 989 isLoadBlocked = false; 990 loadBlockedHandled = false; 991 blockedLoadSeqNum = 0; 992 } 993 } 994 995 if (memDepViolator && squashed_num < memDepViolator->seqNum) { 996 memDepViolator = NULL; 997 } 998 999 int store_idx = storeTail; 1000 decrStIdx(store_idx); 1001 1002 while (stores != 0 && 1003 storeQueue[store_idx].inst->seqNum > squashed_num) { 1004 // Instructions marked as can WB are already committed. 1005 if (storeQueue[store_idx].canWB) { 1006 break; 1007 } 1008 1009 DPRINTF(LSQUnit,"Store Instruction PC %s squashed, " 1010 "idx:%i [sn:%lli]\n", 1011 storeQueue[store_idx].inst->pcState(), 1012 store_idx, storeQueue[store_idx].inst->seqNum); 1013 1014 // I don't think this can happen. It should have been cleared 1015 // by the stalling load. 1016 if (isStalled() && 1017 storeQueue[store_idx].inst->seqNum == stallingStoreIsn) { 1018 panic("Is stalled should have been cleared by stalling load!\n"); 1019 stalled = false; 1020 stallingStoreIsn = 0; 1021 } 1022 1023 // Clear the smart pointer to make sure it is decremented. 1024 storeQueue[store_idx].inst->setSquashed(); 1025 storeQueue[store_idx].inst = NULL; 1026 storeQueue[store_idx].canWB = 0; 1027 1028 // Must delete request now that it wasn't handed off to 1029 // memory. This is quite ugly. @todo: Figure out the proper 1030 // place to really handle request deletes. 1031 delete storeQueue[store_idx].req; 1032 if (TheISA::HasUnalignedMemAcc && storeQueue[store_idx].isSplit) { 1033 delete storeQueue[store_idx].sreqLow; 1034 delete storeQueue[store_idx].sreqHigh; 1035 1036 storeQueue[store_idx].sreqLow = NULL; 1037 storeQueue[store_idx].sreqHigh = NULL; 1038 } 1039 1040 storeQueue[store_idx].req = NULL; 1041 --stores; 1042 1043 // Inefficient! 1044 storeTail = store_idx; 1045 1046 decrStIdx(store_idx); 1047 ++lsqSquashedStores; 1048 } 1049} 1050 1051template <class Impl> 1052void 1053LSQUnit<Impl>::storePostSend(PacketPtr pkt) 1054{ 1055 if (isStalled() && 1056 storeQueue[storeWBIdx].inst->seqNum == stallingStoreIsn) { 1057 DPRINTF(LSQUnit, "Unstalling, stalling store [sn:%lli] " 1058 "load idx:%i\n", 1059 stallingStoreIsn, stallingLoadIdx); 1060 stalled = false; 1061 stallingStoreIsn = 0; 1062 iewStage->replayMemInst(loadQueue[stallingLoadIdx]); 1063 } 1064 1065 if (!storeQueue[storeWBIdx].inst->isStoreConditional()) { 1066 // The store is basically completed at this time. This 1067 // only works so long as the checker doesn't try to 1068 // verify the value in memory for stores. 1069 storeQueue[storeWBIdx].inst->setCompleted(); 1070 1071 if (cpu->checker) { 1072 cpu->checker->verify(storeQueue[storeWBIdx].inst); 1073 } 1074 } 1075 1076 if (needsTSO) { 1077 storeInFlight = true; 1078 } 1079 1080 incrStIdx(storeWBIdx); 1081} 1082 1083template <class Impl> 1084void 1085LSQUnit<Impl>::writeback(DynInstPtr &inst, PacketPtr pkt) 1086{ 1087 iewStage->wakeCPU(); 1088 1089 // Squashed instructions do not need to complete their access. 1090 if (inst->isSquashed()) { 1091 iewStage->decrWb(inst->seqNum); 1092 assert(!inst->isStore()); 1093 ++lsqIgnoredResponses; 1094 return; 1095 } 1096 1097 if (!inst->isExecuted()) { 1098 inst->setExecuted(); 1099 1100 // Complete access to copy data to proper place. 1101 inst->completeAcc(pkt); 1102 } 1103 1104 // Need to insert instruction into queue to commit 1105 iewStage->instToCommit(inst); 1106 1107 iewStage->activityThisCycle(); 1108 1109 // see if this load changed the PC 1110 iewStage->checkMisprediction(inst); 1111} 1112 1113template <class Impl> 1114void 1115LSQUnit<Impl>::completeStore(int store_idx) 1116{ 1117 assert(storeQueue[store_idx].inst); 1118 storeQueue[store_idx].completed = true; 1119 --storesToWB; 1120 // A bit conservative because a store completion may not free up entries, 1121 // but hopefully avoids two store completions in one cycle from making 1122 // the CPU tick twice. 1123 cpu->wakeCPU(); 1124 cpu->activityThisCycle(); 1125 1126 if (store_idx == storeHead) { 1127 do { 1128 incrStIdx(storeHead); 1129 1130 --stores; 1131 } while (storeQueue[storeHead].completed && 1132 storeHead != storeTail); 1133 1134 iewStage->updateLSQNextCycle = true; 1135 } 1136 1137 DPRINTF(LSQUnit, "Completing store [sn:%lli], idx:%i, store head " 1138 "idx:%i\n", 1139 storeQueue[store_idx].inst->seqNum, store_idx, storeHead); 1140
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