1/* 2 * Copyright (c) 2010 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Copyright (c) 2004-2005 The Regents of The University of Michigan 15 * All rights reserved. 16 * 17 * Redistribution and use in source and binary forms, with or without 18 * modification, are permitted provided that the following conditions are 19 * met: redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer; 21 * redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution; 24 * neither the name of the copyright holders nor the names of its 25 * contributors may be used to endorse or promote products derived from 26 * this software without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 39 * 40 * Authors: Kevin Lim 41 * Korey Sewell 42 */ 43 44#include "arch/locked_mem.hh" 45#include "config/the_isa.hh" 46#include "config/use_checker.hh" 47#include "cpu/o3/lsq.hh" 48#include "cpu/o3/lsq_unit.hh" 49#include "base/str.hh" 50#include "mem/packet.hh" 51#include "mem/request.hh" 52 53#if USE_CHECKER 54#include "cpu/checker/cpu.hh" 55#endif 56 57template<class Impl> 58LSQUnit<Impl>::WritebackEvent::WritebackEvent(DynInstPtr &_inst, PacketPtr _pkt, 59 LSQUnit *lsq_ptr) 60 : inst(_inst), pkt(_pkt), lsqPtr(lsq_ptr) 61{ 62 this->setFlags(Event::AutoDelete); 63} 64 65template<class Impl> 66void 67LSQUnit<Impl>::WritebackEvent::process() 68{ 69 if (!lsqPtr->isSwitchedOut()) { 70 lsqPtr->writeback(inst, pkt); 71 } 72 73 if (pkt->senderState) 74 delete pkt->senderState; 75 76 delete pkt->req; 77 delete pkt; 78} 79 80template<class Impl> 81const char * 82LSQUnit<Impl>::WritebackEvent::description() const 83{ 84 return "Store writeback"; 85} 86 87template<class Impl> 88void 89LSQUnit<Impl>::completeDataAccess(PacketPtr pkt) 90{ 91 LSQSenderState *state = dynamic_cast<LSQSenderState *>(pkt->senderState); 92 DynInstPtr inst = state->inst;
| 1/* 2 * Copyright (c) 2010 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Copyright (c) 2004-2005 The Regents of The University of Michigan 15 * All rights reserved. 16 * 17 * Redistribution and use in source and binary forms, with or without 18 * modification, are permitted provided that the following conditions are 19 * met: redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer; 21 * redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution; 24 * neither the name of the copyright holders nor the names of its 25 * contributors may be used to endorse or promote products derived from 26 * this software without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 39 * 40 * Authors: Kevin Lim 41 * Korey Sewell 42 */ 43 44#include "arch/locked_mem.hh" 45#include "config/the_isa.hh" 46#include "config/use_checker.hh" 47#include "cpu/o3/lsq.hh" 48#include "cpu/o3/lsq_unit.hh" 49#include "base/str.hh" 50#include "mem/packet.hh" 51#include "mem/request.hh" 52 53#if USE_CHECKER 54#include "cpu/checker/cpu.hh" 55#endif 56 57template<class Impl> 58LSQUnit<Impl>::WritebackEvent::WritebackEvent(DynInstPtr &_inst, PacketPtr _pkt, 59 LSQUnit *lsq_ptr) 60 : inst(_inst), pkt(_pkt), lsqPtr(lsq_ptr) 61{ 62 this->setFlags(Event::AutoDelete); 63} 64 65template<class Impl> 66void 67LSQUnit<Impl>::WritebackEvent::process() 68{ 69 if (!lsqPtr->isSwitchedOut()) { 70 lsqPtr->writeback(inst, pkt); 71 } 72 73 if (pkt->senderState) 74 delete pkt->senderState; 75 76 delete pkt->req; 77 delete pkt; 78} 79 80template<class Impl> 81const char * 82LSQUnit<Impl>::WritebackEvent::description() const 83{ 84 return "Store writeback"; 85} 86 87template<class Impl> 88void 89LSQUnit<Impl>::completeDataAccess(PacketPtr pkt) 90{ 91 LSQSenderState *state = dynamic_cast<LSQSenderState *>(pkt->senderState); 92 DynInstPtr inst = state->inst;
|
95 96 //iewStage->ldstQueue.removeMSHR(inst->threadNumber,inst->seqNum); 97 98 assert(!pkt->wasNacked()); 99 100 // If this is a split access, wait until all packets are received. 101 if (TheISA::HasUnalignedMemAcc && !state->complete()) { 102 delete pkt->req; 103 delete pkt; 104 return; 105 } 106 107 if (isSwitchedOut() || inst->isSquashed()) { 108 iewStage->decrWb(inst->seqNum); 109 } else { 110 if (!state->noWB) { 111 if (!TheISA::HasUnalignedMemAcc || !state->isSplit || 112 !state->isLoad) { 113 writeback(inst, pkt); 114 } else { 115 writeback(inst, state->mainPkt); 116 } 117 } 118 119 if (inst->isStore()) { 120 completeStore(state->idx); 121 } 122 } 123 124 if (TheISA::HasUnalignedMemAcc && state->isSplit && state->isLoad) { 125 delete state->mainPkt->req; 126 delete state->mainPkt; 127 } 128 delete state; 129 delete pkt->req; 130 delete pkt; 131} 132 133template <class Impl> 134LSQUnit<Impl>::LSQUnit() 135 : loads(0), stores(0), storesToWB(0), stalled(false), 136 isStoreBlocked(false), isLoadBlocked(false), 137 loadBlockedHandled(false), hasPendingPkt(false) 138{ 139} 140 141template<class Impl> 142void 143LSQUnit<Impl>::init(O3CPU *cpu_ptr, IEW *iew_ptr, DerivO3CPUParams *params, 144 LSQ *lsq_ptr, unsigned maxLQEntries, unsigned maxSQEntries, 145 unsigned id) 146{ 147 cpu = cpu_ptr; 148 iewStage = iew_ptr; 149 150 DPRINTF(LSQUnit, "Creating LSQUnit%i object.\n",id); 151 152 switchedOut = false; 153 154 lsq = lsq_ptr; 155 156 lsqID = id; 157 158 // Add 1 for the sentinel entry (they are circular queues). 159 LQEntries = maxLQEntries + 1; 160 SQEntries = maxSQEntries + 1; 161 162 loadQueue.resize(LQEntries); 163 storeQueue.resize(SQEntries); 164 165 loadHead = loadTail = 0; 166 167 storeHead = storeWBIdx = storeTail = 0; 168 169 usedPorts = 0; 170 cachePorts = params->cachePorts; 171 172 retryPkt = NULL; 173 memDepViolator = NULL; 174 175 blockedLoadSeqNum = 0; 176} 177 178template<class Impl> 179std::string 180LSQUnit<Impl>::name() const 181{ 182 if (Impl::MaxThreads == 1) { 183 return iewStage->name() + ".lsq"; 184 } else { 185 return iewStage->name() + ".lsq.thread." + to_string(lsqID); 186 } 187} 188 189template<class Impl> 190void 191LSQUnit<Impl>::regStats() 192{ 193 lsqForwLoads 194 .name(name() + ".forwLoads") 195 .desc("Number of loads that had data forwarded from stores"); 196 197 invAddrLoads 198 .name(name() + ".invAddrLoads") 199 .desc("Number of loads ignored due to an invalid address"); 200 201 lsqSquashedLoads 202 .name(name() + ".squashedLoads") 203 .desc("Number of loads squashed"); 204 205 lsqIgnoredResponses 206 .name(name() + ".ignoredResponses") 207 .desc("Number of memory responses ignored because the instruction is squashed"); 208 209 lsqMemOrderViolation 210 .name(name() + ".memOrderViolation") 211 .desc("Number of memory ordering violations"); 212 213 lsqSquashedStores 214 .name(name() + ".squashedStores") 215 .desc("Number of stores squashed"); 216 217 invAddrSwpfs 218 .name(name() + ".invAddrSwpfs") 219 .desc("Number of software prefetches ignored due to an invalid address"); 220 221 lsqBlockedLoads 222 .name(name() + ".blockedLoads") 223 .desc("Number of blocked loads due to partial load-store forwarding"); 224 225 lsqRescheduledLoads 226 .name(name() + ".rescheduledLoads") 227 .desc("Number of loads that were rescheduled"); 228 229 lsqCacheBlocked 230 .name(name() + ".cacheBlocked") 231 .desc("Number of times an access to memory failed due to the cache being blocked"); 232} 233 234template<class Impl> 235void 236LSQUnit<Impl>::setDcachePort(Port *dcache_port) 237{ 238 dcachePort = dcache_port; 239 240#if USE_CHECKER 241 if (cpu->checker) { 242 cpu->checker->setDcachePort(dcachePort); 243 } 244#endif 245} 246 247template<class Impl> 248void 249LSQUnit<Impl>::clearLQ() 250{ 251 loadQueue.clear(); 252} 253 254template<class Impl> 255void 256LSQUnit<Impl>::clearSQ() 257{ 258 storeQueue.clear(); 259} 260 261template<class Impl> 262void 263LSQUnit<Impl>::switchOut() 264{ 265 switchedOut = true; 266 for (int i = 0; i < loadQueue.size(); ++i) { 267 assert(!loadQueue[i]); 268 loadQueue[i] = NULL; 269 } 270 271 assert(storesToWB == 0); 272} 273 274template<class Impl> 275void 276LSQUnit<Impl>::takeOverFrom() 277{ 278 switchedOut = false; 279 loads = stores = storesToWB = 0; 280 281 loadHead = loadTail = 0; 282 283 storeHead = storeWBIdx = storeTail = 0; 284 285 usedPorts = 0; 286 287 memDepViolator = NULL; 288 289 blockedLoadSeqNum = 0; 290 291 stalled = false; 292 isLoadBlocked = false; 293 loadBlockedHandled = false; 294} 295 296template<class Impl> 297void 298LSQUnit<Impl>::resizeLQ(unsigned size) 299{ 300 unsigned size_plus_sentinel = size + 1; 301 assert(size_plus_sentinel >= LQEntries); 302 303 if (size_plus_sentinel > LQEntries) { 304 while (size_plus_sentinel > loadQueue.size()) { 305 DynInstPtr dummy; 306 loadQueue.push_back(dummy); 307 LQEntries++; 308 } 309 } else { 310 LQEntries = size_plus_sentinel; 311 } 312 313} 314 315template<class Impl> 316void 317LSQUnit<Impl>::resizeSQ(unsigned size) 318{ 319 unsigned size_plus_sentinel = size + 1; 320 if (size_plus_sentinel > SQEntries) { 321 while (size_plus_sentinel > storeQueue.size()) { 322 SQEntry dummy; 323 storeQueue.push_back(dummy); 324 SQEntries++; 325 } 326 } else { 327 SQEntries = size_plus_sentinel; 328 } 329} 330 331template <class Impl> 332void 333LSQUnit<Impl>::insert(DynInstPtr &inst) 334{ 335 assert(inst->isMemRef()); 336 337 assert(inst->isLoad() || inst->isStore()); 338 339 if (inst->isLoad()) { 340 insertLoad(inst); 341 } else { 342 insertStore(inst); 343 } 344 345 inst->setInLSQ(); 346} 347 348template <class Impl> 349void 350LSQUnit<Impl>::insertLoad(DynInstPtr &load_inst) 351{ 352 assert((loadTail + 1) % LQEntries != loadHead); 353 assert(loads < LQEntries); 354 355 DPRINTF(LSQUnit, "Inserting load PC %s, idx:%i [sn:%lli]\n", 356 load_inst->pcState(), loadTail, load_inst->seqNum); 357 358 load_inst->lqIdx = loadTail; 359 360 if (stores == 0) { 361 load_inst->sqIdx = -1; 362 } else { 363 load_inst->sqIdx = storeTail; 364 } 365 366 loadQueue[loadTail] = load_inst; 367 368 incrLdIdx(loadTail); 369 370 ++loads; 371} 372 373template <class Impl> 374void 375LSQUnit<Impl>::insertStore(DynInstPtr &store_inst) 376{ 377 // Make sure it is not full before inserting an instruction. 378 assert((storeTail + 1) % SQEntries != storeHead); 379 assert(stores < SQEntries); 380 381 DPRINTF(LSQUnit, "Inserting store PC %s, idx:%i [sn:%lli]\n", 382 store_inst->pcState(), storeTail, store_inst->seqNum); 383 384 store_inst->sqIdx = storeTail; 385 store_inst->lqIdx = loadTail; 386 387 storeQueue[storeTail] = SQEntry(store_inst); 388 389 incrStIdx(storeTail); 390 391 ++stores; 392} 393 394template <class Impl> 395typename Impl::DynInstPtr 396LSQUnit<Impl>::getMemDepViolator() 397{ 398 DynInstPtr temp = memDepViolator; 399 400 memDepViolator = NULL; 401 402 return temp; 403} 404 405template <class Impl> 406unsigned 407LSQUnit<Impl>::numFreeEntries() 408{ 409 unsigned free_lq_entries = LQEntries - loads; 410 unsigned free_sq_entries = SQEntries - stores; 411 412 // Both the LQ and SQ entries have an extra dummy entry to differentiate 413 // empty/full conditions. Subtract 1 from the free entries. 414 if (free_lq_entries < free_sq_entries) { 415 return free_lq_entries - 1; 416 } else { 417 return free_sq_entries - 1; 418 } 419} 420 421template <class Impl> 422int 423LSQUnit<Impl>::numLoadsReady() 424{ 425 int load_idx = loadHead; 426 int retval = 0; 427 428 while (load_idx != loadTail) { 429 assert(loadQueue[load_idx]); 430 431 if (loadQueue[load_idx]->readyToIssue()) { 432 ++retval; 433 } 434 } 435 436 return retval; 437} 438 439template <class Impl> 440Fault 441LSQUnit<Impl>::executeLoad(DynInstPtr &inst) 442{ 443 using namespace TheISA; 444 // Execute a specific load. 445 Fault load_fault = NoFault; 446 447 DPRINTF(LSQUnit, "Executing load PC %s, [sn:%lli]\n", 448 inst->pcState(),inst->seqNum); 449 450 assert(!inst->isSquashed()); 451 452 load_fault = inst->initiateAcc(); 453 454 // If the instruction faulted or predicated false, then we need to send it 455 // along to commit without the instruction completing. 456 if (load_fault != NoFault || inst->readPredicate() == false) { 457 // Send this instruction to commit, also make sure iew stage 458 // realizes there is activity. 459 // Mark it as executed unless it is an uncached load that 460 // needs to hit the head of commit. 461 if (inst->readPredicate() == false) 462 inst->forwardOldRegs(); 463 DPRINTF(LSQUnit, "Load [sn:%lli] not executed from %s\n", 464 inst->seqNum, 465 (load_fault != NoFault ? "fault" : "predication")); 466 if (!(inst->hasRequest() && inst->uncacheable()) || 467 inst->isAtCommit()) { 468 inst->setExecuted(); 469 } 470 iewStage->instToCommit(inst); 471 iewStage->activityThisCycle(); 472 } else if (!loadBlocked()) { 473 assert(inst->effAddrValid); 474 int load_idx = inst->lqIdx; 475 incrLdIdx(load_idx); 476 while (load_idx != loadTail) { 477 // Really only need to check loads that have actually executed 478 479 // @todo: For now this is extra conservative, detecting a 480 // violation if the addresses match assuming all accesses 481 // are quad word accesses. 482 483 // @todo: Fix this, magic number being used here 484 485 // @todo: Uncachable load is not executed until it reaches 486 // the head of the ROB. Once this if checks only the executed 487 // loads(as noted above), this check can be removed 488 if (loadQueue[load_idx]->effAddrValid && 489 ((loadQueue[load_idx]->effAddr >> 8) 490 == (inst->effAddr >> 8)) && 491 !loadQueue[load_idx]->uncacheable()) { 492 // A load incorrectly passed this load. Squash and refetch. 493 // For now return a fault to show that it was unsuccessful. 494 DynInstPtr violator = loadQueue[load_idx]; 495 if (!memDepViolator || 496 (violator->seqNum < memDepViolator->seqNum)) { 497 memDepViolator = violator; 498 } else { 499 break; 500 } 501 502 ++lsqMemOrderViolation; 503 504 return genMachineCheckFault(); 505 } 506 507 incrLdIdx(load_idx); 508 } 509 } 510 511 return load_fault; 512} 513 514template <class Impl> 515Fault 516LSQUnit<Impl>::executeStore(DynInstPtr &store_inst) 517{ 518 using namespace TheISA; 519 // Make sure that a store exists. 520 assert(stores != 0); 521 522 int store_idx = store_inst->sqIdx; 523 524 DPRINTF(LSQUnit, "Executing store PC %s [sn:%lli]\n", 525 store_inst->pcState(), store_inst->seqNum); 526 527 assert(!store_inst->isSquashed()); 528 529 // Check the recently completed loads to see if any match this store's 530 // address. If so, then we have a memory ordering violation. 531 int load_idx = store_inst->lqIdx; 532 533 Fault store_fault = store_inst->initiateAcc(); 534 535 if (store_inst->readPredicate() == false) 536 store_inst->forwardOldRegs(); 537 538 if (storeQueue[store_idx].size == 0) { 539 DPRINTF(LSQUnit,"Fault on Store PC %s, [sn:%lli], Size = 0\n", 540 store_inst->pcState(), store_inst->seqNum); 541 542 return store_fault; 543 } else if (store_inst->readPredicate() == false) { 544 DPRINTF(LSQUnit, "Store [sn:%lli] not executed from predication\n", 545 store_inst->seqNum); 546 return store_fault; 547 } 548 549 assert(store_fault == NoFault); 550 551 if (store_inst->isStoreConditional()) { 552 // Store conditionals need to set themselves as able to 553 // writeback if we haven't had a fault by here. 554 storeQueue[store_idx].canWB = true; 555 556 ++storesToWB; 557 } 558 559 assert(store_inst->effAddrValid); 560 while (load_idx != loadTail) { 561 // Really only need to check loads that have actually executed 562 // It's safe to check all loads because effAddr is set to 563 // InvalAddr when the dyn inst is created. 564 565 // @todo: For now this is extra conservative, detecting a 566 // violation if the addresses match assuming all accesses 567 // are quad word accesses. 568 569 // @todo: Fix this, magic number being used here 570 571 // @todo: Uncachable load is not executed until it reaches 572 // the head of the ROB. Once this if checks only the executed 573 // loads(as noted above), this check can be removed 574 if (loadQueue[load_idx]->effAddrValid && 575 ((loadQueue[load_idx]->effAddr >> 8) 576 == (store_inst->effAddr >> 8)) && 577 !loadQueue[load_idx]->uncacheable()) { 578 // A load incorrectly passed this store. Squash and refetch. 579 // For now return a fault to show that it was unsuccessful. 580 DynInstPtr violator = loadQueue[load_idx]; 581 if (!memDepViolator || 582 (violator->seqNum < memDepViolator->seqNum)) { 583 memDepViolator = violator; 584 } else { 585 break; 586 } 587 588 ++lsqMemOrderViolation; 589 590 return genMachineCheckFault(); 591 } 592 593 incrLdIdx(load_idx); 594 } 595 596 return store_fault; 597} 598 599template <class Impl> 600void 601LSQUnit<Impl>::commitLoad() 602{ 603 assert(loadQueue[loadHead]); 604 605 DPRINTF(LSQUnit, "Committing head load instruction, PC %s\n", 606 loadQueue[loadHead]->pcState()); 607 608 loadQueue[loadHead] = NULL; 609 610 incrLdIdx(loadHead); 611 612 --loads; 613} 614 615template <class Impl> 616void 617LSQUnit<Impl>::commitLoads(InstSeqNum &youngest_inst) 618{ 619 assert(loads == 0 || loadQueue[loadHead]); 620 621 while (loads != 0 && loadQueue[loadHead]->seqNum <= youngest_inst) { 622 commitLoad(); 623 } 624} 625 626template <class Impl> 627void 628LSQUnit<Impl>::commitStores(InstSeqNum &youngest_inst) 629{ 630 assert(stores == 0 || storeQueue[storeHead].inst); 631 632 int store_idx = storeHead; 633 634 while (store_idx != storeTail) { 635 assert(storeQueue[store_idx].inst); 636 // Mark any stores that are now committed and have not yet 637 // been marked as able to write back. 638 if (!storeQueue[store_idx].canWB) { 639 if (storeQueue[store_idx].inst->seqNum > youngest_inst) { 640 break; 641 } 642 DPRINTF(LSQUnit, "Marking store as able to write back, PC " 643 "%s [sn:%lli]\n", 644 storeQueue[store_idx].inst->pcState(), 645 storeQueue[store_idx].inst->seqNum); 646 647 storeQueue[store_idx].canWB = true; 648 649 ++storesToWB; 650 } 651 652 incrStIdx(store_idx); 653 } 654} 655 656template <class Impl> 657void 658LSQUnit<Impl>::writebackPendingStore() 659{ 660 if (hasPendingPkt) { 661 assert(pendingPkt != NULL); 662 663 // If the cache is blocked, this will store the packet for retry. 664 if (sendStore(pendingPkt)) { 665 storePostSend(pendingPkt); 666 } 667 pendingPkt = NULL; 668 hasPendingPkt = false; 669 } 670} 671 672template <class Impl> 673void 674LSQUnit<Impl>::writebackStores() 675{ 676 // First writeback the second packet from any split store that didn't 677 // complete last cycle because there weren't enough cache ports available. 678 if (TheISA::HasUnalignedMemAcc) { 679 writebackPendingStore(); 680 } 681 682 while (storesToWB > 0 && 683 storeWBIdx != storeTail && 684 storeQueue[storeWBIdx].inst && 685 storeQueue[storeWBIdx].canWB && 686 usedPorts < cachePorts) { 687 688 if (isStoreBlocked || lsq->cacheBlocked()) { 689 DPRINTF(LSQUnit, "Unable to write back any more stores, cache" 690 " is blocked!\n"); 691 break; 692 } 693 694 // Store didn't write any data so no need to write it back to 695 // memory. 696 if (storeQueue[storeWBIdx].size == 0) { 697 completeStore(storeWBIdx); 698 699 incrStIdx(storeWBIdx); 700 701 continue; 702 } 703 704 ++usedPorts; 705 706 if (storeQueue[storeWBIdx].inst->isDataPrefetch()) { 707 incrStIdx(storeWBIdx); 708 709 continue; 710 } 711 712 assert(storeQueue[storeWBIdx].req); 713 assert(!storeQueue[storeWBIdx].committed); 714 715 if (TheISA::HasUnalignedMemAcc && storeQueue[storeWBIdx].isSplit) { 716 assert(storeQueue[storeWBIdx].sreqLow); 717 assert(storeQueue[storeWBIdx].sreqHigh); 718 } 719 720 DynInstPtr inst = storeQueue[storeWBIdx].inst; 721 722 Request *req = storeQueue[storeWBIdx].req; 723 storeQueue[storeWBIdx].committed = true; 724 725 assert(!inst->memData); 726 inst->memData = new uint8_t[64]; 727 728 memcpy(inst->memData, storeQueue[storeWBIdx].data, req->getSize()); 729 730 MemCmd command = 731 req->isSwap() ? MemCmd::SwapReq : 732 (req->isLLSC() ? MemCmd::StoreCondReq : MemCmd::WriteReq); 733 PacketPtr data_pkt; 734 PacketPtr snd_data_pkt = NULL; 735 736 LSQSenderState *state = new LSQSenderState; 737 state->isLoad = false; 738 state->idx = storeWBIdx; 739 state->inst = inst; 740 741 if (!TheISA::HasUnalignedMemAcc || !storeQueue[storeWBIdx].isSplit) { 742 743 // Build a single data packet if the store isn't split. 744 data_pkt = new Packet(req, command, Packet::Broadcast); 745 data_pkt->dataStatic(inst->memData); 746 data_pkt->senderState = state; 747 } else { 748 RequestPtr sreqLow = storeQueue[storeWBIdx].sreqLow; 749 RequestPtr sreqHigh = storeQueue[storeWBIdx].sreqHigh; 750 751 // Create two packets if the store is split in two. 752 data_pkt = new Packet(sreqLow, command, Packet::Broadcast); 753 snd_data_pkt = new Packet(sreqHigh, command, Packet::Broadcast); 754 755 data_pkt->dataStatic(inst->memData); 756 snd_data_pkt->dataStatic(inst->memData + sreqLow->getSize()); 757 758 data_pkt->senderState = state; 759 snd_data_pkt->senderState = state; 760 761 state->isSplit = true; 762 state->outstanding = 2; 763 764 // Can delete the main request now. 765 delete req; 766 req = sreqLow; 767 } 768 769 DPRINTF(LSQUnit, "D-Cache: Writing back store idx:%i PC:%s " 770 "to Addr:%#x, data:%#x [sn:%lli]\n", 771 storeWBIdx, inst->pcState(), 772 req->getPaddr(), (int)*(inst->memData), 773 inst->seqNum); 774 775 // @todo: Remove this SC hack once the memory system handles it. 776 if (inst->isStoreConditional()) { 777 assert(!storeQueue[storeWBIdx].isSplit); 778 // Disable recording the result temporarily. Writing to 779 // misc regs normally updates the result, but this is not 780 // the desired behavior when handling store conditionals. 781 inst->recordResult = false; 782 bool success = TheISA::handleLockedWrite(inst.get(), req); 783 inst->recordResult = true; 784 785 if (!success) { 786 // Instantly complete this store. 787 DPRINTF(LSQUnit, "Store conditional [sn:%lli] failed. " 788 "Instantly completing it.\n", 789 inst->seqNum); 790 WritebackEvent *wb = new WritebackEvent(inst, data_pkt, this); 791 cpu->schedule(wb, curTick() + 1); 792 completeStore(storeWBIdx); 793 incrStIdx(storeWBIdx); 794 continue; 795 } 796 } else { 797 // Non-store conditionals do not need a writeback. 798 state->noWB = true; 799 } 800 801 if (!sendStore(data_pkt)) { 802 DPRINTF(IEW, "D-Cache became blocked when writing [sn:%lli], will" 803 "retry later\n", 804 inst->seqNum); 805 806 // Need to store the second packet, if split. 807 if (TheISA::HasUnalignedMemAcc && storeQueue[storeWBIdx].isSplit) { 808 state->pktToSend = true; 809 state->pendingPacket = snd_data_pkt; 810 } 811 } else { 812 813 // If split, try to send the second packet too 814 if (TheISA::HasUnalignedMemAcc && storeQueue[storeWBIdx].isSplit) { 815 assert(snd_data_pkt); 816 817 // Ensure there are enough ports to use. 818 if (usedPorts < cachePorts) { 819 ++usedPorts; 820 if (sendStore(snd_data_pkt)) { 821 storePostSend(snd_data_pkt); 822 } else { 823 DPRINTF(IEW, "D-Cache became blocked when writing" 824 " [sn:%lli] second packet, will retry later\n", 825 inst->seqNum); 826 } 827 } else { 828 829 // Store the packet for when there's free ports. 830 assert(pendingPkt == NULL); 831 pendingPkt = snd_data_pkt; 832 hasPendingPkt = true; 833 } 834 } else { 835 836 // Not a split store. 837 storePostSend(data_pkt); 838 } 839 } 840 } 841 842 // Not sure this should set it to 0. 843 usedPorts = 0; 844 845 assert(stores >= 0 && storesToWB >= 0); 846} 847 848/*template <class Impl> 849void 850LSQUnit<Impl>::removeMSHR(InstSeqNum seqNum) 851{ 852 list<InstSeqNum>::iterator mshr_it = find(mshrSeqNums.begin(), 853 mshrSeqNums.end(), 854 seqNum); 855 856 if (mshr_it != mshrSeqNums.end()) { 857 mshrSeqNums.erase(mshr_it); 858 DPRINTF(LSQUnit, "Removing MSHR. count = %i\n",mshrSeqNums.size()); 859 } 860}*/ 861 862template <class Impl> 863void 864LSQUnit<Impl>::squash(const InstSeqNum &squashed_num) 865{ 866 DPRINTF(LSQUnit, "Squashing until [sn:%lli]!" 867 "(Loads:%i Stores:%i)\n", squashed_num, loads, stores); 868 869 int load_idx = loadTail; 870 decrLdIdx(load_idx); 871 872 while (loads != 0 && loadQueue[load_idx]->seqNum > squashed_num) { 873 DPRINTF(LSQUnit,"Load Instruction PC %s squashed, " 874 "[sn:%lli]\n", 875 loadQueue[load_idx]->pcState(), 876 loadQueue[load_idx]->seqNum); 877 878 if (isStalled() && load_idx == stallingLoadIdx) { 879 stalled = false; 880 stallingStoreIsn = 0; 881 stallingLoadIdx = 0; 882 } 883 884 // Clear the smart pointer to make sure it is decremented. 885 loadQueue[load_idx]->setSquashed(); 886 loadQueue[load_idx] = NULL; 887 --loads; 888 889 // Inefficient! 890 loadTail = load_idx; 891 892 decrLdIdx(load_idx); 893 ++lsqSquashedLoads; 894 } 895 896 if (isLoadBlocked) { 897 if (squashed_num < blockedLoadSeqNum) { 898 isLoadBlocked = false; 899 loadBlockedHandled = false; 900 blockedLoadSeqNum = 0; 901 } 902 } 903 904 if (memDepViolator && squashed_num < memDepViolator->seqNum) { 905 memDepViolator = NULL; 906 } 907 908 int store_idx = storeTail; 909 decrStIdx(store_idx); 910 911 while (stores != 0 && 912 storeQueue[store_idx].inst->seqNum > squashed_num) { 913 // Instructions marked as can WB are already committed. 914 if (storeQueue[store_idx].canWB) { 915 break; 916 } 917 918 DPRINTF(LSQUnit,"Store Instruction PC %s squashed, " 919 "idx:%i [sn:%lli]\n", 920 storeQueue[store_idx].inst->pcState(), 921 store_idx, storeQueue[store_idx].inst->seqNum); 922 923 // I don't think this can happen. It should have been cleared 924 // by the stalling load. 925 if (isStalled() && 926 storeQueue[store_idx].inst->seqNum == stallingStoreIsn) { 927 panic("Is stalled should have been cleared by stalling load!\n"); 928 stalled = false; 929 stallingStoreIsn = 0; 930 } 931 932 // Clear the smart pointer to make sure it is decremented. 933 storeQueue[store_idx].inst->setSquashed(); 934 storeQueue[store_idx].inst = NULL; 935 storeQueue[store_idx].canWB = 0; 936 937 // Must delete request now that it wasn't handed off to 938 // memory. This is quite ugly. @todo: Figure out the proper 939 // place to really handle request deletes. 940 delete storeQueue[store_idx].req; 941 if (TheISA::HasUnalignedMemAcc && storeQueue[store_idx].isSplit) { 942 delete storeQueue[store_idx].sreqLow; 943 delete storeQueue[store_idx].sreqHigh; 944 945 storeQueue[store_idx].sreqLow = NULL; 946 storeQueue[store_idx].sreqHigh = NULL; 947 } 948 949 storeQueue[store_idx].req = NULL; 950 --stores; 951 952 // Inefficient! 953 storeTail = store_idx; 954 955 decrStIdx(store_idx); 956 ++lsqSquashedStores; 957 } 958} 959 960template <class Impl> 961void 962LSQUnit<Impl>::storePostSend(PacketPtr pkt) 963{ 964 if (isStalled() && 965 storeQueue[storeWBIdx].inst->seqNum == stallingStoreIsn) { 966 DPRINTF(LSQUnit, "Unstalling, stalling store [sn:%lli] " 967 "load idx:%i\n", 968 stallingStoreIsn, stallingLoadIdx); 969 stalled = false; 970 stallingStoreIsn = 0; 971 iewStage->replayMemInst(loadQueue[stallingLoadIdx]); 972 } 973 974 if (!storeQueue[storeWBIdx].inst->isStoreConditional()) { 975 // The store is basically completed at this time. This 976 // only works so long as the checker doesn't try to 977 // verify the value in memory for stores. 978 storeQueue[storeWBIdx].inst->setCompleted(); 979#if USE_CHECKER 980 if (cpu->checker) { 981 cpu->checker->verify(storeQueue[storeWBIdx].inst); 982 } 983#endif 984 } 985 986 incrStIdx(storeWBIdx); 987} 988 989template <class Impl> 990void 991LSQUnit<Impl>::writeback(DynInstPtr &inst, PacketPtr pkt) 992{ 993 iewStage->wakeCPU(); 994 995 // Squashed instructions do not need to complete their access. 996 if (inst->isSquashed()) { 997 iewStage->decrWb(inst->seqNum); 998 assert(!inst->isStore()); 999 ++lsqIgnoredResponses; 1000 return; 1001 } 1002 1003 if (!inst->isExecuted()) { 1004 inst->setExecuted(); 1005 1006 // Complete access to copy data to proper place. 1007 inst->completeAcc(pkt); 1008 } 1009 1010 // Need to insert instruction into queue to commit 1011 iewStage->instToCommit(inst); 1012 1013 iewStage->activityThisCycle(); 1014 1015 // see if this load changed the PC 1016 iewStage->checkMisprediction(inst); 1017} 1018 1019template <class Impl> 1020void 1021LSQUnit<Impl>::completeStore(int store_idx) 1022{ 1023 assert(storeQueue[store_idx].inst); 1024 storeQueue[store_idx].completed = true; 1025 --storesToWB; 1026 // A bit conservative because a store completion may not free up entries, 1027 // but hopefully avoids two store completions in one cycle from making 1028 // the CPU tick twice. 1029 cpu->wakeCPU(); 1030 cpu->activityThisCycle(); 1031 1032 if (store_idx == storeHead) { 1033 do { 1034 incrStIdx(storeHead); 1035 1036 --stores; 1037 } while (storeQueue[storeHead].completed && 1038 storeHead != storeTail); 1039 1040 iewStage->updateLSQNextCycle = true; 1041 } 1042 1043 DPRINTF(LSQUnit, "Completing store [sn:%lli], idx:%i, store head " 1044 "idx:%i\n", 1045 storeQueue[store_idx].inst->seqNum, store_idx, storeHead); 1046 1047 if (isStalled() && 1048 storeQueue[store_idx].inst->seqNum == stallingStoreIsn) { 1049 DPRINTF(LSQUnit, "Unstalling, stalling store [sn:%lli] " 1050 "load idx:%i\n", 1051 stallingStoreIsn, stallingLoadIdx); 1052 stalled = false; 1053 stallingStoreIsn = 0; 1054 iewStage->replayMemInst(loadQueue[stallingLoadIdx]); 1055 } 1056 1057 storeQueue[store_idx].inst->setCompleted(); 1058 1059 // Tell the checker we've completed this instruction. Some stores 1060 // may get reported twice to the checker, but the checker can 1061 // handle that case. 1062#if USE_CHECKER 1063 if (cpu->checker) { 1064 cpu->checker->verify(storeQueue[store_idx].inst); 1065 } 1066#endif 1067} 1068 1069template <class Impl> 1070bool 1071LSQUnit<Impl>::sendStore(PacketPtr data_pkt) 1072{ 1073 if (!dcachePort->sendTiming(data_pkt)) { 1074 // Need to handle becoming blocked on a store. 1075 isStoreBlocked = true; 1076 ++lsqCacheBlocked; 1077 assert(retryPkt == NULL); 1078 retryPkt = data_pkt; 1079 lsq->setRetryTid(lsqID); 1080 return false; 1081 } 1082 return true; 1083} 1084 1085template <class Impl> 1086void 1087LSQUnit<Impl>::recvRetry() 1088{ 1089 if (isStoreBlocked) { 1090 DPRINTF(LSQUnit, "Receiving retry: store blocked\n"); 1091 assert(retryPkt != NULL); 1092 1093 if (dcachePort->sendTiming(retryPkt)) { 1094 LSQSenderState *state = 1095 dynamic_cast<LSQSenderState *>(retryPkt->senderState); 1096 1097 // Don't finish the store unless this is the last packet. 1098 if (!TheISA::HasUnalignedMemAcc || !state->pktToSend) { 1099 storePostSend(retryPkt); 1100 } 1101 retryPkt = NULL; 1102 isStoreBlocked = false; 1103 lsq->setRetryTid(InvalidThreadID); 1104 1105 // Send any outstanding packet. 1106 if (TheISA::HasUnalignedMemAcc && state->pktToSend) { 1107 assert(state->pendingPacket); 1108 if (sendStore(state->pendingPacket)) { 1109 storePostSend(state->pendingPacket); 1110 } 1111 } 1112 } else { 1113 // Still blocked! 1114 ++lsqCacheBlocked; 1115 lsq->setRetryTid(lsqID); 1116 } 1117 } else if (isLoadBlocked) { 1118 DPRINTF(LSQUnit, "Loads squash themselves and all younger insts, " 1119 "no need to resend packet.\n"); 1120 } else { 1121 DPRINTF(LSQUnit, "Retry received but LSQ is no longer blocked.\n"); 1122 } 1123} 1124 1125template <class Impl> 1126inline void 1127LSQUnit<Impl>::incrStIdx(int &store_idx) 1128{ 1129 if (++store_idx >= SQEntries) 1130 store_idx = 0; 1131} 1132 1133template <class Impl> 1134inline void 1135LSQUnit<Impl>::decrStIdx(int &store_idx) 1136{ 1137 if (--store_idx < 0) 1138 store_idx += SQEntries; 1139} 1140 1141template <class Impl> 1142inline void 1143LSQUnit<Impl>::incrLdIdx(int &load_idx) 1144{ 1145 if (++load_idx >= LQEntries) 1146 load_idx = 0; 1147} 1148 1149template <class Impl> 1150inline void 1151LSQUnit<Impl>::decrLdIdx(int &load_idx) 1152{ 1153 if (--load_idx < 0) 1154 load_idx += LQEntries; 1155} 1156 1157template <class Impl> 1158void 1159LSQUnit<Impl>::dumpInsts() 1160{ 1161 cprintf("Load store queue: Dumping instructions.\n"); 1162 cprintf("Load queue size: %i\n", loads); 1163 cprintf("Load queue: "); 1164 1165 int load_idx = loadHead; 1166 1167 while (load_idx != loadTail && loadQueue[load_idx]) { 1168 cprintf("%s ", loadQueue[load_idx]->pcState()); 1169 1170 incrLdIdx(load_idx); 1171 } 1172 1173 cprintf("Store queue size: %i\n", stores); 1174 cprintf("Store queue: "); 1175 1176 int store_idx = storeHead; 1177 1178 while (store_idx != storeTail && storeQueue[store_idx].inst) { 1179 cprintf("%s ", storeQueue[store_idx].inst->pcState()); 1180 1181 incrStIdx(store_idx); 1182 } 1183 1184 cprintf("\n"); 1185}
| 95 96 //iewStage->ldstQueue.removeMSHR(inst->threadNumber,inst->seqNum); 97 98 assert(!pkt->wasNacked()); 99 100 // If this is a split access, wait until all packets are received. 101 if (TheISA::HasUnalignedMemAcc && !state->complete()) { 102 delete pkt->req; 103 delete pkt; 104 return; 105 } 106 107 if (isSwitchedOut() || inst->isSquashed()) { 108 iewStage->decrWb(inst->seqNum); 109 } else { 110 if (!state->noWB) { 111 if (!TheISA::HasUnalignedMemAcc || !state->isSplit || 112 !state->isLoad) { 113 writeback(inst, pkt); 114 } else { 115 writeback(inst, state->mainPkt); 116 } 117 } 118 119 if (inst->isStore()) { 120 completeStore(state->idx); 121 } 122 } 123 124 if (TheISA::HasUnalignedMemAcc && state->isSplit && state->isLoad) { 125 delete state->mainPkt->req; 126 delete state->mainPkt; 127 } 128 delete state; 129 delete pkt->req; 130 delete pkt; 131} 132 133template <class Impl> 134LSQUnit<Impl>::LSQUnit() 135 : loads(0), stores(0), storesToWB(0), stalled(false), 136 isStoreBlocked(false), isLoadBlocked(false), 137 loadBlockedHandled(false), hasPendingPkt(false) 138{ 139} 140 141template<class Impl> 142void 143LSQUnit<Impl>::init(O3CPU *cpu_ptr, IEW *iew_ptr, DerivO3CPUParams *params, 144 LSQ *lsq_ptr, unsigned maxLQEntries, unsigned maxSQEntries, 145 unsigned id) 146{ 147 cpu = cpu_ptr; 148 iewStage = iew_ptr; 149 150 DPRINTF(LSQUnit, "Creating LSQUnit%i object.\n",id); 151 152 switchedOut = false; 153 154 lsq = lsq_ptr; 155 156 lsqID = id; 157 158 // Add 1 for the sentinel entry (they are circular queues). 159 LQEntries = maxLQEntries + 1; 160 SQEntries = maxSQEntries + 1; 161 162 loadQueue.resize(LQEntries); 163 storeQueue.resize(SQEntries); 164 165 loadHead = loadTail = 0; 166 167 storeHead = storeWBIdx = storeTail = 0; 168 169 usedPorts = 0; 170 cachePorts = params->cachePorts; 171 172 retryPkt = NULL; 173 memDepViolator = NULL; 174 175 blockedLoadSeqNum = 0; 176} 177 178template<class Impl> 179std::string 180LSQUnit<Impl>::name() const 181{ 182 if (Impl::MaxThreads == 1) { 183 return iewStage->name() + ".lsq"; 184 } else { 185 return iewStage->name() + ".lsq.thread." + to_string(lsqID); 186 } 187} 188 189template<class Impl> 190void 191LSQUnit<Impl>::regStats() 192{ 193 lsqForwLoads 194 .name(name() + ".forwLoads") 195 .desc("Number of loads that had data forwarded from stores"); 196 197 invAddrLoads 198 .name(name() + ".invAddrLoads") 199 .desc("Number of loads ignored due to an invalid address"); 200 201 lsqSquashedLoads 202 .name(name() + ".squashedLoads") 203 .desc("Number of loads squashed"); 204 205 lsqIgnoredResponses 206 .name(name() + ".ignoredResponses") 207 .desc("Number of memory responses ignored because the instruction is squashed"); 208 209 lsqMemOrderViolation 210 .name(name() + ".memOrderViolation") 211 .desc("Number of memory ordering violations"); 212 213 lsqSquashedStores 214 .name(name() + ".squashedStores") 215 .desc("Number of stores squashed"); 216 217 invAddrSwpfs 218 .name(name() + ".invAddrSwpfs") 219 .desc("Number of software prefetches ignored due to an invalid address"); 220 221 lsqBlockedLoads 222 .name(name() + ".blockedLoads") 223 .desc("Number of blocked loads due to partial load-store forwarding"); 224 225 lsqRescheduledLoads 226 .name(name() + ".rescheduledLoads") 227 .desc("Number of loads that were rescheduled"); 228 229 lsqCacheBlocked 230 .name(name() + ".cacheBlocked") 231 .desc("Number of times an access to memory failed due to the cache being blocked"); 232} 233 234template<class Impl> 235void 236LSQUnit<Impl>::setDcachePort(Port *dcache_port) 237{ 238 dcachePort = dcache_port; 239 240#if USE_CHECKER 241 if (cpu->checker) { 242 cpu->checker->setDcachePort(dcachePort); 243 } 244#endif 245} 246 247template<class Impl> 248void 249LSQUnit<Impl>::clearLQ() 250{ 251 loadQueue.clear(); 252} 253 254template<class Impl> 255void 256LSQUnit<Impl>::clearSQ() 257{ 258 storeQueue.clear(); 259} 260 261template<class Impl> 262void 263LSQUnit<Impl>::switchOut() 264{ 265 switchedOut = true; 266 for (int i = 0; i < loadQueue.size(); ++i) { 267 assert(!loadQueue[i]); 268 loadQueue[i] = NULL; 269 } 270 271 assert(storesToWB == 0); 272} 273 274template<class Impl> 275void 276LSQUnit<Impl>::takeOverFrom() 277{ 278 switchedOut = false; 279 loads = stores = storesToWB = 0; 280 281 loadHead = loadTail = 0; 282 283 storeHead = storeWBIdx = storeTail = 0; 284 285 usedPorts = 0; 286 287 memDepViolator = NULL; 288 289 blockedLoadSeqNum = 0; 290 291 stalled = false; 292 isLoadBlocked = false; 293 loadBlockedHandled = false; 294} 295 296template<class Impl> 297void 298LSQUnit<Impl>::resizeLQ(unsigned size) 299{ 300 unsigned size_plus_sentinel = size + 1; 301 assert(size_plus_sentinel >= LQEntries); 302 303 if (size_plus_sentinel > LQEntries) { 304 while (size_plus_sentinel > loadQueue.size()) { 305 DynInstPtr dummy; 306 loadQueue.push_back(dummy); 307 LQEntries++; 308 } 309 } else { 310 LQEntries = size_plus_sentinel; 311 } 312 313} 314 315template<class Impl> 316void 317LSQUnit<Impl>::resizeSQ(unsigned size) 318{ 319 unsigned size_plus_sentinel = size + 1; 320 if (size_plus_sentinel > SQEntries) { 321 while (size_plus_sentinel > storeQueue.size()) { 322 SQEntry dummy; 323 storeQueue.push_back(dummy); 324 SQEntries++; 325 } 326 } else { 327 SQEntries = size_plus_sentinel; 328 } 329} 330 331template <class Impl> 332void 333LSQUnit<Impl>::insert(DynInstPtr &inst) 334{ 335 assert(inst->isMemRef()); 336 337 assert(inst->isLoad() || inst->isStore()); 338 339 if (inst->isLoad()) { 340 insertLoad(inst); 341 } else { 342 insertStore(inst); 343 } 344 345 inst->setInLSQ(); 346} 347 348template <class Impl> 349void 350LSQUnit<Impl>::insertLoad(DynInstPtr &load_inst) 351{ 352 assert((loadTail + 1) % LQEntries != loadHead); 353 assert(loads < LQEntries); 354 355 DPRINTF(LSQUnit, "Inserting load PC %s, idx:%i [sn:%lli]\n", 356 load_inst->pcState(), loadTail, load_inst->seqNum); 357 358 load_inst->lqIdx = loadTail; 359 360 if (stores == 0) { 361 load_inst->sqIdx = -1; 362 } else { 363 load_inst->sqIdx = storeTail; 364 } 365 366 loadQueue[loadTail] = load_inst; 367 368 incrLdIdx(loadTail); 369 370 ++loads; 371} 372 373template <class Impl> 374void 375LSQUnit<Impl>::insertStore(DynInstPtr &store_inst) 376{ 377 // Make sure it is not full before inserting an instruction. 378 assert((storeTail + 1) % SQEntries != storeHead); 379 assert(stores < SQEntries); 380 381 DPRINTF(LSQUnit, "Inserting store PC %s, idx:%i [sn:%lli]\n", 382 store_inst->pcState(), storeTail, store_inst->seqNum); 383 384 store_inst->sqIdx = storeTail; 385 store_inst->lqIdx = loadTail; 386 387 storeQueue[storeTail] = SQEntry(store_inst); 388 389 incrStIdx(storeTail); 390 391 ++stores; 392} 393 394template <class Impl> 395typename Impl::DynInstPtr 396LSQUnit<Impl>::getMemDepViolator() 397{ 398 DynInstPtr temp = memDepViolator; 399 400 memDepViolator = NULL; 401 402 return temp; 403} 404 405template <class Impl> 406unsigned 407LSQUnit<Impl>::numFreeEntries() 408{ 409 unsigned free_lq_entries = LQEntries - loads; 410 unsigned free_sq_entries = SQEntries - stores; 411 412 // Both the LQ and SQ entries have an extra dummy entry to differentiate 413 // empty/full conditions. Subtract 1 from the free entries. 414 if (free_lq_entries < free_sq_entries) { 415 return free_lq_entries - 1; 416 } else { 417 return free_sq_entries - 1; 418 } 419} 420 421template <class Impl> 422int 423LSQUnit<Impl>::numLoadsReady() 424{ 425 int load_idx = loadHead; 426 int retval = 0; 427 428 while (load_idx != loadTail) { 429 assert(loadQueue[load_idx]); 430 431 if (loadQueue[load_idx]->readyToIssue()) { 432 ++retval; 433 } 434 } 435 436 return retval; 437} 438 439template <class Impl> 440Fault 441LSQUnit<Impl>::executeLoad(DynInstPtr &inst) 442{ 443 using namespace TheISA; 444 // Execute a specific load. 445 Fault load_fault = NoFault; 446 447 DPRINTF(LSQUnit, "Executing load PC %s, [sn:%lli]\n", 448 inst->pcState(),inst->seqNum); 449 450 assert(!inst->isSquashed()); 451 452 load_fault = inst->initiateAcc(); 453 454 // If the instruction faulted or predicated false, then we need to send it 455 // along to commit without the instruction completing. 456 if (load_fault != NoFault || inst->readPredicate() == false) { 457 // Send this instruction to commit, also make sure iew stage 458 // realizes there is activity. 459 // Mark it as executed unless it is an uncached load that 460 // needs to hit the head of commit. 461 if (inst->readPredicate() == false) 462 inst->forwardOldRegs(); 463 DPRINTF(LSQUnit, "Load [sn:%lli] not executed from %s\n", 464 inst->seqNum, 465 (load_fault != NoFault ? "fault" : "predication")); 466 if (!(inst->hasRequest() && inst->uncacheable()) || 467 inst->isAtCommit()) { 468 inst->setExecuted(); 469 } 470 iewStage->instToCommit(inst); 471 iewStage->activityThisCycle(); 472 } else if (!loadBlocked()) { 473 assert(inst->effAddrValid); 474 int load_idx = inst->lqIdx; 475 incrLdIdx(load_idx); 476 while (load_idx != loadTail) { 477 // Really only need to check loads that have actually executed 478 479 // @todo: For now this is extra conservative, detecting a 480 // violation if the addresses match assuming all accesses 481 // are quad word accesses. 482 483 // @todo: Fix this, magic number being used here 484 485 // @todo: Uncachable load is not executed until it reaches 486 // the head of the ROB. Once this if checks only the executed 487 // loads(as noted above), this check can be removed 488 if (loadQueue[load_idx]->effAddrValid && 489 ((loadQueue[load_idx]->effAddr >> 8) 490 == (inst->effAddr >> 8)) && 491 !loadQueue[load_idx]->uncacheable()) { 492 // A load incorrectly passed this load. Squash and refetch. 493 // For now return a fault to show that it was unsuccessful. 494 DynInstPtr violator = loadQueue[load_idx]; 495 if (!memDepViolator || 496 (violator->seqNum < memDepViolator->seqNum)) { 497 memDepViolator = violator; 498 } else { 499 break; 500 } 501 502 ++lsqMemOrderViolation; 503 504 return genMachineCheckFault(); 505 } 506 507 incrLdIdx(load_idx); 508 } 509 } 510 511 return load_fault; 512} 513 514template <class Impl> 515Fault 516LSQUnit<Impl>::executeStore(DynInstPtr &store_inst) 517{ 518 using namespace TheISA; 519 // Make sure that a store exists. 520 assert(stores != 0); 521 522 int store_idx = store_inst->sqIdx; 523 524 DPRINTF(LSQUnit, "Executing store PC %s [sn:%lli]\n", 525 store_inst->pcState(), store_inst->seqNum); 526 527 assert(!store_inst->isSquashed()); 528 529 // Check the recently completed loads to see if any match this store's 530 // address. If so, then we have a memory ordering violation. 531 int load_idx = store_inst->lqIdx; 532 533 Fault store_fault = store_inst->initiateAcc(); 534 535 if (store_inst->readPredicate() == false) 536 store_inst->forwardOldRegs(); 537 538 if (storeQueue[store_idx].size == 0) { 539 DPRINTF(LSQUnit,"Fault on Store PC %s, [sn:%lli], Size = 0\n", 540 store_inst->pcState(), store_inst->seqNum); 541 542 return store_fault; 543 } else if (store_inst->readPredicate() == false) { 544 DPRINTF(LSQUnit, "Store [sn:%lli] not executed from predication\n", 545 store_inst->seqNum); 546 return store_fault; 547 } 548 549 assert(store_fault == NoFault); 550 551 if (store_inst->isStoreConditional()) { 552 // Store conditionals need to set themselves as able to 553 // writeback if we haven't had a fault by here. 554 storeQueue[store_idx].canWB = true; 555 556 ++storesToWB; 557 } 558 559 assert(store_inst->effAddrValid); 560 while (load_idx != loadTail) { 561 // Really only need to check loads that have actually executed 562 // It's safe to check all loads because effAddr is set to 563 // InvalAddr when the dyn inst is created. 564 565 // @todo: For now this is extra conservative, detecting a 566 // violation if the addresses match assuming all accesses 567 // are quad word accesses. 568 569 // @todo: Fix this, magic number being used here 570 571 // @todo: Uncachable load is not executed until it reaches 572 // the head of the ROB. Once this if checks only the executed 573 // loads(as noted above), this check can be removed 574 if (loadQueue[load_idx]->effAddrValid && 575 ((loadQueue[load_idx]->effAddr >> 8) 576 == (store_inst->effAddr >> 8)) && 577 !loadQueue[load_idx]->uncacheable()) { 578 // A load incorrectly passed this store. Squash and refetch. 579 // For now return a fault to show that it was unsuccessful. 580 DynInstPtr violator = loadQueue[load_idx]; 581 if (!memDepViolator || 582 (violator->seqNum < memDepViolator->seqNum)) { 583 memDepViolator = violator; 584 } else { 585 break; 586 } 587 588 ++lsqMemOrderViolation; 589 590 return genMachineCheckFault(); 591 } 592 593 incrLdIdx(load_idx); 594 } 595 596 return store_fault; 597} 598 599template <class Impl> 600void 601LSQUnit<Impl>::commitLoad() 602{ 603 assert(loadQueue[loadHead]); 604 605 DPRINTF(LSQUnit, "Committing head load instruction, PC %s\n", 606 loadQueue[loadHead]->pcState()); 607 608 loadQueue[loadHead] = NULL; 609 610 incrLdIdx(loadHead); 611 612 --loads; 613} 614 615template <class Impl> 616void 617LSQUnit<Impl>::commitLoads(InstSeqNum &youngest_inst) 618{ 619 assert(loads == 0 || loadQueue[loadHead]); 620 621 while (loads != 0 && loadQueue[loadHead]->seqNum <= youngest_inst) { 622 commitLoad(); 623 } 624} 625 626template <class Impl> 627void 628LSQUnit<Impl>::commitStores(InstSeqNum &youngest_inst) 629{ 630 assert(stores == 0 || storeQueue[storeHead].inst); 631 632 int store_idx = storeHead; 633 634 while (store_idx != storeTail) { 635 assert(storeQueue[store_idx].inst); 636 // Mark any stores that are now committed and have not yet 637 // been marked as able to write back. 638 if (!storeQueue[store_idx].canWB) { 639 if (storeQueue[store_idx].inst->seqNum > youngest_inst) { 640 break; 641 } 642 DPRINTF(LSQUnit, "Marking store as able to write back, PC " 643 "%s [sn:%lli]\n", 644 storeQueue[store_idx].inst->pcState(), 645 storeQueue[store_idx].inst->seqNum); 646 647 storeQueue[store_idx].canWB = true; 648 649 ++storesToWB; 650 } 651 652 incrStIdx(store_idx); 653 } 654} 655 656template <class Impl> 657void 658LSQUnit<Impl>::writebackPendingStore() 659{ 660 if (hasPendingPkt) { 661 assert(pendingPkt != NULL); 662 663 // If the cache is blocked, this will store the packet for retry. 664 if (sendStore(pendingPkt)) { 665 storePostSend(pendingPkt); 666 } 667 pendingPkt = NULL; 668 hasPendingPkt = false; 669 } 670} 671 672template <class Impl> 673void 674LSQUnit<Impl>::writebackStores() 675{ 676 // First writeback the second packet from any split store that didn't 677 // complete last cycle because there weren't enough cache ports available. 678 if (TheISA::HasUnalignedMemAcc) { 679 writebackPendingStore(); 680 } 681 682 while (storesToWB > 0 && 683 storeWBIdx != storeTail && 684 storeQueue[storeWBIdx].inst && 685 storeQueue[storeWBIdx].canWB && 686 usedPorts < cachePorts) { 687 688 if (isStoreBlocked || lsq->cacheBlocked()) { 689 DPRINTF(LSQUnit, "Unable to write back any more stores, cache" 690 " is blocked!\n"); 691 break; 692 } 693 694 // Store didn't write any data so no need to write it back to 695 // memory. 696 if (storeQueue[storeWBIdx].size == 0) { 697 completeStore(storeWBIdx); 698 699 incrStIdx(storeWBIdx); 700 701 continue; 702 } 703 704 ++usedPorts; 705 706 if (storeQueue[storeWBIdx].inst->isDataPrefetch()) { 707 incrStIdx(storeWBIdx); 708 709 continue; 710 } 711 712 assert(storeQueue[storeWBIdx].req); 713 assert(!storeQueue[storeWBIdx].committed); 714 715 if (TheISA::HasUnalignedMemAcc && storeQueue[storeWBIdx].isSplit) { 716 assert(storeQueue[storeWBIdx].sreqLow); 717 assert(storeQueue[storeWBIdx].sreqHigh); 718 } 719 720 DynInstPtr inst = storeQueue[storeWBIdx].inst; 721 722 Request *req = storeQueue[storeWBIdx].req; 723 storeQueue[storeWBIdx].committed = true; 724 725 assert(!inst->memData); 726 inst->memData = new uint8_t[64]; 727 728 memcpy(inst->memData, storeQueue[storeWBIdx].data, req->getSize()); 729 730 MemCmd command = 731 req->isSwap() ? MemCmd::SwapReq : 732 (req->isLLSC() ? MemCmd::StoreCondReq : MemCmd::WriteReq); 733 PacketPtr data_pkt; 734 PacketPtr snd_data_pkt = NULL; 735 736 LSQSenderState *state = new LSQSenderState; 737 state->isLoad = false; 738 state->idx = storeWBIdx; 739 state->inst = inst; 740 741 if (!TheISA::HasUnalignedMemAcc || !storeQueue[storeWBIdx].isSplit) { 742 743 // Build a single data packet if the store isn't split. 744 data_pkt = new Packet(req, command, Packet::Broadcast); 745 data_pkt->dataStatic(inst->memData); 746 data_pkt->senderState = state; 747 } else { 748 RequestPtr sreqLow = storeQueue[storeWBIdx].sreqLow; 749 RequestPtr sreqHigh = storeQueue[storeWBIdx].sreqHigh; 750 751 // Create two packets if the store is split in two. 752 data_pkt = new Packet(sreqLow, command, Packet::Broadcast); 753 snd_data_pkt = new Packet(sreqHigh, command, Packet::Broadcast); 754 755 data_pkt->dataStatic(inst->memData); 756 snd_data_pkt->dataStatic(inst->memData + sreqLow->getSize()); 757 758 data_pkt->senderState = state; 759 snd_data_pkt->senderState = state; 760 761 state->isSplit = true; 762 state->outstanding = 2; 763 764 // Can delete the main request now. 765 delete req; 766 req = sreqLow; 767 } 768 769 DPRINTF(LSQUnit, "D-Cache: Writing back store idx:%i PC:%s " 770 "to Addr:%#x, data:%#x [sn:%lli]\n", 771 storeWBIdx, inst->pcState(), 772 req->getPaddr(), (int)*(inst->memData), 773 inst->seqNum); 774 775 // @todo: Remove this SC hack once the memory system handles it. 776 if (inst->isStoreConditional()) { 777 assert(!storeQueue[storeWBIdx].isSplit); 778 // Disable recording the result temporarily. Writing to 779 // misc regs normally updates the result, but this is not 780 // the desired behavior when handling store conditionals. 781 inst->recordResult = false; 782 bool success = TheISA::handleLockedWrite(inst.get(), req); 783 inst->recordResult = true; 784 785 if (!success) { 786 // Instantly complete this store. 787 DPRINTF(LSQUnit, "Store conditional [sn:%lli] failed. " 788 "Instantly completing it.\n", 789 inst->seqNum); 790 WritebackEvent *wb = new WritebackEvent(inst, data_pkt, this); 791 cpu->schedule(wb, curTick() + 1); 792 completeStore(storeWBIdx); 793 incrStIdx(storeWBIdx); 794 continue; 795 } 796 } else { 797 // Non-store conditionals do not need a writeback. 798 state->noWB = true; 799 } 800 801 if (!sendStore(data_pkt)) { 802 DPRINTF(IEW, "D-Cache became blocked when writing [sn:%lli], will" 803 "retry later\n", 804 inst->seqNum); 805 806 // Need to store the second packet, if split. 807 if (TheISA::HasUnalignedMemAcc && storeQueue[storeWBIdx].isSplit) { 808 state->pktToSend = true; 809 state->pendingPacket = snd_data_pkt; 810 } 811 } else { 812 813 // If split, try to send the second packet too 814 if (TheISA::HasUnalignedMemAcc && storeQueue[storeWBIdx].isSplit) { 815 assert(snd_data_pkt); 816 817 // Ensure there are enough ports to use. 818 if (usedPorts < cachePorts) { 819 ++usedPorts; 820 if (sendStore(snd_data_pkt)) { 821 storePostSend(snd_data_pkt); 822 } else { 823 DPRINTF(IEW, "D-Cache became blocked when writing" 824 " [sn:%lli] second packet, will retry later\n", 825 inst->seqNum); 826 } 827 } else { 828 829 // Store the packet for when there's free ports. 830 assert(pendingPkt == NULL); 831 pendingPkt = snd_data_pkt; 832 hasPendingPkt = true; 833 } 834 } else { 835 836 // Not a split store. 837 storePostSend(data_pkt); 838 } 839 } 840 } 841 842 // Not sure this should set it to 0. 843 usedPorts = 0; 844 845 assert(stores >= 0 && storesToWB >= 0); 846} 847 848/*template <class Impl> 849void 850LSQUnit<Impl>::removeMSHR(InstSeqNum seqNum) 851{ 852 list<InstSeqNum>::iterator mshr_it = find(mshrSeqNums.begin(), 853 mshrSeqNums.end(), 854 seqNum); 855 856 if (mshr_it != mshrSeqNums.end()) { 857 mshrSeqNums.erase(mshr_it); 858 DPRINTF(LSQUnit, "Removing MSHR. count = %i\n",mshrSeqNums.size()); 859 } 860}*/ 861 862template <class Impl> 863void 864LSQUnit<Impl>::squash(const InstSeqNum &squashed_num) 865{ 866 DPRINTF(LSQUnit, "Squashing until [sn:%lli]!" 867 "(Loads:%i Stores:%i)\n", squashed_num, loads, stores); 868 869 int load_idx = loadTail; 870 decrLdIdx(load_idx); 871 872 while (loads != 0 && loadQueue[load_idx]->seqNum > squashed_num) { 873 DPRINTF(LSQUnit,"Load Instruction PC %s squashed, " 874 "[sn:%lli]\n", 875 loadQueue[load_idx]->pcState(), 876 loadQueue[load_idx]->seqNum); 877 878 if (isStalled() && load_idx == stallingLoadIdx) { 879 stalled = false; 880 stallingStoreIsn = 0; 881 stallingLoadIdx = 0; 882 } 883 884 // Clear the smart pointer to make sure it is decremented. 885 loadQueue[load_idx]->setSquashed(); 886 loadQueue[load_idx] = NULL; 887 --loads; 888 889 // Inefficient! 890 loadTail = load_idx; 891 892 decrLdIdx(load_idx); 893 ++lsqSquashedLoads; 894 } 895 896 if (isLoadBlocked) { 897 if (squashed_num < blockedLoadSeqNum) { 898 isLoadBlocked = false; 899 loadBlockedHandled = false; 900 blockedLoadSeqNum = 0; 901 } 902 } 903 904 if (memDepViolator && squashed_num < memDepViolator->seqNum) { 905 memDepViolator = NULL; 906 } 907 908 int store_idx = storeTail; 909 decrStIdx(store_idx); 910 911 while (stores != 0 && 912 storeQueue[store_idx].inst->seqNum > squashed_num) { 913 // Instructions marked as can WB are already committed. 914 if (storeQueue[store_idx].canWB) { 915 break; 916 } 917 918 DPRINTF(LSQUnit,"Store Instruction PC %s squashed, " 919 "idx:%i [sn:%lli]\n", 920 storeQueue[store_idx].inst->pcState(), 921 store_idx, storeQueue[store_idx].inst->seqNum); 922 923 // I don't think this can happen. It should have been cleared 924 // by the stalling load. 925 if (isStalled() && 926 storeQueue[store_idx].inst->seqNum == stallingStoreIsn) { 927 panic("Is stalled should have been cleared by stalling load!\n"); 928 stalled = false; 929 stallingStoreIsn = 0; 930 } 931 932 // Clear the smart pointer to make sure it is decremented. 933 storeQueue[store_idx].inst->setSquashed(); 934 storeQueue[store_idx].inst = NULL; 935 storeQueue[store_idx].canWB = 0; 936 937 // Must delete request now that it wasn't handed off to 938 // memory. This is quite ugly. @todo: Figure out the proper 939 // place to really handle request deletes. 940 delete storeQueue[store_idx].req; 941 if (TheISA::HasUnalignedMemAcc && storeQueue[store_idx].isSplit) { 942 delete storeQueue[store_idx].sreqLow; 943 delete storeQueue[store_idx].sreqHigh; 944 945 storeQueue[store_idx].sreqLow = NULL; 946 storeQueue[store_idx].sreqHigh = NULL; 947 } 948 949 storeQueue[store_idx].req = NULL; 950 --stores; 951 952 // Inefficient! 953 storeTail = store_idx; 954 955 decrStIdx(store_idx); 956 ++lsqSquashedStores; 957 } 958} 959 960template <class Impl> 961void 962LSQUnit<Impl>::storePostSend(PacketPtr pkt) 963{ 964 if (isStalled() && 965 storeQueue[storeWBIdx].inst->seqNum == stallingStoreIsn) { 966 DPRINTF(LSQUnit, "Unstalling, stalling store [sn:%lli] " 967 "load idx:%i\n", 968 stallingStoreIsn, stallingLoadIdx); 969 stalled = false; 970 stallingStoreIsn = 0; 971 iewStage->replayMemInst(loadQueue[stallingLoadIdx]); 972 } 973 974 if (!storeQueue[storeWBIdx].inst->isStoreConditional()) { 975 // The store is basically completed at this time. This 976 // only works so long as the checker doesn't try to 977 // verify the value in memory for stores. 978 storeQueue[storeWBIdx].inst->setCompleted(); 979#if USE_CHECKER 980 if (cpu->checker) { 981 cpu->checker->verify(storeQueue[storeWBIdx].inst); 982 } 983#endif 984 } 985 986 incrStIdx(storeWBIdx); 987} 988 989template <class Impl> 990void 991LSQUnit<Impl>::writeback(DynInstPtr &inst, PacketPtr pkt) 992{ 993 iewStage->wakeCPU(); 994 995 // Squashed instructions do not need to complete their access. 996 if (inst->isSquashed()) { 997 iewStage->decrWb(inst->seqNum); 998 assert(!inst->isStore()); 999 ++lsqIgnoredResponses; 1000 return; 1001 } 1002 1003 if (!inst->isExecuted()) { 1004 inst->setExecuted(); 1005 1006 // Complete access to copy data to proper place. 1007 inst->completeAcc(pkt); 1008 } 1009 1010 // Need to insert instruction into queue to commit 1011 iewStage->instToCommit(inst); 1012 1013 iewStage->activityThisCycle(); 1014 1015 // see if this load changed the PC 1016 iewStage->checkMisprediction(inst); 1017} 1018 1019template <class Impl> 1020void 1021LSQUnit<Impl>::completeStore(int store_idx) 1022{ 1023 assert(storeQueue[store_idx].inst); 1024 storeQueue[store_idx].completed = true; 1025 --storesToWB; 1026 // A bit conservative because a store completion may not free up entries, 1027 // but hopefully avoids two store completions in one cycle from making 1028 // the CPU tick twice. 1029 cpu->wakeCPU(); 1030 cpu->activityThisCycle(); 1031 1032 if (store_idx == storeHead) { 1033 do { 1034 incrStIdx(storeHead); 1035 1036 --stores; 1037 } while (storeQueue[storeHead].completed && 1038 storeHead != storeTail); 1039 1040 iewStage->updateLSQNextCycle = true; 1041 } 1042 1043 DPRINTF(LSQUnit, "Completing store [sn:%lli], idx:%i, store head " 1044 "idx:%i\n", 1045 storeQueue[store_idx].inst->seqNum, store_idx, storeHead); 1046 1047 if (isStalled() && 1048 storeQueue[store_idx].inst->seqNum == stallingStoreIsn) { 1049 DPRINTF(LSQUnit, "Unstalling, stalling store [sn:%lli] " 1050 "load idx:%i\n", 1051 stallingStoreIsn, stallingLoadIdx); 1052 stalled = false; 1053 stallingStoreIsn = 0; 1054 iewStage->replayMemInst(loadQueue[stallingLoadIdx]); 1055 } 1056 1057 storeQueue[store_idx].inst->setCompleted(); 1058 1059 // Tell the checker we've completed this instruction. Some stores 1060 // may get reported twice to the checker, but the checker can 1061 // handle that case. 1062#if USE_CHECKER 1063 if (cpu->checker) { 1064 cpu->checker->verify(storeQueue[store_idx].inst); 1065 } 1066#endif 1067} 1068 1069template <class Impl> 1070bool 1071LSQUnit<Impl>::sendStore(PacketPtr data_pkt) 1072{ 1073 if (!dcachePort->sendTiming(data_pkt)) { 1074 // Need to handle becoming blocked on a store. 1075 isStoreBlocked = true; 1076 ++lsqCacheBlocked; 1077 assert(retryPkt == NULL); 1078 retryPkt = data_pkt; 1079 lsq->setRetryTid(lsqID); 1080 return false; 1081 } 1082 return true; 1083} 1084 1085template <class Impl> 1086void 1087LSQUnit<Impl>::recvRetry() 1088{ 1089 if (isStoreBlocked) { 1090 DPRINTF(LSQUnit, "Receiving retry: store blocked\n"); 1091 assert(retryPkt != NULL); 1092 1093 if (dcachePort->sendTiming(retryPkt)) { 1094 LSQSenderState *state = 1095 dynamic_cast<LSQSenderState *>(retryPkt->senderState); 1096 1097 // Don't finish the store unless this is the last packet. 1098 if (!TheISA::HasUnalignedMemAcc || !state->pktToSend) { 1099 storePostSend(retryPkt); 1100 } 1101 retryPkt = NULL; 1102 isStoreBlocked = false; 1103 lsq->setRetryTid(InvalidThreadID); 1104 1105 // Send any outstanding packet. 1106 if (TheISA::HasUnalignedMemAcc && state->pktToSend) { 1107 assert(state->pendingPacket); 1108 if (sendStore(state->pendingPacket)) { 1109 storePostSend(state->pendingPacket); 1110 } 1111 } 1112 } else { 1113 // Still blocked! 1114 ++lsqCacheBlocked; 1115 lsq->setRetryTid(lsqID); 1116 } 1117 } else if (isLoadBlocked) { 1118 DPRINTF(LSQUnit, "Loads squash themselves and all younger insts, " 1119 "no need to resend packet.\n"); 1120 } else { 1121 DPRINTF(LSQUnit, "Retry received but LSQ is no longer blocked.\n"); 1122 } 1123} 1124 1125template <class Impl> 1126inline void 1127LSQUnit<Impl>::incrStIdx(int &store_idx) 1128{ 1129 if (++store_idx >= SQEntries) 1130 store_idx = 0; 1131} 1132 1133template <class Impl> 1134inline void 1135LSQUnit<Impl>::decrStIdx(int &store_idx) 1136{ 1137 if (--store_idx < 0) 1138 store_idx += SQEntries; 1139} 1140 1141template <class Impl> 1142inline void 1143LSQUnit<Impl>::incrLdIdx(int &load_idx) 1144{ 1145 if (++load_idx >= LQEntries) 1146 load_idx = 0; 1147} 1148 1149template <class Impl> 1150inline void 1151LSQUnit<Impl>::decrLdIdx(int &load_idx) 1152{ 1153 if (--load_idx < 0) 1154 load_idx += LQEntries; 1155} 1156 1157template <class Impl> 1158void 1159LSQUnit<Impl>::dumpInsts() 1160{ 1161 cprintf("Load store queue: Dumping instructions.\n"); 1162 cprintf("Load queue size: %i\n", loads); 1163 cprintf("Load queue: "); 1164 1165 int load_idx = loadHead; 1166 1167 while (load_idx != loadTail && loadQueue[load_idx]) { 1168 cprintf("%s ", loadQueue[load_idx]->pcState()); 1169 1170 incrLdIdx(load_idx); 1171 } 1172 1173 cprintf("Store queue size: %i\n", stores); 1174 cprintf("Store queue: "); 1175 1176 int store_idx = storeHead; 1177 1178 while (store_idx != storeTail && storeQueue[store_idx].inst) { 1179 cprintf("%s ", storeQueue[store_idx].inst->pcState()); 1180 1181 incrStIdx(store_idx); 1182 } 1183 1184 cprintf("\n"); 1185}
|