1/*
2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Kevin Lim
29 * Korey Sewell
30 */
31
32#include "arch/locked_mem.hh"
33#include "config/use_checker.hh"
34
35#include "cpu/o3/lsq.hh"
36#include "cpu/o3/lsq_unit.hh"
37#include "base/str.hh"
38#include "mem/packet.hh"
39#include "mem/request.hh"
40
41#if USE_CHECKER
42#include "cpu/checker/cpu.hh"
43#endif
44
45template<class Impl>
46LSQUnit<Impl>::WritebackEvent::WritebackEvent(DynInstPtr &_inst, PacketPtr _pkt,
47 LSQUnit *lsq_ptr)
48 : Event(&mainEventQueue), inst(_inst), pkt(_pkt), lsqPtr(lsq_ptr)
49{
50 this->setFlags(Event::AutoDelete);
51}
52
53template<class Impl>
54void
55LSQUnit<Impl>::WritebackEvent::process()
56{
57 if (!lsqPtr->isSwitchedOut()) {
58 lsqPtr->writeback(inst, pkt);
59 }
60
61 if (pkt->senderState)
62 delete pkt->senderState;
63
64 delete pkt->req;
65 delete pkt;
66}
67
68template<class Impl>
69const char *
70LSQUnit<Impl>::WritebackEvent::description()
71{
72 return "Store writeback event";
73}
74
75template<class Impl>
76void
77LSQUnit<Impl>::completeDataAccess(PacketPtr pkt)
78{
79 LSQSenderState *state = dynamic_cast<LSQSenderState *>(pkt->senderState);
80 DynInstPtr inst = state->inst;
81 DPRINTF(IEW, "Writeback event [sn:%lli]\n", inst->seqNum);
82 DPRINTF(Activity, "Activity: Writeback event [sn:%lli]\n", inst->seqNum);
83
84 //iewStage->ldstQueue.removeMSHR(inst->threadNumber,inst->seqNum);
85
86 if (isSwitchedOut() || inst->isSquashed()) {
87 iewStage->decrWb(inst->seqNum);
88 } else {
89 if (!state->noWB) {
90 writeback(inst, pkt);
91 }
92
93 if (inst->isStore()) {
94 completeStore(state->idx);
95 }
96 }
97
98 delete state;
99 delete pkt->req;
100 delete pkt;
101}
102
103template <class Impl>
104LSQUnit<Impl>::LSQUnit()
105 : loads(0), stores(0), storesToWB(0), stalled(false),
106 isStoreBlocked(false), isLoadBlocked(false),
107 loadBlockedHandled(false)
108{
109}
110
111template<class Impl>
112void
113LSQUnit<Impl>::init(O3CPU *cpu_ptr, IEW *iew_ptr, Params *params, LSQ *lsq_ptr,
114 unsigned maxLQEntries, unsigned maxSQEntries, unsigned id)
115{
116 cpu = cpu_ptr;
117 iewStage = iew_ptr;
118
119 DPRINTF(LSQUnit, "Creating LSQUnit%i object.\n",id);
120
121 switchedOut = false;
122
123 lsq = lsq_ptr;
124
125 lsqID = id;
126
127 // Add 1 for the sentinel entry (they are circular queues).
128 LQEntries = maxLQEntries + 1;
129 SQEntries = maxSQEntries + 1;
130
131 loadQueue.resize(LQEntries);
132 storeQueue.resize(SQEntries);
133
134 loadHead = loadTail = 0;
135
136 storeHead = storeWBIdx = storeTail = 0;
137
138 usedPorts = 0;
139 cachePorts = params->cachePorts;
140
141 retryPkt = NULL;
142 memDepViolator = NULL;
143
144 blockedLoadSeqNum = 0;
145}
146
147template<class Impl>
148std::string
149LSQUnit<Impl>::name() const
150{
151 if (Impl::MaxThreads == 1) {
152 return iewStage->name() + ".lsq";
153 } else {
154 return iewStage->name() + ".lsq.thread." + to_string(lsqID);
155 }
156}
157
158template<class Impl>
159void
160LSQUnit<Impl>::regStats()
161{
162 lsqForwLoads
163 .name(name() + ".forwLoads")
164 .desc("Number of loads that had data forwarded from stores");
165
166 invAddrLoads
167 .name(name() + ".invAddrLoads")
168 .desc("Number of loads ignored due to an invalid address");
169
170 lsqSquashedLoads
171 .name(name() + ".squashedLoads")
172 .desc("Number of loads squashed");
173
174 lsqIgnoredResponses
175 .name(name() + ".ignoredResponses")
176 .desc("Number of memory responses ignored because the instruction is squashed");
177
178 lsqMemOrderViolation
179 .name(name() + ".memOrderViolation")
180 .desc("Number of memory ordering violations");
181
182 lsqSquashedStores
183 .name(name() + ".squashedStores")
184 .desc("Number of stores squashed");
185
186 invAddrSwpfs
187 .name(name() + ".invAddrSwpfs")
188 .desc("Number of software prefetches ignored due to an invalid address");
189
190 lsqBlockedLoads
191 .name(name() + ".blockedLoads")
192 .desc("Number of blocked loads due to partial load-store forwarding");
193
194 lsqRescheduledLoads
195 .name(name() + ".rescheduledLoads")
196 .desc("Number of loads that were rescheduled");
197
198 lsqCacheBlocked
199 .name(name() + ".cacheBlocked")
200 .desc("Number of times an access to memory failed due to the cache being blocked");
201}
202
203template<class Impl>
204void
205LSQUnit<Impl>::setDcachePort(Port *dcache_port)
206{
207 dcachePort = dcache_port;
208
209#if USE_CHECKER
210 if (cpu->checker) {
211 cpu->checker->setDcachePort(dcachePort);
212 }
213#endif
214}
215
216template<class Impl>
217void
218LSQUnit<Impl>::clearLQ()
219{
220 loadQueue.clear();
221}
222
223template<class Impl>
224void
225LSQUnit<Impl>::clearSQ()
226{
227 storeQueue.clear();
228}
229
230template<class Impl>
231void
232LSQUnit<Impl>::switchOut()
233{
234 switchedOut = true;
235 for (int i = 0; i < loadQueue.size(); ++i) {
236 assert(!loadQueue[i]);
237 loadQueue[i] = NULL;
238 }
239
240 assert(storesToWB == 0);
241}
242
243template<class Impl>
244void
245LSQUnit<Impl>::takeOverFrom()
246{
247 switchedOut = false;
248 loads = stores = storesToWB = 0;
249
250 loadHead = loadTail = 0;
251
252 storeHead = storeWBIdx = storeTail = 0;
253
254 usedPorts = 0;
255
256 memDepViolator = NULL;
257
258 blockedLoadSeqNum = 0;
259
260 stalled = false;
261 isLoadBlocked = false;
262 loadBlockedHandled = false;
263}
264
265template<class Impl>
266void
267LSQUnit<Impl>::resizeLQ(unsigned size)
268{
269 unsigned size_plus_sentinel = size + 1;
270 assert(size_plus_sentinel >= LQEntries);
271
272 if (size_plus_sentinel > LQEntries) {
273 while (size_plus_sentinel > loadQueue.size()) {
274 DynInstPtr dummy;
275 loadQueue.push_back(dummy);
276 LQEntries++;
277 }
278 } else {
279 LQEntries = size_plus_sentinel;
280 }
281
282}
283
284template<class Impl>
285void
286LSQUnit<Impl>::resizeSQ(unsigned size)
287{
288 unsigned size_plus_sentinel = size + 1;
289 if (size_plus_sentinel > SQEntries) {
290 while (size_plus_sentinel > storeQueue.size()) {
291 SQEntry dummy;
292 storeQueue.push_back(dummy);
293 SQEntries++;
294 }
295 } else {
296 SQEntries = size_plus_sentinel;
297 }
298}
299
300template <class Impl>
301void
302LSQUnit<Impl>::insert(DynInstPtr &inst)
303{
304 assert(inst->isMemRef());
305
306 assert(inst->isLoad() || inst->isStore());
307
308 if (inst->isLoad()) {
309 insertLoad(inst);
310 } else {
311 insertStore(inst);
312 }
313
314 inst->setInLSQ();
315}
316
317template <class Impl>
318void
319LSQUnit<Impl>::insertLoad(DynInstPtr &load_inst)
320{
321 assert((loadTail + 1) % LQEntries != loadHead);
322 assert(loads < LQEntries);
323
324 DPRINTF(LSQUnit, "Inserting load PC %#x, idx:%i [sn:%lli]\n",
325 load_inst->readPC(), loadTail, load_inst->seqNum);
326
327 load_inst->lqIdx = loadTail;
328
329 if (stores == 0) {
330 load_inst->sqIdx = -1;
331 } else {
332 load_inst->sqIdx = storeTail;
333 }
334
335 loadQueue[loadTail] = load_inst;
336
337 incrLdIdx(loadTail);
338
339 ++loads;
340}
341
342template <class Impl>
343void
344LSQUnit<Impl>::insertStore(DynInstPtr &store_inst)
345{
346 // Make sure it is not full before inserting an instruction.
347 assert((storeTail + 1) % SQEntries != storeHead);
348 assert(stores < SQEntries);
349
350 DPRINTF(LSQUnit, "Inserting store PC %#x, idx:%i [sn:%lli]\n",
351 store_inst->readPC(), storeTail, store_inst->seqNum);
352
353 store_inst->sqIdx = storeTail;
354 store_inst->lqIdx = loadTail;
355
356 storeQueue[storeTail] = SQEntry(store_inst);
357
358 incrStIdx(storeTail);
359
360 ++stores;
361}
362
363template <class Impl>
364typename Impl::DynInstPtr
365LSQUnit<Impl>::getMemDepViolator()
366{
367 DynInstPtr temp = memDepViolator;
368
369 memDepViolator = NULL;
370
371 return temp;
372}
373
374template <class Impl>
375unsigned
376LSQUnit<Impl>::numFreeEntries()
377{
378 unsigned free_lq_entries = LQEntries - loads;
379 unsigned free_sq_entries = SQEntries - stores;
380
381 // Both the LQ and SQ entries have an extra dummy entry to differentiate
382 // empty/full conditions. Subtract 1 from the free entries.
383 if (free_lq_entries < free_sq_entries) {
384 return free_lq_entries - 1;
385 } else {
386 return free_sq_entries - 1;
387 }
388}
389
390template <class Impl>
391int
392LSQUnit<Impl>::numLoadsReady()
393{
394 int load_idx = loadHead;
395 int retval = 0;
396
397 while (load_idx != loadTail) {
398 assert(loadQueue[load_idx]);
399
400 if (loadQueue[load_idx]->readyToIssue()) {
401 ++retval;
402 }
403 }
404
405 return retval;
406}
407
408template <class Impl>
409Fault
410LSQUnit<Impl>::executeLoad(DynInstPtr &inst)
411{
412 using namespace TheISA;
413 // Execute a specific load.
414 Fault load_fault = NoFault;
415
416 DPRINTF(LSQUnit, "Executing load PC %#x, [sn:%lli]\n",
417 inst->readPC(),inst->seqNum);
418
419 assert(!inst->isSquashed());
420
421 load_fault = inst->initiateAcc();
422
423 // If the instruction faulted, then we need to send it along to commit
424 // without the instruction completing.
425 if (load_fault != NoFault) {
426 // Send this instruction to commit, also make sure iew stage
427 // realizes there is activity.
428 // Mark it as executed unless it is an uncached load that
429 // needs to hit the head of commit.
430 if (!(inst->hasRequest() && inst->uncacheable()) ||
431 inst->isAtCommit()) {
432 inst->setExecuted();
433 }
434 iewStage->instToCommit(inst);
435 iewStage->activityThisCycle();
436 } else if (!loadBlocked()) {
437 assert(inst->effAddrValid);
438 int load_idx = inst->lqIdx;
439 incrLdIdx(load_idx);
440 while (load_idx != loadTail) {
441 // Really only need to check loads that have actually executed
442
443 // @todo: For now this is extra conservative, detecting a
444 // violation if the addresses match assuming all accesses
445 // are quad word accesses.
446
447 // @todo: Fix this, magic number being used here
448 if (loadQueue[load_idx]->effAddrValid &&
449 (loadQueue[load_idx]->effAddr >> 8) ==
450 (inst->effAddr >> 8)) {
451 // A load incorrectly passed this load. Squash and refetch.
452 // For now return a fault to show that it was unsuccessful.
453 DynInstPtr violator = loadQueue[load_idx];
454 if (!memDepViolator ||
455 (violator->seqNum < memDepViolator->seqNum)) {
456 memDepViolator = violator;
457 } else {
458 break;
459 }
460
461 ++lsqMemOrderViolation;
462
463 return genMachineCheckFault();
464 }
465
466 incrLdIdx(load_idx);
467 }
468 }
469
470 return load_fault;
471}
472
473template <class Impl>
474Fault
475LSQUnit<Impl>::executeStore(DynInstPtr &store_inst)
476{
477 using namespace TheISA;
478 // Make sure that a store exists.
479 assert(stores != 0);
480
481 int store_idx = store_inst->sqIdx;
482
483 DPRINTF(LSQUnit, "Executing store PC %#x [sn:%lli]\n",
484 store_inst->readPC(), store_inst->seqNum);
485
486 assert(!store_inst->isSquashed());
487
488 // Check the recently completed loads to see if any match this store's
489 // address. If so, then we have a memory ordering violation.
490 int load_idx = store_inst->lqIdx;
491
492 Fault store_fault = store_inst->initiateAcc();
493
494 if (storeQueue[store_idx].size == 0) {
495 DPRINTF(LSQUnit,"Fault on Store PC %#x, [sn:%lli],Size = 0\n",
496 store_inst->readPC(),store_inst->seqNum);
497
498 return store_fault;
499 }
500
501 assert(store_fault == NoFault);
502
503 if (store_inst->isStoreConditional()) {
504 // Store conditionals need to set themselves as able to
505 // writeback if we haven't had a fault by here.
506 storeQueue[store_idx].canWB = true;
507
508 ++storesToWB;
509 }
510
511 assert(store_inst->effAddrValid);
512 while (load_idx != loadTail) {
513 // Really only need to check loads that have actually executed
514 // It's safe to check all loads because effAddr is set to
515 // InvalAddr when the dyn inst is created.
516
517 // @todo: For now this is extra conservative, detecting a
518 // violation if the addresses match assuming all accesses
519 // are quad word accesses.
520
521 // @todo: Fix this, magic number being used here
522 if (loadQueue[load_idx]->effAddrValid &&
523 (loadQueue[load_idx]->effAddr >> 8) ==
524 (store_inst->effAddr >> 8)) {
525 // A load incorrectly passed this store. Squash and refetch.
526 // For now return a fault to show that it was unsuccessful.
527 DynInstPtr violator = loadQueue[load_idx];
528 if (!memDepViolator ||
529 (violator->seqNum < memDepViolator->seqNum)) {
530 memDepViolator = violator;
531 } else {
532 break;
533 }
534
535 ++lsqMemOrderViolation;
536
537 return genMachineCheckFault();
538 }
539
540 incrLdIdx(load_idx);
541 }
542
543 return store_fault;
544}
545
546template <class Impl>
547void
548LSQUnit<Impl>::commitLoad()
549{
550 assert(loadQueue[loadHead]);
551
552 DPRINTF(LSQUnit, "Committing head load instruction, PC %#x\n",
553 loadQueue[loadHead]->readPC());
554
555 loadQueue[loadHead] = NULL;
556
557 incrLdIdx(loadHead);
558
559 --loads;
560}
561
562template <class Impl>
563void
564LSQUnit<Impl>::commitLoads(InstSeqNum &youngest_inst)
565{
566 assert(loads == 0 || loadQueue[loadHead]);
567
568 while (loads != 0 && loadQueue[loadHead]->seqNum <= youngest_inst) {
569 commitLoad();
570 }
571}
572
573template <class Impl>
574void
575LSQUnit<Impl>::commitStores(InstSeqNum &youngest_inst)
576{
577 assert(stores == 0 || storeQueue[storeHead].inst);
578
579 int store_idx = storeHead;
580
581 while (store_idx != storeTail) {
582 assert(storeQueue[store_idx].inst);
583 // Mark any stores that are now committed and have not yet
584 // been marked as able to write back.
585 if (!storeQueue[store_idx].canWB) {
586 if (storeQueue[store_idx].inst->seqNum > youngest_inst) {
587 break;
588 }
589 DPRINTF(LSQUnit, "Marking store as able to write back, PC "
590 "%#x [sn:%lli]\n",
591 storeQueue[store_idx].inst->readPC(),
592 storeQueue[store_idx].inst->seqNum);
593
594 storeQueue[store_idx].canWB = true;
595
596 ++storesToWB;
597 }
598
599 incrStIdx(store_idx);
600 }
601}
602
603template <class Impl>
604void
605LSQUnit<Impl>::writebackStores()
606{
607 while (storesToWB > 0 &&
608 storeWBIdx != storeTail &&
609 storeQueue[storeWBIdx].inst &&
610 storeQueue[storeWBIdx].canWB &&
611 usedPorts < cachePorts) {
612
613 if (isStoreBlocked || lsq->cacheBlocked()) {
614 DPRINTF(LSQUnit, "Unable to write back any more stores, cache"
615 " is blocked!\n");
616 break;
617 }
618
619 // Store didn't write any data so no need to write it back to
620 // memory.
621 if (storeQueue[storeWBIdx].size == 0) {
622 completeStore(storeWBIdx);
623
624 incrStIdx(storeWBIdx);
625
626 continue;
627 }
628
629 ++usedPorts;
630
631 if (storeQueue[storeWBIdx].inst->isDataPrefetch()) {
632 incrStIdx(storeWBIdx);
633
634 continue;
635 }
636
637 assert(storeQueue[storeWBIdx].req);
638 assert(!storeQueue[storeWBIdx].committed);
639
640 DynInstPtr inst = storeQueue[storeWBIdx].inst;
641
642 Request *req = storeQueue[storeWBIdx].req;
643 storeQueue[storeWBIdx].committed = true;
644
645 assert(!inst->memData);
646 inst->memData = new uint8_t[64];
647
| 1/*
2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Kevin Lim
29 * Korey Sewell
30 */
31
32#include "arch/locked_mem.hh"
33#include "config/use_checker.hh"
34
35#include "cpu/o3/lsq.hh"
36#include "cpu/o3/lsq_unit.hh"
37#include "base/str.hh"
38#include "mem/packet.hh"
39#include "mem/request.hh"
40
41#if USE_CHECKER
42#include "cpu/checker/cpu.hh"
43#endif
44
45template<class Impl>
46LSQUnit<Impl>::WritebackEvent::WritebackEvent(DynInstPtr &_inst, PacketPtr _pkt,
47 LSQUnit *lsq_ptr)
48 : Event(&mainEventQueue), inst(_inst), pkt(_pkt), lsqPtr(lsq_ptr)
49{
50 this->setFlags(Event::AutoDelete);
51}
52
53template<class Impl>
54void
55LSQUnit<Impl>::WritebackEvent::process()
56{
57 if (!lsqPtr->isSwitchedOut()) {
58 lsqPtr->writeback(inst, pkt);
59 }
60
61 if (pkt->senderState)
62 delete pkt->senderState;
63
64 delete pkt->req;
65 delete pkt;
66}
67
68template<class Impl>
69const char *
70LSQUnit<Impl>::WritebackEvent::description()
71{
72 return "Store writeback event";
73}
74
75template<class Impl>
76void
77LSQUnit<Impl>::completeDataAccess(PacketPtr pkt)
78{
79 LSQSenderState *state = dynamic_cast<LSQSenderState *>(pkt->senderState);
80 DynInstPtr inst = state->inst;
81 DPRINTF(IEW, "Writeback event [sn:%lli]\n", inst->seqNum);
82 DPRINTF(Activity, "Activity: Writeback event [sn:%lli]\n", inst->seqNum);
83
84 //iewStage->ldstQueue.removeMSHR(inst->threadNumber,inst->seqNum);
85
86 if (isSwitchedOut() || inst->isSquashed()) {
87 iewStage->decrWb(inst->seqNum);
88 } else {
89 if (!state->noWB) {
90 writeback(inst, pkt);
91 }
92
93 if (inst->isStore()) {
94 completeStore(state->idx);
95 }
96 }
97
98 delete state;
99 delete pkt->req;
100 delete pkt;
101}
102
103template <class Impl>
104LSQUnit<Impl>::LSQUnit()
105 : loads(0), stores(0), storesToWB(0), stalled(false),
106 isStoreBlocked(false), isLoadBlocked(false),
107 loadBlockedHandled(false)
108{
109}
110
111template<class Impl>
112void
113LSQUnit<Impl>::init(O3CPU *cpu_ptr, IEW *iew_ptr, Params *params, LSQ *lsq_ptr,
114 unsigned maxLQEntries, unsigned maxSQEntries, unsigned id)
115{
116 cpu = cpu_ptr;
117 iewStage = iew_ptr;
118
119 DPRINTF(LSQUnit, "Creating LSQUnit%i object.\n",id);
120
121 switchedOut = false;
122
123 lsq = lsq_ptr;
124
125 lsqID = id;
126
127 // Add 1 for the sentinel entry (they are circular queues).
128 LQEntries = maxLQEntries + 1;
129 SQEntries = maxSQEntries + 1;
130
131 loadQueue.resize(LQEntries);
132 storeQueue.resize(SQEntries);
133
134 loadHead = loadTail = 0;
135
136 storeHead = storeWBIdx = storeTail = 0;
137
138 usedPorts = 0;
139 cachePorts = params->cachePorts;
140
141 retryPkt = NULL;
142 memDepViolator = NULL;
143
144 blockedLoadSeqNum = 0;
145}
146
147template<class Impl>
148std::string
149LSQUnit<Impl>::name() const
150{
151 if (Impl::MaxThreads == 1) {
152 return iewStage->name() + ".lsq";
153 } else {
154 return iewStage->name() + ".lsq.thread." + to_string(lsqID);
155 }
156}
157
158template<class Impl>
159void
160LSQUnit<Impl>::regStats()
161{
162 lsqForwLoads
163 .name(name() + ".forwLoads")
164 .desc("Number of loads that had data forwarded from stores");
165
166 invAddrLoads
167 .name(name() + ".invAddrLoads")
168 .desc("Number of loads ignored due to an invalid address");
169
170 lsqSquashedLoads
171 .name(name() + ".squashedLoads")
172 .desc("Number of loads squashed");
173
174 lsqIgnoredResponses
175 .name(name() + ".ignoredResponses")
176 .desc("Number of memory responses ignored because the instruction is squashed");
177
178 lsqMemOrderViolation
179 .name(name() + ".memOrderViolation")
180 .desc("Number of memory ordering violations");
181
182 lsqSquashedStores
183 .name(name() + ".squashedStores")
184 .desc("Number of stores squashed");
185
186 invAddrSwpfs
187 .name(name() + ".invAddrSwpfs")
188 .desc("Number of software prefetches ignored due to an invalid address");
189
190 lsqBlockedLoads
191 .name(name() + ".blockedLoads")
192 .desc("Number of blocked loads due to partial load-store forwarding");
193
194 lsqRescheduledLoads
195 .name(name() + ".rescheduledLoads")
196 .desc("Number of loads that were rescheduled");
197
198 lsqCacheBlocked
199 .name(name() + ".cacheBlocked")
200 .desc("Number of times an access to memory failed due to the cache being blocked");
201}
202
203template<class Impl>
204void
205LSQUnit<Impl>::setDcachePort(Port *dcache_port)
206{
207 dcachePort = dcache_port;
208
209#if USE_CHECKER
210 if (cpu->checker) {
211 cpu->checker->setDcachePort(dcachePort);
212 }
213#endif
214}
215
216template<class Impl>
217void
218LSQUnit<Impl>::clearLQ()
219{
220 loadQueue.clear();
221}
222
223template<class Impl>
224void
225LSQUnit<Impl>::clearSQ()
226{
227 storeQueue.clear();
228}
229
230template<class Impl>
231void
232LSQUnit<Impl>::switchOut()
233{
234 switchedOut = true;
235 for (int i = 0; i < loadQueue.size(); ++i) {
236 assert(!loadQueue[i]);
237 loadQueue[i] = NULL;
238 }
239
240 assert(storesToWB == 0);
241}
242
243template<class Impl>
244void
245LSQUnit<Impl>::takeOverFrom()
246{
247 switchedOut = false;
248 loads = stores = storesToWB = 0;
249
250 loadHead = loadTail = 0;
251
252 storeHead = storeWBIdx = storeTail = 0;
253
254 usedPorts = 0;
255
256 memDepViolator = NULL;
257
258 blockedLoadSeqNum = 0;
259
260 stalled = false;
261 isLoadBlocked = false;
262 loadBlockedHandled = false;
263}
264
265template<class Impl>
266void
267LSQUnit<Impl>::resizeLQ(unsigned size)
268{
269 unsigned size_plus_sentinel = size + 1;
270 assert(size_plus_sentinel >= LQEntries);
271
272 if (size_plus_sentinel > LQEntries) {
273 while (size_plus_sentinel > loadQueue.size()) {
274 DynInstPtr dummy;
275 loadQueue.push_back(dummy);
276 LQEntries++;
277 }
278 } else {
279 LQEntries = size_plus_sentinel;
280 }
281
282}
283
284template<class Impl>
285void
286LSQUnit<Impl>::resizeSQ(unsigned size)
287{
288 unsigned size_plus_sentinel = size + 1;
289 if (size_plus_sentinel > SQEntries) {
290 while (size_plus_sentinel > storeQueue.size()) {
291 SQEntry dummy;
292 storeQueue.push_back(dummy);
293 SQEntries++;
294 }
295 } else {
296 SQEntries = size_plus_sentinel;
297 }
298}
299
300template <class Impl>
301void
302LSQUnit<Impl>::insert(DynInstPtr &inst)
303{
304 assert(inst->isMemRef());
305
306 assert(inst->isLoad() || inst->isStore());
307
308 if (inst->isLoad()) {
309 insertLoad(inst);
310 } else {
311 insertStore(inst);
312 }
313
314 inst->setInLSQ();
315}
316
317template <class Impl>
318void
319LSQUnit<Impl>::insertLoad(DynInstPtr &load_inst)
320{
321 assert((loadTail + 1) % LQEntries != loadHead);
322 assert(loads < LQEntries);
323
324 DPRINTF(LSQUnit, "Inserting load PC %#x, idx:%i [sn:%lli]\n",
325 load_inst->readPC(), loadTail, load_inst->seqNum);
326
327 load_inst->lqIdx = loadTail;
328
329 if (stores == 0) {
330 load_inst->sqIdx = -1;
331 } else {
332 load_inst->sqIdx = storeTail;
333 }
334
335 loadQueue[loadTail] = load_inst;
336
337 incrLdIdx(loadTail);
338
339 ++loads;
340}
341
342template <class Impl>
343void
344LSQUnit<Impl>::insertStore(DynInstPtr &store_inst)
345{
346 // Make sure it is not full before inserting an instruction.
347 assert((storeTail + 1) % SQEntries != storeHead);
348 assert(stores < SQEntries);
349
350 DPRINTF(LSQUnit, "Inserting store PC %#x, idx:%i [sn:%lli]\n",
351 store_inst->readPC(), storeTail, store_inst->seqNum);
352
353 store_inst->sqIdx = storeTail;
354 store_inst->lqIdx = loadTail;
355
356 storeQueue[storeTail] = SQEntry(store_inst);
357
358 incrStIdx(storeTail);
359
360 ++stores;
361}
362
363template <class Impl>
364typename Impl::DynInstPtr
365LSQUnit<Impl>::getMemDepViolator()
366{
367 DynInstPtr temp = memDepViolator;
368
369 memDepViolator = NULL;
370
371 return temp;
372}
373
374template <class Impl>
375unsigned
376LSQUnit<Impl>::numFreeEntries()
377{
378 unsigned free_lq_entries = LQEntries - loads;
379 unsigned free_sq_entries = SQEntries - stores;
380
381 // Both the LQ and SQ entries have an extra dummy entry to differentiate
382 // empty/full conditions. Subtract 1 from the free entries.
383 if (free_lq_entries < free_sq_entries) {
384 return free_lq_entries - 1;
385 } else {
386 return free_sq_entries - 1;
387 }
388}
389
390template <class Impl>
391int
392LSQUnit<Impl>::numLoadsReady()
393{
394 int load_idx = loadHead;
395 int retval = 0;
396
397 while (load_idx != loadTail) {
398 assert(loadQueue[load_idx]);
399
400 if (loadQueue[load_idx]->readyToIssue()) {
401 ++retval;
402 }
403 }
404
405 return retval;
406}
407
408template <class Impl>
409Fault
410LSQUnit<Impl>::executeLoad(DynInstPtr &inst)
411{
412 using namespace TheISA;
413 // Execute a specific load.
414 Fault load_fault = NoFault;
415
416 DPRINTF(LSQUnit, "Executing load PC %#x, [sn:%lli]\n",
417 inst->readPC(),inst->seqNum);
418
419 assert(!inst->isSquashed());
420
421 load_fault = inst->initiateAcc();
422
423 // If the instruction faulted, then we need to send it along to commit
424 // without the instruction completing.
425 if (load_fault != NoFault) {
426 // Send this instruction to commit, also make sure iew stage
427 // realizes there is activity.
428 // Mark it as executed unless it is an uncached load that
429 // needs to hit the head of commit.
430 if (!(inst->hasRequest() && inst->uncacheable()) ||
431 inst->isAtCommit()) {
432 inst->setExecuted();
433 }
434 iewStage->instToCommit(inst);
435 iewStage->activityThisCycle();
436 } else if (!loadBlocked()) {
437 assert(inst->effAddrValid);
438 int load_idx = inst->lqIdx;
439 incrLdIdx(load_idx);
440 while (load_idx != loadTail) {
441 // Really only need to check loads that have actually executed
442
443 // @todo: For now this is extra conservative, detecting a
444 // violation if the addresses match assuming all accesses
445 // are quad word accesses.
446
447 // @todo: Fix this, magic number being used here
448 if (loadQueue[load_idx]->effAddrValid &&
449 (loadQueue[load_idx]->effAddr >> 8) ==
450 (inst->effAddr >> 8)) {
451 // A load incorrectly passed this load. Squash and refetch.
452 // For now return a fault to show that it was unsuccessful.
453 DynInstPtr violator = loadQueue[load_idx];
454 if (!memDepViolator ||
455 (violator->seqNum < memDepViolator->seqNum)) {
456 memDepViolator = violator;
457 } else {
458 break;
459 }
460
461 ++lsqMemOrderViolation;
462
463 return genMachineCheckFault();
464 }
465
466 incrLdIdx(load_idx);
467 }
468 }
469
470 return load_fault;
471}
472
473template <class Impl>
474Fault
475LSQUnit<Impl>::executeStore(DynInstPtr &store_inst)
476{
477 using namespace TheISA;
478 // Make sure that a store exists.
479 assert(stores != 0);
480
481 int store_idx = store_inst->sqIdx;
482
483 DPRINTF(LSQUnit, "Executing store PC %#x [sn:%lli]\n",
484 store_inst->readPC(), store_inst->seqNum);
485
486 assert(!store_inst->isSquashed());
487
488 // Check the recently completed loads to see if any match this store's
489 // address. If so, then we have a memory ordering violation.
490 int load_idx = store_inst->lqIdx;
491
492 Fault store_fault = store_inst->initiateAcc();
493
494 if (storeQueue[store_idx].size == 0) {
495 DPRINTF(LSQUnit,"Fault on Store PC %#x, [sn:%lli],Size = 0\n",
496 store_inst->readPC(),store_inst->seqNum);
497
498 return store_fault;
499 }
500
501 assert(store_fault == NoFault);
502
503 if (store_inst->isStoreConditional()) {
504 // Store conditionals need to set themselves as able to
505 // writeback if we haven't had a fault by here.
506 storeQueue[store_idx].canWB = true;
507
508 ++storesToWB;
509 }
510
511 assert(store_inst->effAddrValid);
512 while (load_idx != loadTail) {
513 // Really only need to check loads that have actually executed
514 // It's safe to check all loads because effAddr is set to
515 // InvalAddr when the dyn inst is created.
516
517 // @todo: For now this is extra conservative, detecting a
518 // violation if the addresses match assuming all accesses
519 // are quad word accesses.
520
521 // @todo: Fix this, magic number being used here
522 if (loadQueue[load_idx]->effAddrValid &&
523 (loadQueue[load_idx]->effAddr >> 8) ==
524 (store_inst->effAddr >> 8)) {
525 // A load incorrectly passed this store. Squash and refetch.
526 // For now return a fault to show that it was unsuccessful.
527 DynInstPtr violator = loadQueue[load_idx];
528 if (!memDepViolator ||
529 (violator->seqNum < memDepViolator->seqNum)) {
530 memDepViolator = violator;
531 } else {
532 break;
533 }
534
535 ++lsqMemOrderViolation;
536
537 return genMachineCheckFault();
538 }
539
540 incrLdIdx(load_idx);
541 }
542
543 return store_fault;
544}
545
546template <class Impl>
547void
548LSQUnit<Impl>::commitLoad()
549{
550 assert(loadQueue[loadHead]);
551
552 DPRINTF(LSQUnit, "Committing head load instruction, PC %#x\n",
553 loadQueue[loadHead]->readPC());
554
555 loadQueue[loadHead] = NULL;
556
557 incrLdIdx(loadHead);
558
559 --loads;
560}
561
562template <class Impl>
563void
564LSQUnit<Impl>::commitLoads(InstSeqNum &youngest_inst)
565{
566 assert(loads == 0 || loadQueue[loadHead]);
567
568 while (loads != 0 && loadQueue[loadHead]->seqNum <= youngest_inst) {
569 commitLoad();
570 }
571}
572
573template <class Impl>
574void
575LSQUnit<Impl>::commitStores(InstSeqNum &youngest_inst)
576{
577 assert(stores == 0 || storeQueue[storeHead].inst);
578
579 int store_idx = storeHead;
580
581 while (store_idx != storeTail) {
582 assert(storeQueue[store_idx].inst);
583 // Mark any stores that are now committed and have not yet
584 // been marked as able to write back.
585 if (!storeQueue[store_idx].canWB) {
586 if (storeQueue[store_idx].inst->seqNum > youngest_inst) {
587 break;
588 }
589 DPRINTF(LSQUnit, "Marking store as able to write back, PC "
590 "%#x [sn:%lli]\n",
591 storeQueue[store_idx].inst->readPC(),
592 storeQueue[store_idx].inst->seqNum);
593
594 storeQueue[store_idx].canWB = true;
595
596 ++storesToWB;
597 }
598
599 incrStIdx(store_idx);
600 }
601}
602
603template <class Impl>
604void
605LSQUnit<Impl>::writebackStores()
606{
607 while (storesToWB > 0 &&
608 storeWBIdx != storeTail &&
609 storeQueue[storeWBIdx].inst &&
610 storeQueue[storeWBIdx].canWB &&
611 usedPorts < cachePorts) {
612
613 if (isStoreBlocked || lsq->cacheBlocked()) {
614 DPRINTF(LSQUnit, "Unable to write back any more stores, cache"
615 " is blocked!\n");
616 break;
617 }
618
619 // Store didn't write any data so no need to write it back to
620 // memory.
621 if (storeQueue[storeWBIdx].size == 0) {
622 completeStore(storeWBIdx);
623
624 incrStIdx(storeWBIdx);
625
626 continue;
627 }
628
629 ++usedPorts;
630
631 if (storeQueue[storeWBIdx].inst->isDataPrefetch()) {
632 incrStIdx(storeWBIdx);
633
634 continue;
635 }
636
637 assert(storeQueue[storeWBIdx].req);
638 assert(!storeQueue[storeWBIdx].committed);
639
640 DynInstPtr inst = storeQueue[storeWBIdx].inst;
641
642 Request *req = storeQueue[storeWBIdx].req;
643 storeQueue[storeWBIdx].committed = true;
644
645 assert(!inst->memData);
646 inst->memData = new uint8_t[64];
647
|
663 PacketPtr data_pkt = new Packet(req, MemCmd::WriteReq,
664 Packet::Broadcast);
665 data_pkt->dataStatic(inst->memData);
666
667 LSQSenderState *state = new LSQSenderState;
668 state->isLoad = false;
669 state->idx = storeWBIdx;
670 state->inst = inst;
671 data_pkt->senderState = state;
672
673 DPRINTF(LSQUnit, "D-Cache: Writing back store idx:%i PC:%#x "
674 "to Addr:%#x, data:%#x [sn:%lli]\n",
675 storeWBIdx, inst->readPC(),
676 req->getPaddr(), (int)*(inst->memData),
677 inst->seqNum);
678
679 // @todo: Remove this SC hack once the memory system handles it.
680 if (req->isLocked()) {
681 // Disable recording the result temporarily. Writing to
682 // misc regs normally updates the result, but this is not
683 // the desired behavior when handling store conditionals.
684 inst->recordResult = false;
685 bool success = TheISA::handleLockedWrite(inst.get(), req);
686 inst->recordResult = true;
687
688 if (!success) {
689 // Instantly complete this store.
690 DPRINTF(LSQUnit, "Store conditional [sn:%lli] failed. "
691 "Instantly completing it.\n",
692 inst->seqNum);
693 WritebackEvent *wb = new WritebackEvent(inst, data_pkt, this);
694 wb->schedule(curTick + 1);
695 delete state;
696 completeStore(storeWBIdx);
697 incrStIdx(storeWBIdx);
698 continue;
699 }
700 } else {
701 // Non-store conditionals do not need a writeback.
702 state->noWB = true;
703 }
704
705 if (!dcachePort->sendTiming(data_pkt)) {
706 if (data_pkt->result == Packet::BadAddress) {
707 panic("LSQ sent out a bad address for a completed store!");
708 }
709 // Need to handle becoming blocked on a store.
710 DPRINTF(IEW, "D-Cache became blocked when writing [sn:%lli], will"
711 "retry later\n",
712 inst->seqNum);
713 isStoreBlocked = true;
714 ++lsqCacheBlocked;
715 assert(retryPkt == NULL);
716 retryPkt = data_pkt;
717 lsq->setRetryTid(lsqID);
718 } else {
719 storePostSend(data_pkt);
720 }
721 }
722
723 // Not sure this should set it to 0.
724 usedPorts = 0;
725
726 assert(stores >= 0 && storesToWB >= 0);
727}
728
729/*template <class Impl>
730void
731LSQUnit<Impl>::removeMSHR(InstSeqNum seqNum)
732{
733 list<InstSeqNum>::iterator mshr_it = find(mshrSeqNums.begin(),
734 mshrSeqNums.end(),
735 seqNum);
736
737 if (mshr_it != mshrSeqNums.end()) {
738 mshrSeqNums.erase(mshr_it);
739 DPRINTF(LSQUnit, "Removing MSHR. count = %i\n",mshrSeqNums.size());
740 }
741}*/
742
743template <class Impl>
744void
745LSQUnit<Impl>::squash(const InstSeqNum &squashed_num)
746{
747 DPRINTF(LSQUnit, "Squashing until [sn:%lli]!"
748 "(Loads:%i Stores:%i)\n", squashed_num, loads, stores);
749
750 int load_idx = loadTail;
751 decrLdIdx(load_idx);
752
753 while (loads != 0 && loadQueue[load_idx]->seqNum > squashed_num) {
754 DPRINTF(LSQUnit,"Load Instruction PC %#x squashed, "
755 "[sn:%lli]\n",
756 loadQueue[load_idx]->readPC(),
757 loadQueue[load_idx]->seqNum);
758
759 if (isStalled() && load_idx == stallingLoadIdx) {
760 stalled = false;
761 stallingStoreIsn = 0;
762 stallingLoadIdx = 0;
763 }
764
765 // Clear the smart pointer to make sure it is decremented.
766 loadQueue[load_idx]->setSquashed();
767 loadQueue[load_idx] = NULL;
768 --loads;
769
770 // Inefficient!
771 loadTail = load_idx;
772
773 decrLdIdx(load_idx);
774 ++lsqSquashedLoads;
775 }
776
777 if (isLoadBlocked) {
778 if (squashed_num < blockedLoadSeqNum) {
779 isLoadBlocked = false;
780 loadBlockedHandled = false;
781 blockedLoadSeqNum = 0;
782 }
783 }
784
785 if (memDepViolator && squashed_num < memDepViolator->seqNum) {
786 memDepViolator = NULL;
787 }
788
789 int store_idx = storeTail;
790 decrStIdx(store_idx);
791
792 while (stores != 0 &&
793 storeQueue[store_idx].inst->seqNum > squashed_num) {
794 // Instructions marked as can WB are already committed.
795 if (storeQueue[store_idx].canWB) {
796 break;
797 }
798
799 DPRINTF(LSQUnit,"Store Instruction PC %#x squashed, "
800 "idx:%i [sn:%lli]\n",
801 storeQueue[store_idx].inst->readPC(),
802 store_idx, storeQueue[store_idx].inst->seqNum);
803
804 // I don't think this can happen. It should have been cleared
805 // by the stalling load.
806 if (isStalled() &&
807 storeQueue[store_idx].inst->seqNum == stallingStoreIsn) {
808 panic("Is stalled should have been cleared by stalling load!\n");
809 stalled = false;
810 stallingStoreIsn = 0;
811 }
812
813 // Clear the smart pointer to make sure it is decremented.
814 storeQueue[store_idx].inst->setSquashed();
815 storeQueue[store_idx].inst = NULL;
816 storeQueue[store_idx].canWB = 0;
817
818 // Must delete request now that it wasn't handed off to
819 // memory. This is quite ugly. @todo: Figure out the proper
820 // place to really handle request deletes.
821 delete storeQueue[store_idx].req;
822
823 storeQueue[store_idx].req = NULL;
824 --stores;
825
826 // Inefficient!
827 storeTail = store_idx;
828
829 decrStIdx(store_idx);
830 ++lsqSquashedStores;
831 }
832}
833
834template <class Impl>
835void
836LSQUnit<Impl>::storePostSend(PacketPtr pkt)
837{
838 if (isStalled() &&
839 storeQueue[storeWBIdx].inst->seqNum == stallingStoreIsn) {
840 DPRINTF(LSQUnit, "Unstalling, stalling store [sn:%lli] "
841 "load idx:%i\n",
842 stallingStoreIsn, stallingLoadIdx);
843 stalled = false;
844 stallingStoreIsn = 0;
845 iewStage->replayMemInst(loadQueue[stallingLoadIdx]);
846 }
847
848 if (!storeQueue[storeWBIdx].inst->isStoreConditional()) {
849 // The store is basically completed at this time. This
850 // only works so long as the checker doesn't try to
851 // verify the value in memory for stores.
852 storeQueue[storeWBIdx].inst->setCompleted();
853#if USE_CHECKER
854 if (cpu->checker) {
855 cpu->checker->verify(storeQueue[storeWBIdx].inst);
856 }
857#endif
858 }
859
860 if (pkt->result != Packet::Success) {
861 DPRINTF(LSQUnit,"D-Cache Write Miss on idx:%i!\n",
862 storeWBIdx);
863
864 DPRINTF(Activity, "Active st accessing mem miss [sn:%lli]\n",
865 storeQueue[storeWBIdx].inst->seqNum);
866
867 //mshrSeqNums.push_back(storeQueue[storeWBIdx].inst->seqNum);
868
869 //DPRINTF(LSQUnit, "Added MSHR. count = %i\n",mshrSeqNums.size());
870
871 // @todo: Increment stat here.
872 } else {
873 DPRINTF(LSQUnit,"D-Cache: Write Hit on idx:%i !\n",
874 storeWBIdx);
875
876 DPRINTF(Activity, "Active st accessing mem hit [sn:%lli]\n",
877 storeQueue[storeWBIdx].inst->seqNum);
878 }
879
880 incrStIdx(storeWBIdx);
881}
882
883template <class Impl>
884void
885LSQUnit<Impl>::writeback(DynInstPtr &inst, PacketPtr pkt)
886{
887 iewStage->wakeCPU();
888
889 // Squashed instructions do not need to complete their access.
890 if (inst->isSquashed()) {
891 iewStage->decrWb(inst->seqNum);
892 assert(!inst->isStore());
893 ++lsqIgnoredResponses;
894 return;
895 }
896
897 if (!inst->isExecuted()) {
898 inst->setExecuted();
899
900 // Complete access to copy data to proper place.
901 inst->completeAcc(pkt);
902 }
903
904 // Need to insert instruction into queue to commit
905 iewStage->instToCommit(inst);
906
907 iewStage->activityThisCycle();
908}
909
910template <class Impl>
911void
912LSQUnit<Impl>::completeStore(int store_idx)
913{
914 assert(storeQueue[store_idx].inst);
915 storeQueue[store_idx].completed = true;
916 --storesToWB;
917 // A bit conservative because a store completion may not free up entries,
918 // but hopefully avoids two store completions in one cycle from making
919 // the CPU tick twice.
920 cpu->wakeCPU();
921 cpu->activityThisCycle();
922
923 if (store_idx == storeHead) {
924 do {
925 incrStIdx(storeHead);
926
927 --stores;
928 } while (storeQueue[storeHead].completed &&
929 storeHead != storeTail);
930
931 iewStage->updateLSQNextCycle = true;
932 }
933
934 DPRINTF(LSQUnit, "Completing store [sn:%lli], idx:%i, store head "
935 "idx:%i\n",
936 storeQueue[store_idx].inst->seqNum, store_idx, storeHead);
937
938 if (isStalled() &&
939 storeQueue[store_idx].inst->seqNum == stallingStoreIsn) {
940 DPRINTF(LSQUnit, "Unstalling, stalling store [sn:%lli] "
941 "load idx:%i\n",
942 stallingStoreIsn, stallingLoadIdx);
943 stalled = false;
944 stallingStoreIsn = 0;
945 iewStage->replayMemInst(loadQueue[stallingLoadIdx]);
946 }
947
948 storeQueue[store_idx].inst->setCompleted();
949
950 // Tell the checker we've completed this instruction. Some stores
951 // may get reported twice to the checker, but the checker can
952 // handle that case.
953#if USE_CHECKER
954 if (cpu->checker) {
955 cpu->checker->verify(storeQueue[store_idx].inst);
956 }
957#endif
958}
959
960template <class Impl>
961void
962LSQUnit<Impl>::recvRetry()
963{
964 if (isStoreBlocked) {
965 assert(retryPkt != NULL);
966
967 if (dcachePort->sendTiming(retryPkt)) {
968 if (retryPkt->result == Packet::BadAddress) {
969 panic("LSQ sent out a bad address for a completed store!");
970 }
971 storePostSend(retryPkt);
972 retryPkt = NULL;
973 isStoreBlocked = false;
974 lsq->setRetryTid(-1);
975 } else {
976 // Still blocked!
977 ++lsqCacheBlocked;
978 lsq->setRetryTid(lsqID);
979 }
980 } else if (isLoadBlocked) {
981 DPRINTF(LSQUnit, "Loads squash themselves and all younger insts, "
982 "no need to resend packet.\n");
983 } else {
984 DPRINTF(LSQUnit, "Retry received but LSQ is no longer blocked.\n");
985 }
986}
987
988template <class Impl>
989inline void
990LSQUnit<Impl>::incrStIdx(int &store_idx)
991{
992 if (++store_idx >= SQEntries)
993 store_idx = 0;
994}
995
996template <class Impl>
997inline void
998LSQUnit<Impl>::decrStIdx(int &store_idx)
999{
1000 if (--store_idx < 0)
1001 store_idx += SQEntries;
1002}
1003
1004template <class Impl>
1005inline void
1006LSQUnit<Impl>::incrLdIdx(int &load_idx)
1007{
1008 if (++load_idx >= LQEntries)
1009 load_idx = 0;
1010}
1011
1012template <class Impl>
1013inline void
1014LSQUnit<Impl>::decrLdIdx(int &load_idx)
1015{
1016 if (--load_idx < 0)
1017 load_idx += LQEntries;
1018}
1019
1020template <class Impl>
1021void
1022LSQUnit<Impl>::dumpInsts()
1023{
1024 cprintf("Load store queue: Dumping instructions.\n");
1025 cprintf("Load queue size: %i\n", loads);
1026 cprintf("Load queue: ");
1027
1028 int load_idx = loadHead;
1029
1030 while (load_idx != loadTail && loadQueue[load_idx]) {
1031 cprintf("%#x ", loadQueue[load_idx]->readPC());
1032
1033 incrLdIdx(load_idx);
1034 }
1035
1036 cprintf("Store queue size: %i\n", stores);
1037 cprintf("Store queue: ");
1038
1039 int store_idx = storeHead;
1040
1041 while (store_idx != storeTail && storeQueue[store_idx].inst) {
1042 cprintf("%#x ", storeQueue[store_idx].inst->readPC());
1043
1044 incrStIdx(store_idx);
1045 }
1046
1047 cprintf("\n");
1048}
| 650 PacketPtr data_pkt = new Packet(req, MemCmd::WriteReq,
651 Packet::Broadcast);
652 data_pkt->dataStatic(inst->memData);
653
654 LSQSenderState *state = new LSQSenderState;
655 state->isLoad = false;
656 state->idx = storeWBIdx;
657 state->inst = inst;
658 data_pkt->senderState = state;
659
660 DPRINTF(LSQUnit, "D-Cache: Writing back store idx:%i PC:%#x "
661 "to Addr:%#x, data:%#x [sn:%lli]\n",
662 storeWBIdx, inst->readPC(),
663 req->getPaddr(), (int)*(inst->memData),
664 inst->seqNum);
665
666 // @todo: Remove this SC hack once the memory system handles it.
667 if (req->isLocked()) {
668 // Disable recording the result temporarily. Writing to
669 // misc regs normally updates the result, but this is not
670 // the desired behavior when handling store conditionals.
671 inst->recordResult = false;
672 bool success = TheISA::handleLockedWrite(inst.get(), req);
673 inst->recordResult = true;
674
675 if (!success) {
676 // Instantly complete this store.
677 DPRINTF(LSQUnit, "Store conditional [sn:%lli] failed. "
678 "Instantly completing it.\n",
679 inst->seqNum);
680 WritebackEvent *wb = new WritebackEvent(inst, data_pkt, this);
681 wb->schedule(curTick + 1);
682 delete state;
683 completeStore(storeWBIdx);
684 incrStIdx(storeWBIdx);
685 continue;
686 }
687 } else {
688 // Non-store conditionals do not need a writeback.
689 state->noWB = true;
690 }
691
692 if (!dcachePort->sendTiming(data_pkt)) {
693 if (data_pkt->result == Packet::BadAddress) {
694 panic("LSQ sent out a bad address for a completed store!");
695 }
696 // Need to handle becoming blocked on a store.
697 DPRINTF(IEW, "D-Cache became blocked when writing [sn:%lli], will"
698 "retry later\n",
699 inst->seqNum);
700 isStoreBlocked = true;
701 ++lsqCacheBlocked;
702 assert(retryPkt == NULL);
703 retryPkt = data_pkt;
704 lsq->setRetryTid(lsqID);
705 } else {
706 storePostSend(data_pkt);
707 }
708 }
709
710 // Not sure this should set it to 0.
711 usedPorts = 0;
712
713 assert(stores >= 0 && storesToWB >= 0);
714}
715
716/*template <class Impl>
717void
718LSQUnit<Impl>::removeMSHR(InstSeqNum seqNum)
719{
720 list<InstSeqNum>::iterator mshr_it = find(mshrSeqNums.begin(),
721 mshrSeqNums.end(),
722 seqNum);
723
724 if (mshr_it != mshrSeqNums.end()) {
725 mshrSeqNums.erase(mshr_it);
726 DPRINTF(LSQUnit, "Removing MSHR. count = %i\n",mshrSeqNums.size());
727 }
728}*/
729
730template <class Impl>
731void
732LSQUnit<Impl>::squash(const InstSeqNum &squashed_num)
733{
734 DPRINTF(LSQUnit, "Squashing until [sn:%lli]!"
735 "(Loads:%i Stores:%i)\n", squashed_num, loads, stores);
736
737 int load_idx = loadTail;
738 decrLdIdx(load_idx);
739
740 while (loads != 0 && loadQueue[load_idx]->seqNum > squashed_num) {
741 DPRINTF(LSQUnit,"Load Instruction PC %#x squashed, "
742 "[sn:%lli]\n",
743 loadQueue[load_idx]->readPC(),
744 loadQueue[load_idx]->seqNum);
745
746 if (isStalled() && load_idx == stallingLoadIdx) {
747 stalled = false;
748 stallingStoreIsn = 0;
749 stallingLoadIdx = 0;
750 }
751
752 // Clear the smart pointer to make sure it is decremented.
753 loadQueue[load_idx]->setSquashed();
754 loadQueue[load_idx] = NULL;
755 --loads;
756
757 // Inefficient!
758 loadTail = load_idx;
759
760 decrLdIdx(load_idx);
761 ++lsqSquashedLoads;
762 }
763
764 if (isLoadBlocked) {
765 if (squashed_num < blockedLoadSeqNum) {
766 isLoadBlocked = false;
767 loadBlockedHandled = false;
768 blockedLoadSeqNum = 0;
769 }
770 }
771
772 if (memDepViolator && squashed_num < memDepViolator->seqNum) {
773 memDepViolator = NULL;
774 }
775
776 int store_idx = storeTail;
777 decrStIdx(store_idx);
778
779 while (stores != 0 &&
780 storeQueue[store_idx].inst->seqNum > squashed_num) {
781 // Instructions marked as can WB are already committed.
782 if (storeQueue[store_idx].canWB) {
783 break;
784 }
785
786 DPRINTF(LSQUnit,"Store Instruction PC %#x squashed, "
787 "idx:%i [sn:%lli]\n",
788 storeQueue[store_idx].inst->readPC(),
789 store_idx, storeQueue[store_idx].inst->seqNum);
790
791 // I don't think this can happen. It should have been cleared
792 // by the stalling load.
793 if (isStalled() &&
794 storeQueue[store_idx].inst->seqNum == stallingStoreIsn) {
795 panic("Is stalled should have been cleared by stalling load!\n");
796 stalled = false;
797 stallingStoreIsn = 0;
798 }
799
800 // Clear the smart pointer to make sure it is decremented.
801 storeQueue[store_idx].inst->setSquashed();
802 storeQueue[store_idx].inst = NULL;
803 storeQueue[store_idx].canWB = 0;
804
805 // Must delete request now that it wasn't handed off to
806 // memory. This is quite ugly. @todo: Figure out the proper
807 // place to really handle request deletes.
808 delete storeQueue[store_idx].req;
809
810 storeQueue[store_idx].req = NULL;
811 --stores;
812
813 // Inefficient!
814 storeTail = store_idx;
815
816 decrStIdx(store_idx);
817 ++lsqSquashedStores;
818 }
819}
820
821template <class Impl>
822void
823LSQUnit<Impl>::storePostSend(PacketPtr pkt)
824{
825 if (isStalled() &&
826 storeQueue[storeWBIdx].inst->seqNum == stallingStoreIsn) {
827 DPRINTF(LSQUnit, "Unstalling, stalling store [sn:%lli] "
828 "load idx:%i\n",
829 stallingStoreIsn, stallingLoadIdx);
830 stalled = false;
831 stallingStoreIsn = 0;
832 iewStage->replayMemInst(loadQueue[stallingLoadIdx]);
833 }
834
835 if (!storeQueue[storeWBIdx].inst->isStoreConditional()) {
836 // The store is basically completed at this time. This
837 // only works so long as the checker doesn't try to
838 // verify the value in memory for stores.
839 storeQueue[storeWBIdx].inst->setCompleted();
840#if USE_CHECKER
841 if (cpu->checker) {
842 cpu->checker->verify(storeQueue[storeWBIdx].inst);
843 }
844#endif
845 }
846
847 if (pkt->result != Packet::Success) {
848 DPRINTF(LSQUnit,"D-Cache Write Miss on idx:%i!\n",
849 storeWBIdx);
850
851 DPRINTF(Activity, "Active st accessing mem miss [sn:%lli]\n",
852 storeQueue[storeWBIdx].inst->seqNum);
853
854 //mshrSeqNums.push_back(storeQueue[storeWBIdx].inst->seqNum);
855
856 //DPRINTF(LSQUnit, "Added MSHR. count = %i\n",mshrSeqNums.size());
857
858 // @todo: Increment stat here.
859 } else {
860 DPRINTF(LSQUnit,"D-Cache: Write Hit on idx:%i !\n",
861 storeWBIdx);
862
863 DPRINTF(Activity, "Active st accessing mem hit [sn:%lli]\n",
864 storeQueue[storeWBIdx].inst->seqNum);
865 }
866
867 incrStIdx(storeWBIdx);
868}
869
870template <class Impl>
871void
872LSQUnit<Impl>::writeback(DynInstPtr &inst, PacketPtr pkt)
873{
874 iewStage->wakeCPU();
875
876 // Squashed instructions do not need to complete their access.
877 if (inst->isSquashed()) {
878 iewStage->decrWb(inst->seqNum);
879 assert(!inst->isStore());
880 ++lsqIgnoredResponses;
881 return;
882 }
883
884 if (!inst->isExecuted()) {
885 inst->setExecuted();
886
887 // Complete access to copy data to proper place.
888 inst->completeAcc(pkt);
889 }
890
891 // Need to insert instruction into queue to commit
892 iewStage->instToCommit(inst);
893
894 iewStage->activityThisCycle();
895}
896
897template <class Impl>
898void
899LSQUnit<Impl>::completeStore(int store_idx)
900{
901 assert(storeQueue[store_idx].inst);
902 storeQueue[store_idx].completed = true;
903 --storesToWB;
904 // A bit conservative because a store completion may not free up entries,
905 // but hopefully avoids two store completions in one cycle from making
906 // the CPU tick twice.
907 cpu->wakeCPU();
908 cpu->activityThisCycle();
909
910 if (store_idx == storeHead) {
911 do {
912 incrStIdx(storeHead);
913
914 --stores;
915 } while (storeQueue[storeHead].completed &&
916 storeHead != storeTail);
917
918 iewStage->updateLSQNextCycle = true;
919 }
920
921 DPRINTF(LSQUnit, "Completing store [sn:%lli], idx:%i, store head "
922 "idx:%i\n",
923 storeQueue[store_idx].inst->seqNum, store_idx, storeHead);
924
925 if (isStalled() &&
926 storeQueue[store_idx].inst->seqNum == stallingStoreIsn) {
927 DPRINTF(LSQUnit, "Unstalling, stalling store [sn:%lli] "
928 "load idx:%i\n",
929 stallingStoreIsn, stallingLoadIdx);
930 stalled = false;
931 stallingStoreIsn = 0;
932 iewStage->replayMemInst(loadQueue[stallingLoadIdx]);
933 }
934
935 storeQueue[store_idx].inst->setCompleted();
936
937 // Tell the checker we've completed this instruction. Some stores
938 // may get reported twice to the checker, but the checker can
939 // handle that case.
940#if USE_CHECKER
941 if (cpu->checker) {
942 cpu->checker->verify(storeQueue[store_idx].inst);
943 }
944#endif
945}
946
947template <class Impl>
948void
949LSQUnit<Impl>::recvRetry()
950{
951 if (isStoreBlocked) {
952 assert(retryPkt != NULL);
953
954 if (dcachePort->sendTiming(retryPkt)) {
955 if (retryPkt->result == Packet::BadAddress) {
956 panic("LSQ sent out a bad address for a completed store!");
957 }
958 storePostSend(retryPkt);
959 retryPkt = NULL;
960 isStoreBlocked = false;
961 lsq->setRetryTid(-1);
962 } else {
963 // Still blocked!
964 ++lsqCacheBlocked;
965 lsq->setRetryTid(lsqID);
966 }
967 } else if (isLoadBlocked) {
968 DPRINTF(LSQUnit, "Loads squash themselves and all younger insts, "
969 "no need to resend packet.\n");
970 } else {
971 DPRINTF(LSQUnit, "Retry received but LSQ is no longer blocked.\n");
972 }
973}
974
975template <class Impl>
976inline void
977LSQUnit<Impl>::incrStIdx(int &store_idx)
978{
979 if (++store_idx >= SQEntries)
980 store_idx = 0;
981}
982
983template <class Impl>
984inline void
985LSQUnit<Impl>::decrStIdx(int &store_idx)
986{
987 if (--store_idx < 0)
988 store_idx += SQEntries;
989}
990
991template <class Impl>
992inline void
993LSQUnit<Impl>::incrLdIdx(int &load_idx)
994{
995 if (++load_idx >= LQEntries)
996 load_idx = 0;
997}
998
999template <class Impl>
1000inline void
1001LSQUnit<Impl>::decrLdIdx(int &load_idx)
1002{
1003 if (--load_idx < 0)
1004 load_idx += LQEntries;
1005}
1006
1007template <class Impl>
1008void
1009LSQUnit<Impl>::dumpInsts()
1010{
1011 cprintf("Load store queue: Dumping instructions.\n");
1012 cprintf("Load queue size: %i\n", loads);
1013 cprintf("Load queue: ");
1014
1015 int load_idx = loadHead;
1016
1017 while (load_idx != loadTail && loadQueue[load_idx]) {
1018 cprintf("%#x ", loadQueue[load_idx]->readPC());
1019
1020 incrLdIdx(load_idx);
1021 }
1022
1023 cprintf("Store queue size: %i\n", stores);
1024 cprintf("Store queue: ");
1025
1026 int store_idx = storeHead;
1027
1028 while (store_idx != storeTail && storeQueue[store_idx].inst) {
1029 cprintf("%#x ", storeQueue[store_idx].inst->readPC());
1030
1031 incrStIdx(store_idx);
1032 }
1033
1034 cprintf("\n");
1035}
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