1/*
2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Kevin Lim
29 * Korey Sewell
30 */
31
32#include "arch/locked_mem.hh"
33#include "config/use_checker.hh"
34
35#include "cpu/o3/lsq.hh"
36#include "cpu/o3/lsq_unit.hh"
37#include "base/str.hh"
38#include "mem/packet.hh"
39#include "mem/request.hh"
40
41#if USE_CHECKER
42#include "cpu/checker/cpu.hh"
43#endif
44
45template<class Impl>
46LSQUnit<Impl>::WritebackEvent::WritebackEvent(DynInstPtr &_inst, PacketPtr _pkt,
47 LSQUnit *lsq_ptr)
48 : Event(&mainEventQueue), inst(_inst), pkt(_pkt), lsqPtr(lsq_ptr)
49{
50 this->setFlags(Event::AutoDelete);
51}
52
53template<class Impl>
54void
55LSQUnit<Impl>::WritebackEvent::process()
56{
57 if (!lsqPtr->isSwitchedOut()) {
58 lsqPtr->writeback(inst, pkt);
59 }
| 1/*
2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Kevin Lim
29 * Korey Sewell
30 */
31
32#include "arch/locked_mem.hh"
33#include "config/use_checker.hh"
34
35#include "cpu/o3/lsq.hh"
36#include "cpu/o3/lsq_unit.hh"
37#include "base/str.hh"
38#include "mem/packet.hh"
39#include "mem/request.hh"
40
41#if USE_CHECKER
42#include "cpu/checker/cpu.hh"
43#endif
44
45template<class Impl>
46LSQUnit<Impl>::WritebackEvent::WritebackEvent(DynInstPtr &_inst, PacketPtr _pkt,
47 LSQUnit *lsq_ptr)
48 : Event(&mainEventQueue), inst(_inst), pkt(_pkt), lsqPtr(lsq_ptr)
49{
50 this->setFlags(Event::AutoDelete);
51}
52
53template<class Impl>
54void
55LSQUnit<Impl>::WritebackEvent::process()
56{
57 if (!lsqPtr->isSwitchedOut()) {
58 lsqPtr->writeback(inst, pkt);
59 }
|
87 } else {
88 if (!state->noWB) {
89 writeback(inst, pkt);
90 }
91
92 if (inst->isStore()) {
93 completeStore(state->idx);
94 }
95 }
96
97 delete state;
98 delete pkt->req;
99 delete pkt;
100}
101
102template <class Impl>
103LSQUnit<Impl>::LSQUnit()
104 : loads(0), stores(0), storesToWB(0), stalled(false),
105 isStoreBlocked(false), isLoadBlocked(false),
106 loadBlockedHandled(false)
107{
108}
109
110template<class Impl>
111void
112LSQUnit<Impl>::init(Params *params, LSQ *lsq_ptr, unsigned maxLQEntries,
113 unsigned maxSQEntries, unsigned id)
114{
115// DPRINTF(LSQUnit, "Creating LSQUnit%i object.\n",id);
116
117 switchedOut = false;
118
119 lsq = lsq_ptr;
120
121 lsqID = id;
122
123 // Add 1 for the sentinel entry (they are circular queues).
124 LQEntries = maxLQEntries + 1;
125 SQEntries = maxSQEntries + 1;
126
127 loadQueue.resize(LQEntries);
128 storeQueue.resize(SQEntries);
129
130 loadHead = loadTail = 0;
131
132 storeHead = storeWBIdx = storeTail = 0;
133
134 usedPorts = 0;
135 cachePorts = params->cachePorts;
136
137 retryPkt = NULL;
138 memDepViolator = NULL;
139
140 blockedLoadSeqNum = 0;
141}
142
143template<class Impl>
144void
145LSQUnit<Impl>::setCPU(O3CPU *cpu_ptr)
146{
147 cpu = cpu_ptr;
148
149#if USE_CHECKER
150 if (cpu->checker) {
151 cpu->checker->setDcachePort(dcachePort);
152 }
153#endif
154}
155
156template<class Impl>
157std::string
158LSQUnit<Impl>::name() const
159{
160 if (Impl::MaxThreads == 1) {
161 return iewStage->name() + ".lsq";
162 } else {
163 return iewStage->name() + ".lsq.thread." + to_string(lsqID);
164 }
165}
166
167template<class Impl>
168void
169LSQUnit<Impl>::regStats()
170{
171 lsqForwLoads
172 .name(name() + ".forwLoads")
173 .desc("Number of loads that had data forwarded from stores");
174
175 invAddrLoads
176 .name(name() + ".invAddrLoads")
177 .desc("Number of loads ignored due to an invalid address");
178
179 lsqSquashedLoads
180 .name(name() + ".squashedLoads")
181 .desc("Number of loads squashed");
182
183 lsqIgnoredResponses
184 .name(name() + ".ignoredResponses")
185 .desc("Number of memory responses ignored because the instruction is squashed");
186
187 lsqMemOrderViolation
188 .name(name() + ".memOrderViolation")
189 .desc("Number of memory ordering violations");
190
191 lsqSquashedStores
192 .name(name() + ".squashedStores")
193 .desc("Number of stores squashed");
194
195 invAddrSwpfs
196 .name(name() + ".invAddrSwpfs")
197 .desc("Number of software prefetches ignored due to an invalid address");
198
199 lsqBlockedLoads
200 .name(name() + ".blockedLoads")
201 .desc("Number of blocked loads due to partial load-store forwarding");
202
203 lsqRescheduledLoads
204 .name(name() + ".rescheduledLoads")
205 .desc("Number of loads that were rescheduled");
206
207 lsqCacheBlocked
208 .name(name() + ".cacheBlocked")
209 .desc("Number of times an access to memory failed due to the cache being blocked");
210}
211
212template<class Impl>
213void
214LSQUnit<Impl>::clearLQ()
215{
216 loadQueue.clear();
217}
218
219template<class Impl>
220void
221LSQUnit<Impl>::clearSQ()
222{
223 storeQueue.clear();
224}
225
226template<class Impl>
227void
228LSQUnit<Impl>::switchOut()
229{
230 switchedOut = true;
231 for (int i = 0; i < loadQueue.size(); ++i) {
232 assert(!loadQueue[i]);
233 loadQueue[i] = NULL;
234 }
235
236 assert(storesToWB == 0);
237}
238
239template<class Impl>
240void
241LSQUnit<Impl>::takeOverFrom()
242{
243 switchedOut = false;
244 loads = stores = storesToWB = 0;
245
246 loadHead = loadTail = 0;
247
248 storeHead = storeWBIdx = storeTail = 0;
249
250 usedPorts = 0;
251
252 memDepViolator = NULL;
253
254 blockedLoadSeqNum = 0;
255
256 stalled = false;
257 isLoadBlocked = false;
258 loadBlockedHandled = false;
259}
260
261template<class Impl>
262void
263LSQUnit<Impl>::resizeLQ(unsigned size)
264{
265 unsigned size_plus_sentinel = size + 1;
266 assert(size_plus_sentinel >= LQEntries);
267
268 if (size_plus_sentinel > LQEntries) {
269 while (size_plus_sentinel > loadQueue.size()) {
270 DynInstPtr dummy;
271 loadQueue.push_back(dummy);
272 LQEntries++;
273 }
274 } else {
275 LQEntries = size_plus_sentinel;
276 }
277
278}
279
280template<class Impl>
281void
282LSQUnit<Impl>::resizeSQ(unsigned size)
283{
284 unsigned size_plus_sentinel = size + 1;
285 if (size_plus_sentinel > SQEntries) {
286 while (size_plus_sentinel > storeQueue.size()) {
287 SQEntry dummy;
288 storeQueue.push_back(dummy);
289 SQEntries++;
290 }
291 } else {
292 SQEntries = size_plus_sentinel;
293 }
294}
295
296template <class Impl>
297void
298LSQUnit<Impl>::insert(DynInstPtr &inst)
299{
300 assert(inst->isMemRef());
301
302 assert(inst->isLoad() || inst->isStore());
303
304 if (inst->isLoad()) {
305 insertLoad(inst);
306 } else {
307 insertStore(inst);
308 }
309
310 inst->setInLSQ();
311}
312
313template <class Impl>
314void
315LSQUnit<Impl>::insertLoad(DynInstPtr &load_inst)
316{
317 assert((loadTail + 1) % LQEntries != loadHead);
318 assert(loads < LQEntries);
319
320 DPRINTF(LSQUnit, "Inserting load PC %#x, idx:%i [sn:%lli]\n",
321 load_inst->readPC(), loadTail, load_inst->seqNum);
322
323 load_inst->lqIdx = loadTail;
324
325 if (stores == 0) {
326 load_inst->sqIdx = -1;
327 } else {
328 load_inst->sqIdx = storeTail;
329 }
330
331 loadQueue[loadTail] = load_inst;
332
333 incrLdIdx(loadTail);
334
335 ++loads;
336}
337
338template <class Impl>
339void
340LSQUnit<Impl>::insertStore(DynInstPtr &store_inst)
341{
342 // Make sure it is not full before inserting an instruction.
343 assert((storeTail + 1) % SQEntries != storeHead);
344 assert(stores < SQEntries);
345
346 DPRINTF(LSQUnit, "Inserting store PC %#x, idx:%i [sn:%lli]\n",
347 store_inst->readPC(), storeTail, store_inst->seqNum);
348
349 store_inst->sqIdx = storeTail;
350 store_inst->lqIdx = loadTail;
351
352 storeQueue[storeTail] = SQEntry(store_inst);
353
354 incrStIdx(storeTail);
355
356 ++stores;
357}
358
359template <class Impl>
360typename Impl::DynInstPtr
361LSQUnit<Impl>::getMemDepViolator()
362{
363 DynInstPtr temp = memDepViolator;
364
365 memDepViolator = NULL;
366
367 return temp;
368}
369
370template <class Impl>
371unsigned
372LSQUnit<Impl>::numFreeEntries()
373{
374 unsigned free_lq_entries = LQEntries - loads;
375 unsigned free_sq_entries = SQEntries - stores;
376
377 // Both the LQ and SQ entries have an extra dummy entry to differentiate
378 // empty/full conditions. Subtract 1 from the free entries.
379 if (free_lq_entries < free_sq_entries) {
380 return free_lq_entries - 1;
381 } else {
382 return free_sq_entries - 1;
383 }
384}
385
386template <class Impl>
387int
388LSQUnit<Impl>::numLoadsReady()
389{
390 int load_idx = loadHead;
391 int retval = 0;
392
393 while (load_idx != loadTail) {
394 assert(loadQueue[load_idx]);
395
396 if (loadQueue[load_idx]->readyToIssue()) {
397 ++retval;
398 }
399 }
400
401 return retval;
402}
403
404template <class Impl>
405Fault
406LSQUnit<Impl>::executeLoad(DynInstPtr &inst)
407{
408 using namespace TheISA;
409 // Execute a specific load.
410 Fault load_fault = NoFault;
411
412 DPRINTF(LSQUnit, "Executing load PC %#x, [sn:%lli]\n",
413 inst->readPC(),inst->seqNum);
414
415 assert(!inst->isSquashed());
416
417 load_fault = inst->initiateAcc();
418
419 // If the instruction faulted, then we need to send it along to commit
420 // without the instruction completing.
421 if (load_fault != NoFault) {
422 // Send this instruction to commit, also make sure iew stage
423 // realizes there is activity.
424 // Mark it as executed unless it is an uncached load that
425 // needs to hit the head of commit.
426 if (!(inst->hasRequest() && inst->uncacheable()) ||
427 inst->isAtCommit()) {
428 inst->setExecuted();
429 }
430 iewStage->instToCommit(inst);
431 iewStage->activityThisCycle();
432 } else if (!loadBlocked()) {
433 assert(inst->effAddrValid);
434 int load_idx = inst->lqIdx;
435 incrLdIdx(load_idx);
436 while (load_idx != loadTail) {
437 // Really only need to check loads that have actually executed
438
439 // @todo: For now this is extra conservative, detecting a
440 // violation if the addresses match assuming all accesses
441 // are quad word accesses.
442
443 // @todo: Fix this, magic number being used here
444 if (loadQueue[load_idx]->effAddrValid &&
445 (loadQueue[load_idx]->effAddr >> 8) ==
446 (inst->effAddr >> 8)) {
447 // A load incorrectly passed this load. Squash and refetch.
448 // For now return a fault to show that it was unsuccessful.
449 DynInstPtr violator = loadQueue[load_idx];
450 if (!memDepViolator ||
451 (violator->seqNum < memDepViolator->seqNum)) {
452 memDepViolator = violator;
453 } else {
454 break;
455 }
456
457 ++lsqMemOrderViolation;
458
459 return genMachineCheckFault();
460 }
461
462 incrLdIdx(load_idx);
463 }
464 }
465
466 return load_fault;
467}
468
469template <class Impl>
470Fault
471LSQUnit<Impl>::executeStore(DynInstPtr &store_inst)
472{
473 using namespace TheISA;
474 // Make sure that a store exists.
475 assert(stores != 0);
476
477 int store_idx = store_inst->sqIdx;
478
479 DPRINTF(LSQUnit, "Executing store PC %#x [sn:%lli]\n",
480 store_inst->readPC(), store_inst->seqNum);
481
482 assert(!store_inst->isSquashed());
483
484 // Check the recently completed loads to see if any match this store's
485 // address. If so, then we have a memory ordering violation.
486 int load_idx = store_inst->lqIdx;
487
488 Fault store_fault = store_inst->initiateAcc();
489
490 if (storeQueue[store_idx].size == 0) {
491 DPRINTF(LSQUnit,"Fault on Store PC %#x, [sn:%lli],Size = 0\n",
492 store_inst->readPC(),store_inst->seqNum);
493
494 return store_fault;
495 }
496
497 assert(store_fault == NoFault);
498
499 if (store_inst->isStoreConditional()) {
500 // Store conditionals need to set themselves as able to
501 // writeback if we haven't had a fault by here.
502 storeQueue[store_idx].canWB = true;
503
504 ++storesToWB;
505 }
506
507 assert(store_inst->effAddrValid);
508 while (load_idx != loadTail) {
509 // Really only need to check loads that have actually executed
510 // It's safe to check all loads because effAddr is set to
511 // InvalAddr when the dyn inst is created.
512
513 // @todo: For now this is extra conservative, detecting a
514 // violation if the addresses match assuming all accesses
515 // are quad word accesses.
516
517 // @todo: Fix this, magic number being used here
518 if (loadQueue[load_idx]->effAddrValid &&
519 (loadQueue[load_idx]->effAddr >> 8) ==
520 (store_inst->effAddr >> 8)) {
521 // A load incorrectly passed this store. Squash and refetch.
522 // For now return a fault to show that it was unsuccessful.
523 DynInstPtr violator = loadQueue[load_idx];
524 if (!memDepViolator ||
525 (violator->seqNum < memDepViolator->seqNum)) {
526 memDepViolator = violator;
527 } else {
528 break;
529 }
530
531 ++lsqMemOrderViolation;
532
533 return genMachineCheckFault();
534 }
535
536 incrLdIdx(load_idx);
537 }
538
539 return store_fault;
540}
541
542template <class Impl>
543void
544LSQUnit<Impl>::commitLoad()
545{
546 assert(loadQueue[loadHead]);
547
548 DPRINTF(LSQUnit, "Committing head load instruction, PC %#x\n",
549 loadQueue[loadHead]->readPC());
550
551 loadQueue[loadHead] = NULL;
552
553 incrLdIdx(loadHead);
554
555 --loads;
556}
557
558template <class Impl>
559void
560LSQUnit<Impl>::commitLoads(InstSeqNum &youngest_inst)
561{
562 assert(loads == 0 || loadQueue[loadHead]);
563
564 while (loads != 0 && loadQueue[loadHead]->seqNum <= youngest_inst) {
565 commitLoad();
566 }
567}
568
569template <class Impl>
570void
571LSQUnit<Impl>::commitStores(InstSeqNum &youngest_inst)
572{
573 assert(stores == 0 || storeQueue[storeHead].inst);
574
575 int store_idx = storeHead;
576
577 while (store_idx != storeTail) {
578 assert(storeQueue[store_idx].inst);
579 // Mark any stores that are now committed and have not yet
580 // been marked as able to write back.
581 if (!storeQueue[store_idx].canWB) {
582 if (storeQueue[store_idx].inst->seqNum > youngest_inst) {
583 break;
584 }
585 DPRINTF(LSQUnit, "Marking store as able to write back, PC "
586 "%#x [sn:%lli]\n",
587 storeQueue[store_idx].inst->readPC(),
588 storeQueue[store_idx].inst->seqNum);
589
590 storeQueue[store_idx].canWB = true;
591
592 ++storesToWB;
593 }
594
595 incrStIdx(store_idx);
596 }
597}
598
599template <class Impl>
600void
601LSQUnit<Impl>::writebackStores()
602{
603 while (storesToWB > 0 &&
604 storeWBIdx != storeTail &&
605 storeQueue[storeWBIdx].inst &&
606 storeQueue[storeWBIdx].canWB &&
607 usedPorts < cachePorts) {
608
609 if (isStoreBlocked || lsq->cacheBlocked()) {
610 DPRINTF(LSQUnit, "Unable to write back any more stores, cache"
611 " is blocked!\n");
612 break;
613 }
614
615 // Store didn't write any data so no need to write it back to
616 // memory.
617 if (storeQueue[storeWBIdx].size == 0) {
618 completeStore(storeWBIdx);
619
620 incrStIdx(storeWBIdx);
621
622 continue;
623 }
624
625 ++usedPorts;
626
627 if (storeQueue[storeWBIdx].inst->isDataPrefetch()) {
628 incrStIdx(storeWBIdx);
629
630 continue;
631 }
632
633 assert(storeQueue[storeWBIdx].req);
634 assert(!storeQueue[storeWBIdx].committed);
635
636 DynInstPtr inst = storeQueue[storeWBIdx].inst;
637
638 Request *req = storeQueue[storeWBIdx].req;
639 storeQueue[storeWBIdx].committed = true;
640
641 assert(!inst->memData);
642 inst->memData = new uint8_t[64];
643
644 TheISA::IntReg convertedData =
645 TheISA::htog(storeQueue[storeWBIdx].data);
646
647 //FIXME This is a hack to get SPARC working. It, along with endianness
648 //in the memory system in general, need to be straightened out more
649 //formally. The problem is that the data's endianness is swapped when
650 //it's in the 64 bit data field in the store queue. The data that you
651 //want won't start at the beginning of the field anymore unless it was
652 //a 64 bit access.
653 memcpy(inst->memData,
654 (uint8_t *)&convertedData +
655 (TheISA::ByteOrderDiffers ?
656 (sizeof(TheISA::IntReg) - req->getSize()) : 0),
657 req->getSize());
658
659 PacketPtr data_pkt = new Packet(req, MemCmd::WriteReq,
660 Packet::Broadcast);
661 data_pkt->dataStatic(inst->memData);
662
663 LSQSenderState *state = new LSQSenderState;
664 state->isLoad = false;
665 state->idx = storeWBIdx;
666 state->inst = inst;
667 data_pkt->senderState = state;
668
669 DPRINTF(LSQUnit, "D-Cache: Writing back store idx:%i PC:%#x "
670 "to Addr:%#x, data:%#x [sn:%lli]\n",
671 storeWBIdx, inst->readPC(),
672 req->getPaddr(), (int)*(inst->memData),
673 inst->seqNum);
674
675 // @todo: Remove this SC hack once the memory system handles it.
676 if (req->isLocked()) {
677 // Disable recording the result temporarily. Writing to
678 // misc regs normally updates the result, but this is not
679 // the desired behavior when handling store conditionals.
680 inst->recordResult = false;
681 bool success = TheISA::handleLockedWrite(inst.get(), req);
682 inst->recordResult = true;
683
684 if (!success) {
685 // Instantly complete this store.
686 DPRINTF(LSQUnit, "Store conditional [sn:%lli] failed. "
687 "Instantly completing it.\n",
688 inst->seqNum);
689 WritebackEvent *wb = new WritebackEvent(inst, data_pkt, this);
690 wb->schedule(curTick + 1);
691 delete state;
692 completeStore(storeWBIdx);
693 incrStIdx(storeWBIdx);
694 continue;
695 }
696 } else {
697 // Non-store conditionals do not need a writeback.
698 state->noWB = true;
699 }
700
701 if (!dcachePort->sendTiming(data_pkt)) {
702 if (data_pkt->result == Packet::BadAddress) {
703 panic("LSQ sent out a bad address for a completed store!");
704 }
705 // Need to handle becoming blocked on a store.
706 DPRINTF(IEW, "D-Cache became blocked when writing [sn:%lli], will"
707 "retry later\n",
708 inst->seqNum);
709 isStoreBlocked = true;
710 ++lsqCacheBlocked;
711 assert(retryPkt == NULL);
712 retryPkt = data_pkt;
713 lsq->setRetryTid(lsqID);
714 } else {
715 storePostSend(data_pkt);
716 }
717 }
718
719 // Not sure this should set it to 0.
720 usedPorts = 0;
721
722 assert(stores >= 0 && storesToWB >= 0);
723}
724
725/*template <class Impl>
726void
727LSQUnit<Impl>::removeMSHR(InstSeqNum seqNum)
728{
729 list<InstSeqNum>::iterator mshr_it = find(mshrSeqNums.begin(),
730 mshrSeqNums.end(),
731 seqNum);
732
733 if (mshr_it != mshrSeqNums.end()) {
734 mshrSeqNums.erase(mshr_it);
735 DPRINTF(LSQUnit, "Removing MSHR. count = %i\n",mshrSeqNums.size());
736 }
737}*/
738
739template <class Impl>
740void
741LSQUnit<Impl>::squash(const InstSeqNum &squashed_num)
742{
743 DPRINTF(LSQUnit, "Squashing until [sn:%lli]!"
744 "(Loads:%i Stores:%i)\n", squashed_num, loads, stores);
745
746 int load_idx = loadTail;
747 decrLdIdx(load_idx);
748
749 while (loads != 0 && loadQueue[load_idx]->seqNum > squashed_num) {
750 DPRINTF(LSQUnit,"Load Instruction PC %#x squashed, "
751 "[sn:%lli]\n",
752 loadQueue[load_idx]->readPC(),
753 loadQueue[load_idx]->seqNum);
754
755 if (isStalled() && load_idx == stallingLoadIdx) {
756 stalled = false;
757 stallingStoreIsn = 0;
758 stallingLoadIdx = 0;
759 }
760
761 // Clear the smart pointer to make sure it is decremented.
762 loadQueue[load_idx]->setSquashed();
763 loadQueue[load_idx] = NULL;
764 --loads;
765
766 // Inefficient!
767 loadTail = load_idx;
768
769 decrLdIdx(load_idx);
770 ++lsqSquashedLoads;
771 }
772
773 if (isLoadBlocked) {
774 if (squashed_num < blockedLoadSeqNum) {
775 isLoadBlocked = false;
776 loadBlockedHandled = false;
777 blockedLoadSeqNum = 0;
778 }
779 }
780
781 if (memDepViolator && squashed_num < memDepViolator->seqNum) {
782 memDepViolator = NULL;
783 }
784
785 int store_idx = storeTail;
786 decrStIdx(store_idx);
787
788 while (stores != 0 &&
789 storeQueue[store_idx].inst->seqNum > squashed_num) {
790 // Instructions marked as can WB are already committed.
791 if (storeQueue[store_idx].canWB) {
792 break;
793 }
794
795 DPRINTF(LSQUnit,"Store Instruction PC %#x squashed, "
796 "idx:%i [sn:%lli]\n",
797 storeQueue[store_idx].inst->readPC(),
798 store_idx, storeQueue[store_idx].inst->seqNum);
799
800 // I don't think this can happen. It should have been cleared
801 // by the stalling load.
802 if (isStalled() &&
803 storeQueue[store_idx].inst->seqNum == stallingStoreIsn) {
804 panic("Is stalled should have been cleared by stalling load!\n");
805 stalled = false;
806 stallingStoreIsn = 0;
807 }
808
809 // Clear the smart pointer to make sure it is decremented.
810 storeQueue[store_idx].inst->setSquashed();
811 storeQueue[store_idx].inst = NULL;
812 storeQueue[store_idx].canWB = 0;
813
814 // Must delete request now that it wasn't handed off to
815 // memory. This is quite ugly. @todo: Figure out the proper
816 // place to really handle request deletes.
817 delete storeQueue[store_idx].req;
818
819 storeQueue[store_idx].req = NULL;
820 --stores;
821
822 // Inefficient!
823 storeTail = store_idx;
824
825 decrStIdx(store_idx);
826 ++lsqSquashedStores;
827 }
828}
829
830template <class Impl>
831void
832LSQUnit<Impl>::storePostSend(PacketPtr pkt)
833{
834 if (isStalled() &&
835 storeQueue[storeWBIdx].inst->seqNum == stallingStoreIsn) {
836 DPRINTF(LSQUnit, "Unstalling, stalling store [sn:%lli] "
837 "load idx:%i\n",
838 stallingStoreIsn, stallingLoadIdx);
839 stalled = false;
840 stallingStoreIsn = 0;
841 iewStage->replayMemInst(loadQueue[stallingLoadIdx]);
842 }
843
844 if (!storeQueue[storeWBIdx].inst->isStoreConditional()) {
845 // The store is basically completed at this time. This
846 // only works so long as the checker doesn't try to
847 // verify the value in memory for stores.
848 storeQueue[storeWBIdx].inst->setCompleted();
849#if USE_CHECKER
850 if (cpu->checker) {
851 cpu->checker->verify(storeQueue[storeWBIdx].inst);
852 }
853#endif
854 }
855
856 if (pkt->result != Packet::Success) {
857 DPRINTF(LSQUnit,"D-Cache Write Miss on idx:%i!\n",
858 storeWBIdx);
859
860 DPRINTF(Activity, "Active st accessing mem miss [sn:%lli]\n",
861 storeQueue[storeWBIdx].inst->seqNum);
862
863 //mshrSeqNums.push_back(storeQueue[storeWBIdx].inst->seqNum);
864
865 //DPRINTF(LSQUnit, "Added MSHR. count = %i\n",mshrSeqNums.size());
866
867 // @todo: Increment stat here.
868 } else {
869 DPRINTF(LSQUnit,"D-Cache: Write Hit on idx:%i !\n",
870 storeWBIdx);
871
872 DPRINTF(Activity, "Active st accessing mem hit [sn:%lli]\n",
873 storeQueue[storeWBIdx].inst->seqNum);
874 }
875
876 incrStIdx(storeWBIdx);
877}
878
879template <class Impl>
880void
881LSQUnit<Impl>::writeback(DynInstPtr &inst, PacketPtr pkt)
882{
883 iewStage->wakeCPU();
884
885 // Squashed instructions do not need to complete their access.
886 if (inst->isSquashed()) {
887 iewStage->decrWb(inst->seqNum);
888 assert(!inst->isStore());
889 ++lsqIgnoredResponses;
890 return;
891 }
892
893 if (!inst->isExecuted()) {
894 inst->setExecuted();
895
896 // Complete access to copy data to proper place.
897 inst->completeAcc(pkt);
898 }
899
900 // Need to insert instruction into queue to commit
901 iewStage->instToCommit(inst);
902
903 iewStage->activityThisCycle();
904}
905
906template <class Impl>
907void
908LSQUnit<Impl>::completeStore(int store_idx)
909{
910 assert(storeQueue[store_idx].inst);
911 storeQueue[store_idx].completed = true;
912 --storesToWB;
913 // A bit conservative because a store completion may not free up entries,
914 // but hopefully avoids two store completions in one cycle from making
915 // the CPU tick twice.
916 cpu->wakeCPU();
917 cpu->activityThisCycle();
918
919 if (store_idx == storeHead) {
920 do {
921 incrStIdx(storeHead);
922
923 --stores;
924 } while (storeQueue[storeHead].completed &&
925 storeHead != storeTail);
926
927 iewStage->updateLSQNextCycle = true;
928 }
929
930 DPRINTF(LSQUnit, "Completing store [sn:%lli], idx:%i, store head "
931 "idx:%i\n",
932 storeQueue[store_idx].inst->seqNum, store_idx, storeHead);
933
934 if (isStalled() &&
935 storeQueue[store_idx].inst->seqNum == stallingStoreIsn) {
936 DPRINTF(LSQUnit, "Unstalling, stalling store [sn:%lli] "
937 "load idx:%i\n",
938 stallingStoreIsn, stallingLoadIdx);
939 stalled = false;
940 stallingStoreIsn = 0;
941 iewStage->replayMemInst(loadQueue[stallingLoadIdx]);
942 }
943
944 storeQueue[store_idx].inst->setCompleted();
945
946 // Tell the checker we've completed this instruction. Some stores
947 // may get reported twice to the checker, but the checker can
948 // handle that case.
949#if USE_CHECKER
950 if (cpu->checker) {
951 cpu->checker->verify(storeQueue[store_idx].inst);
952 }
953#endif
954}
955
956template <class Impl>
957void
958LSQUnit<Impl>::recvRetry()
959{
960 if (isStoreBlocked) {
961 assert(retryPkt != NULL);
962
963 if (dcachePort->sendTiming(retryPkt)) {
964 if (retryPkt->result == Packet::BadAddress) {
965 panic("LSQ sent out a bad address for a completed store!");
966 }
967 storePostSend(retryPkt);
968 retryPkt = NULL;
969 isStoreBlocked = false;
970 lsq->setRetryTid(-1);
971 } else {
972 // Still blocked!
973 ++lsqCacheBlocked;
974 lsq->setRetryTid(lsqID);
975 }
976 } else if (isLoadBlocked) {
977 DPRINTF(LSQUnit, "Loads squash themselves and all younger insts, "
978 "no need to resend packet.\n");
979 } else {
980 DPRINTF(LSQUnit, "Retry received but LSQ is no longer blocked.\n");
981 }
982}
983
984template <class Impl>
985inline void
986LSQUnit<Impl>::incrStIdx(int &store_idx)
987{
988 if (++store_idx >= SQEntries)
989 store_idx = 0;
990}
991
992template <class Impl>
993inline void
994LSQUnit<Impl>::decrStIdx(int &store_idx)
995{
996 if (--store_idx < 0)
997 store_idx += SQEntries;
998}
999
1000template <class Impl>
1001inline void
1002LSQUnit<Impl>::incrLdIdx(int &load_idx)
1003{
1004 if (++load_idx >= LQEntries)
1005 load_idx = 0;
1006}
1007
1008template <class Impl>
1009inline void
1010LSQUnit<Impl>::decrLdIdx(int &load_idx)
1011{
1012 if (--load_idx < 0)
1013 load_idx += LQEntries;
1014}
1015
1016template <class Impl>
1017void
1018LSQUnit<Impl>::dumpInsts()
1019{
1020 cprintf("Load store queue: Dumping instructions.\n");
1021 cprintf("Load queue size: %i\n", loads);
1022 cprintf("Load queue: ");
1023
1024 int load_idx = loadHead;
1025
1026 while (load_idx != loadTail && loadQueue[load_idx]) {
1027 cprintf("%#x ", loadQueue[load_idx]->readPC());
1028
1029 incrLdIdx(load_idx);
1030 }
1031
1032 cprintf("Store queue size: %i\n", stores);
1033 cprintf("Store queue: ");
1034
1035 int store_idx = storeHead;
1036
1037 while (store_idx != storeTail && storeQueue[store_idx].inst) {
1038 cprintf("%#x ", storeQueue[store_idx].inst->readPC());
1039
1040 incrStIdx(store_idx);
1041 }
1042
1043 cprintf("\n");
1044}
| 88 } else {
89 if (!state->noWB) {
90 writeback(inst, pkt);
91 }
92
93 if (inst->isStore()) {
94 completeStore(state->idx);
95 }
96 }
97
98 delete state;
99 delete pkt->req;
100 delete pkt;
101}
102
103template <class Impl>
104LSQUnit<Impl>::LSQUnit()
105 : loads(0), stores(0), storesToWB(0), stalled(false),
106 isStoreBlocked(false), isLoadBlocked(false),
107 loadBlockedHandled(false)
108{
109}
110
111template<class Impl>
112void
113LSQUnit<Impl>::init(Params *params, LSQ *lsq_ptr, unsigned maxLQEntries,
114 unsigned maxSQEntries, unsigned id)
115{
116// DPRINTF(LSQUnit, "Creating LSQUnit%i object.\n",id);
117
118 switchedOut = false;
119
120 lsq = lsq_ptr;
121
122 lsqID = id;
123
124 // Add 1 for the sentinel entry (they are circular queues).
125 LQEntries = maxLQEntries + 1;
126 SQEntries = maxSQEntries + 1;
127
128 loadQueue.resize(LQEntries);
129 storeQueue.resize(SQEntries);
130
131 loadHead = loadTail = 0;
132
133 storeHead = storeWBIdx = storeTail = 0;
134
135 usedPorts = 0;
136 cachePorts = params->cachePorts;
137
138 retryPkt = NULL;
139 memDepViolator = NULL;
140
141 blockedLoadSeqNum = 0;
142}
143
144template<class Impl>
145void
146LSQUnit<Impl>::setCPU(O3CPU *cpu_ptr)
147{
148 cpu = cpu_ptr;
149
150#if USE_CHECKER
151 if (cpu->checker) {
152 cpu->checker->setDcachePort(dcachePort);
153 }
154#endif
155}
156
157template<class Impl>
158std::string
159LSQUnit<Impl>::name() const
160{
161 if (Impl::MaxThreads == 1) {
162 return iewStage->name() + ".lsq";
163 } else {
164 return iewStage->name() + ".lsq.thread." + to_string(lsqID);
165 }
166}
167
168template<class Impl>
169void
170LSQUnit<Impl>::regStats()
171{
172 lsqForwLoads
173 .name(name() + ".forwLoads")
174 .desc("Number of loads that had data forwarded from stores");
175
176 invAddrLoads
177 .name(name() + ".invAddrLoads")
178 .desc("Number of loads ignored due to an invalid address");
179
180 lsqSquashedLoads
181 .name(name() + ".squashedLoads")
182 .desc("Number of loads squashed");
183
184 lsqIgnoredResponses
185 .name(name() + ".ignoredResponses")
186 .desc("Number of memory responses ignored because the instruction is squashed");
187
188 lsqMemOrderViolation
189 .name(name() + ".memOrderViolation")
190 .desc("Number of memory ordering violations");
191
192 lsqSquashedStores
193 .name(name() + ".squashedStores")
194 .desc("Number of stores squashed");
195
196 invAddrSwpfs
197 .name(name() + ".invAddrSwpfs")
198 .desc("Number of software prefetches ignored due to an invalid address");
199
200 lsqBlockedLoads
201 .name(name() + ".blockedLoads")
202 .desc("Number of blocked loads due to partial load-store forwarding");
203
204 lsqRescheduledLoads
205 .name(name() + ".rescheduledLoads")
206 .desc("Number of loads that were rescheduled");
207
208 lsqCacheBlocked
209 .name(name() + ".cacheBlocked")
210 .desc("Number of times an access to memory failed due to the cache being blocked");
211}
212
213template<class Impl>
214void
215LSQUnit<Impl>::clearLQ()
216{
217 loadQueue.clear();
218}
219
220template<class Impl>
221void
222LSQUnit<Impl>::clearSQ()
223{
224 storeQueue.clear();
225}
226
227template<class Impl>
228void
229LSQUnit<Impl>::switchOut()
230{
231 switchedOut = true;
232 for (int i = 0; i < loadQueue.size(); ++i) {
233 assert(!loadQueue[i]);
234 loadQueue[i] = NULL;
235 }
236
237 assert(storesToWB == 0);
238}
239
240template<class Impl>
241void
242LSQUnit<Impl>::takeOverFrom()
243{
244 switchedOut = false;
245 loads = stores = storesToWB = 0;
246
247 loadHead = loadTail = 0;
248
249 storeHead = storeWBIdx = storeTail = 0;
250
251 usedPorts = 0;
252
253 memDepViolator = NULL;
254
255 blockedLoadSeqNum = 0;
256
257 stalled = false;
258 isLoadBlocked = false;
259 loadBlockedHandled = false;
260}
261
262template<class Impl>
263void
264LSQUnit<Impl>::resizeLQ(unsigned size)
265{
266 unsigned size_plus_sentinel = size + 1;
267 assert(size_plus_sentinel >= LQEntries);
268
269 if (size_plus_sentinel > LQEntries) {
270 while (size_plus_sentinel > loadQueue.size()) {
271 DynInstPtr dummy;
272 loadQueue.push_back(dummy);
273 LQEntries++;
274 }
275 } else {
276 LQEntries = size_plus_sentinel;
277 }
278
279}
280
281template<class Impl>
282void
283LSQUnit<Impl>::resizeSQ(unsigned size)
284{
285 unsigned size_plus_sentinel = size + 1;
286 if (size_plus_sentinel > SQEntries) {
287 while (size_plus_sentinel > storeQueue.size()) {
288 SQEntry dummy;
289 storeQueue.push_back(dummy);
290 SQEntries++;
291 }
292 } else {
293 SQEntries = size_plus_sentinel;
294 }
295}
296
297template <class Impl>
298void
299LSQUnit<Impl>::insert(DynInstPtr &inst)
300{
301 assert(inst->isMemRef());
302
303 assert(inst->isLoad() || inst->isStore());
304
305 if (inst->isLoad()) {
306 insertLoad(inst);
307 } else {
308 insertStore(inst);
309 }
310
311 inst->setInLSQ();
312}
313
314template <class Impl>
315void
316LSQUnit<Impl>::insertLoad(DynInstPtr &load_inst)
317{
318 assert((loadTail + 1) % LQEntries != loadHead);
319 assert(loads < LQEntries);
320
321 DPRINTF(LSQUnit, "Inserting load PC %#x, idx:%i [sn:%lli]\n",
322 load_inst->readPC(), loadTail, load_inst->seqNum);
323
324 load_inst->lqIdx = loadTail;
325
326 if (stores == 0) {
327 load_inst->sqIdx = -1;
328 } else {
329 load_inst->sqIdx = storeTail;
330 }
331
332 loadQueue[loadTail] = load_inst;
333
334 incrLdIdx(loadTail);
335
336 ++loads;
337}
338
339template <class Impl>
340void
341LSQUnit<Impl>::insertStore(DynInstPtr &store_inst)
342{
343 // Make sure it is not full before inserting an instruction.
344 assert((storeTail + 1) % SQEntries != storeHead);
345 assert(stores < SQEntries);
346
347 DPRINTF(LSQUnit, "Inserting store PC %#x, idx:%i [sn:%lli]\n",
348 store_inst->readPC(), storeTail, store_inst->seqNum);
349
350 store_inst->sqIdx = storeTail;
351 store_inst->lqIdx = loadTail;
352
353 storeQueue[storeTail] = SQEntry(store_inst);
354
355 incrStIdx(storeTail);
356
357 ++stores;
358}
359
360template <class Impl>
361typename Impl::DynInstPtr
362LSQUnit<Impl>::getMemDepViolator()
363{
364 DynInstPtr temp = memDepViolator;
365
366 memDepViolator = NULL;
367
368 return temp;
369}
370
371template <class Impl>
372unsigned
373LSQUnit<Impl>::numFreeEntries()
374{
375 unsigned free_lq_entries = LQEntries - loads;
376 unsigned free_sq_entries = SQEntries - stores;
377
378 // Both the LQ and SQ entries have an extra dummy entry to differentiate
379 // empty/full conditions. Subtract 1 from the free entries.
380 if (free_lq_entries < free_sq_entries) {
381 return free_lq_entries - 1;
382 } else {
383 return free_sq_entries - 1;
384 }
385}
386
387template <class Impl>
388int
389LSQUnit<Impl>::numLoadsReady()
390{
391 int load_idx = loadHead;
392 int retval = 0;
393
394 while (load_idx != loadTail) {
395 assert(loadQueue[load_idx]);
396
397 if (loadQueue[load_idx]->readyToIssue()) {
398 ++retval;
399 }
400 }
401
402 return retval;
403}
404
405template <class Impl>
406Fault
407LSQUnit<Impl>::executeLoad(DynInstPtr &inst)
408{
409 using namespace TheISA;
410 // Execute a specific load.
411 Fault load_fault = NoFault;
412
413 DPRINTF(LSQUnit, "Executing load PC %#x, [sn:%lli]\n",
414 inst->readPC(),inst->seqNum);
415
416 assert(!inst->isSquashed());
417
418 load_fault = inst->initiateAcc();
419
420 // If the instruction faulted, then we need to send it along to commit
421 // without the instruction completing.
422 if (load_fault != NoFault) {
423 // Send this instruction to commit, also make sure iew stage
424 // realizes there is activity.
425 // Mark it as executed unless it is an uncached load that
426 // needs to hit the head of commit.
427 if (!(inst->hasRequest() && inst->uncacheable()) ||
428 inst->isAtCommit()) {
429 inst->setExecuted();
430 }
431 iewStage->instToCommit(inst);
432 iewStage->activityThisCycle();
433 } else if (!loadBlocked()) {
434 assert(inst->effAddrValid);
435 int load_idx = inst->lqIdx;
436 incrLdIdx(load_idx);
437 while (load_idx != loadTail) {
438 // Really only need to check loads that have actually executed
439
440 // @todo: For now this is extra conservative, detecting a
441 // violation if the addresses match assuming all accesses
442 // are quad word accesses.
443
444 // @todo: Fix this, magic number being used here
445 if (loadQueue[load_idx]->effAddrValid &&
446 (loadQueue[load_idx]->effAddr >> 8) ==
447 (inst->effAddr >> 8)) {
448 // A load incorrectly passed this load. Squash and refetch.
449 // For now return a fault to show that it was unsuccessful.
450 DynInstPtr violator = loadQueue[load_idx];
451 if (!memDepViolator ||
452 (violator->seqNum < memDepViolator->seqNum)) {
453 memDepViolator = violator;
454 } else {
455 break;
456 }
457
458 ++lsqMemOrderViolation;
459
460 return genMachineCheckFault();
461 }
462
463 incrLdIdx(load_idx);
464 }
465 }
466
467 return load_fault;
468}
469
470template <class Impl>
471Fault
472LSQUnit<Impl>::executeStore(DynInstPtr &store_inst)
473{
474 using namespace TheISA;
475 // Make sure that a store exists.
476 assert(stores != 0);
477
478 int store_idx = store_inst->sqIdx;
479
480 DPRINTF(LSQUnit, "Executing store PC %#x [sn:%lli]\n",
481 store_inst->readPC(), store_inst->seqNum);
482
483 assert(!store_inst->isSquashed());
484
485 // Check the recently completed loads to see if any match this store's
486 // address. If so, then we have a memory ordering violation.
487 int load_idx = store_inst->lqIdx;
488
489 Fault store_fault = store_inst->initiateAcc();
490
491 if (storeQueue[store_idx].size == 0) {
492 DPRINTF(LSQUnit,"Fault on Store PC %#x, [sn:%lli],Size = 0\n",
493 store_inst->readPC(),store_inst->seqNum);
494
495 return store_fault;
496 }
497
498 assert(store_fault == NoFault);
499
500 if (store_inst->isStoreConditional()) {
501 // Store conditionals need to set themselves as able to
502 // writeback if we haven't had a fault by here.
503 storeQueue[store_idx].canWB = true;
504
505 ++storesToWB;
506 }
507
508 assert(store_inst->effAddrValid);
509 while (load_idx != loadTail) {
510 // Really only need to check loads that have actually executed
511 // It's safe to check all loads because effAddr is set to
512 // InvalAddr when the dyn inst is created.
513
514 // @todo: For now this is extra conservative, detecting a
515 // violation if the addresses match assuming all accesses
516 // are quad word accesses.
517
518 // @todo: Fix this, magic number being used here
519 if (loadQueue[load_idx]->effAddrValid &&
520 (loadQueue[load_idx]->effAddr >> 8) ==
521 (store_inst->effAddr >> 8)) {
522 // A load incorrectly passed this store. Squash and refetch.
523 // For now return a fault to show that it was unsuccessful.
524 DynInstPtr violator = loadQueue[load_idx];
525 if (!memDepViolator ||
526 (violator->seqNum < memDepViolator->seqNum)) {
527 memDepViolator = violator;
528 } else {
529 break;
530 }
531
532 ++lsqMemOrderViolation;
533
534 return genMachineCheckFault();
535 }
536
537 incrLdIdx(load_idx);
538 }
539
540 return store_fault;
541}
542
543template <class Impl>
544void
545LSQUnit<Impl>::commitLoad()
546{
547 assert(loadQueue[loadHead]);
548
549 DPRINTF(LSQUnit, "Committing head load instruction, PC %#x\n",
550 loadQueue[loadHead]->readPC());
551
552 loadQueue[loadHead] = NULL;
553
554 incrLdIdx(loadHead);
555
556 --loads;
557}
558
559template <class Impl>
560void
561LSQUnit<Impl>::commitLoads(InstSeqNum &youngest_inst)
562{
563 assert(loads == 0 || loadQueue[loadHead]);
564
565 while (loads != 0 && loadQueue[loadHead]->seqNum <= youngest_inst) {
566 commitLoad();
567 }
568}
569
570template <class Impl>
571void
572LSQUnit<Impl>::commitStores(InstSeqNum &youngest_inst)
573{
574 assert(stores == 0 || storeQueue[storeHead].inst);
575
576 int store_idx = storeHead;
577
578 while (store_idx != storeTail) {
579 assert(storeQueue[store_idx].inst);
580 // Mark any stores that are now committed and have not yet
581 // been marked as able to write back.
582 if (!storeQueue[store_idx].canWB) {
583 if (storeQueue[store_idx].inst->seqNum > youngest_inst) {
584 break;
585 }
586 DPRINTF(LSQUnit, "Marking store as able to write back, PC "
587 "%#x [sn:%lli]\n",
588 storeQueue[store_idx].inst->readPC(),
589 storeQueue[store_idx].inst->seqNum);
590
591 storeQueue[store_idx].canWB = true;
592
593 ++storesToWB;
594 }
595
596 incrStIdx(store_idx);
597 }
598}
599
600template <class Impl>
601void
602LSQUnit<Impl>::writebackStores()
603{
604 while (storesToWB > 0 &&
605 storeWBIdx != storeTail &&
606 storeQueue[storeWBIdx].inst &&
607 storeQueue[storeWBIdx].canWB &&
608 usedPorts < cachePorts) {
609
610 if (isStoreBlocked || lsq->cacheBlocked()) {
611 DPRINTF(LSQUnit, "Unable to write back any more stores, cache"
612 " is blocked!\n");
613 break;
614 }
615
616 // Store didn't write any data so no need to write it back to
617 // memory.
618 if (storeQueue[storeWBIdx].size == 0) {
619 completeStore(storeWBIdx);
620
621 incrStIdx(storeWBIdx);
622
623 continue;
624 }
625
626 ++usedPorts;
627
628 if (storeQueue[storeWBIdx].inst->isDataPrefetch()) {
629 incrStIdx(storeWBIdx);
630
631 continue;
632 }
633
634 assert(storeQueue[storeWBIdx].req);
635 assert(!storeQueue[storeWBIdx].committed);
636
637 DynInstPtr inst = storeQueue[storeWBIdx].inst;
638
639 Request *req = storeQueue[storeWBIdx].req;
640 storeQueue[storeWBIdx].committed = true;
641
642 assert(!inst->memData);
643 inst->memData = new uint8_t[64];
644
645 TheISA::IntReg convertedData =
646 TheISA::htog(storeQueue[storeWBIdx].data);
647
648 //FIXME This is a hack to get SPARC working. It, along with endianness
649 //in the memory system in general, need to be straightened out more
650 //formally. The problem is that the data's endianness is swapped when
651 //it's in the 64 bit data field in the store queue. The data that you
652 //want won't start at the beginning of the field anymore unless it was
653 //a 64 bit access.
654 memcpy(inst->memData,
655 (uint8_t *)&convertedData +
656 (TheISA::ByteOrderDiffers ?
657 (sizeof(TheISA::IntReg) - req->getSize()) : 0),
658 req->getSize());
659
660 PacketPtr data_pkt = new Packet(req, MemCmd::WriteReq,
661 Packet::Broadcast);
662 data_pkt->dataStatic(inst->memData);
663
664 LSQSenderState *state = new LSQSenderState;
665 state->isLoad = false;
666 state->idx = storeWBIdx;
667 state->inst = inst;
668 data_pkt->senderState = state;
669
670 DPRINTF(LSQUnit, "D-Cache: Writing back store idx:%i PC:%#x "
671 "to Addr:%#x, data:%#x [sn:%lli]\n",
672 storeWBIdx, inst->readPC(),
673 req->getPaddr(), (int)*(inst->memData),
674 inst->seqNum);
675
676 // @todo: Remove this SC hack once the memory system handles it.
677 if (req->isLocked()) {
678 // Disable recording the result temporarily. Writing to
679 // misc regs normally updates the result, but this is not
680 // the desired behavior when handling store conditionals.
681 inst->recordResult = false;
682 bool success = TheISA::handleLockedWrite(inst.get(), req);
683 inst->recordResult = true;
684
685 if (!success) {
686 // Instantly complete this store.
687 DPRINTF(LSQUnit, "Store conditional [sn:%lli] failed. "
688 "Instantly completing it.\n",
689 inst->seqNum);
690 WritebackEvent *wb = new WritebackEvent(inst, data_pkt, this);
691 wb->schedule(curTick + 1);
692 delete state;
693 completeStore(storeWBIdx);
694 incrStIdx(storeWBIdx);
695 continue;
696 }
697 } else {
698 // Non-store conditionals do not need a writeback.
699 state->noWB = true;
700 }
701
702 if (!dcachePort->sendTiming(data_pkt)) {
703 if (data_pkt->result == Packet::BadAddress) {
704 panic("LSQ sent out a bad address for a completed store!");
705 }
706 // Need to handle becoming blocked on a store.
707 DPRINTF(IEW, "D-Cache became blocked when writing [sn:%lli], will"
708 "retry later\n",
709 inst->seqNum);
710 isStoreBlocked = true;
711 ++lsqCacheBlocked;
712 assert(retryPkt == NULL);
713 retryPkt = data_pkt;
714 lsq->setRetryTid(lsqID);
715 } else {
716 storePostSend(data_pkt);
717 }
718 }
719
720 // Not sure this should set it to 0.
721 usedPorts = 0;
722
723 assert(stores >= 0 && storesToWB >= 0);
724}
725
726/*template <class Impl>
727void
728LSQUnit<Impl>::removeMSHR(InstSeqNum seqNum)
729{
730 list<InstSeqNum>::iterator mshr_it = find(mshrSeqNums.begin(),
731 mshrSeqNums.end(),
732 seqNum);
733
734 if (mshr_it != mshrSeqNums.end()) {
735 mshrSeqNums.erase(mshr_it);
736 DPRINTF(LSQUnit, "Removing MSHR. count = %i\n",mshrSeqNums.size());
737 }
738}*/
739
740template <class Impl>
741void
742LSQUnit<Impl>::squash(const InstSeqNum &squashed_num)
743{
744 DPRINTF(LSQUnit, "Squashing until [sn:%lli]!"
745 "(Loads:%i Stores:%i)\n", squashed_num, loads, stores);
746
747 int load_idx = loadTail;
748 decrLdIdx(load_idx);
749
750 while (loads != 0 && loadQueue[load_idx]->seqNum > squashed_num) {
751 DPRINTF(LSQUnit,"Load Instruction PC %#x squashed, "
752 "[sn:%lli]\n",
753 loadQueue[load_idx]->readPC(),
754 loadQueue[load_idx]->seqNum);
755
756 if (isStalled() && load_idx == stallingLoadIdx) {
757 stalled = false;
758 stallingStoreIsn = 0;
759 stallingLoadIdx = 0;
760 }
761
762 // Clear the smart pointer to make sure it is decremented.
763 loadQueue[load_idx]->setSquashed();
764 loadQueue[load_idx] = NULL;
765 --loads;
766
767 // Inefficient!
768 loadTail = load_idx;
769
770 decrLdIdx(load_idx);
771 ++lsqSquashedLoads;
772 }
773
774 if (isLoadBlocked) {
775 if (squashed_num < blockedLoadSeqNum) {
776 isLoadBlocked = false;
777 loadBlockedHandled = false;
778 blockedLoadSeqNum = 0;
779 }
780 }
781
782 if (memDepViolator && squashed_num < memDepViolator->seqNum) {
783 memDepViolator = NULL;
784 }
785
786 int store_idx = storeTail;
787 decrStIdx(store_idx);
788
789 while (stores != 0 &&
790 storeQueue[store_idx].inst->seqNum > squashed_num) {
791 // Instructions marked as can WB are already committed.
792 if (storeQueue[store_idx].canWB) {
793 break;
794 }
795
796 DPRINTF(LSQUnit,"Store Instruction PC %#x squashed, "
797 "idx:%i [sn:%lli]\n",
798 storeQueue[store_idx].inst->readPC(),
799 store_idx, storeQueue[store_idx].inst->seqNum);
800
801 // I don't think this can happen. It should have been cleared
802 // by the stalling load.
803 if (isStalled() &&
804 storeQueue[store_idx].inst->seqNum == stallingStoreIsn) {
805 panic("Is stalled should have been cleared by stalling load!\n");
806 stalled = false;
807 stallingStoreIsn = 0;
808 }
809
810 // Clear the smart pointer to make sure it is decremented.
811 storeQueue[store_idx].inst->setSquashed();
812 storeQueue[store_idx].inst = NULL;
813 storeQueue[store_idx].canWB = 0;
814
815 // Must delete request now that it wasn't handed off to
816 // memory. This is quite ugly. @todo: Figure out the proper
817 // place to really handle request deletes.
818 delete storeQueue[store_idx].req;
819
820 storeQueue[store_idx].req = NULL;
821 --stores;
822
823 // Inefficient!
824 storeTail = store_idx;
825
826 decrStIdx(store_idx);
827 ++lsqSquashedStores;
828 }
829}
830
831template <class Impl>
832void
833LSQUnit<Impl>::storePostSend(PacketPtr pkt)
834{
835 if (isStalled() &&
836 storeQueue[storeWBIdx].inst->seqNum == stallingStoreIsn) {
837 DPRINTF(LSQUnit, "Unstalling, stalling store [sn:%lli] "
838 "load idx:%i\n",
839 stallingStoreIsn, stallingLoadIdx);
840 stalled = false;
841 stallingStoreIsn = 0;
842 iewStage->replayMemInst(loadQueue[stallingLoadIdx]);
843 }
844
845 if (!storeQueue[storeWBIdx].inst->isStoreConditional()) {
846 // The store is basically completed at this time. This
847 // only works so long as the checker doesn't try to
848 // verify the value in memory for stores.
849 storeQueue[storeWBIdx].inst->setCompleted();
850#if USE_CHECKER
851 if (cpu->checker) {
852 cpu->checker->verify(storeQueue[storeWBIdx].inst);
853 }
854#endif
855 }
856
857 if (pkt->result != Packet::Success) {
858 DPRINTF(LSQUnit,"D-Cache Write Miss on idx:%i!\n",
859 storeWBIdx);
860
861 DPRINTF(Activity, "Active st accessing mem miss [sn:%lli]\n",
862 storeQueue[storeWBIdx].inst->seqNum);
863
864 //mshrSeqNums.push_back(storeQueue[storeWBIdx].inst->seqNum);
865
866 //DPRINTF(LSQUnit, "Added MSHR. count = %i\n",mshrSeqNums.size());
867
868 // @todo: Increment stat here.
869 } else {
870 DPRINTF(LSQUnit,"D-Cache: Write Hit on idx:%i !\n",
871 storeWBIdx);
872
873 DPRINTF(Activity, "Active st accessing mem hit [sn:%lli]\n",
874 storeQueue[storeWBIdx].inst->seqNum);
875 }
876
877 incrStIdx(storeWBIdx);
878}
879
880template <class Impl>
881void
882LSQUnit<Impl>::writeback(DynInstPtr &inst, PacketPtr pkt)
883{
884 iewStage->wakeCPU();
885
886 // Squashed instructions do not need to complete their access.
887 if (inst->isSquashed()) {
888 iewStage->decrWb(inst->seqNum);
889 assert(!inst->isStore());
890 ++lsqIgnoredResponses;
891 return;
892 }
893
894 if (!inst->isExecuted()) {
895 inst->setExecuted();
896
897 // Complete access to copy data to proper place.
898 inst->completeAcc(pkt);
899 }
900
901 // Need to insert instruction into queue to commit
902 iewStage->instToCommit(inst);
903
904 iewStage->activityThisCycle();
905}
906
907template <class Impl>
908void
909LSQUnit<Impl>::completeStore(int store_idx)
910{
911 assert(storeQueue[store_idx].inst);
912 storeQueue[store_idx].completed = true;
913 --storesToWB;
914 // A bit conservative because a store completion may not free up entries,
915 // but hopefully avoids two store completions in one cycle from making
916 // the CPU tick twice.
917 cpu->wakeCPU();
918 cpu->activityThisCycle();
919
920 if (store_idx == storeHead) {
921 do {
922 incrStIdx(storeHead);
923
924 --stores;
925 } while (storeQueue[storeHead].completed &&
926 storeHead != storeTail);
927
928 iewStage->updateLSQNextCycle = true;
929 }
930
931 DPRINTF(LSQUnit, "Completing store [sn:%lli], idx:%i, store head "
932 "idx:%i\n",
933 storeQueue[store_idx].inst->seqNum, store_idx, storeHead);
934
935 if (isStalled() &&
936 storeQueue[store_idx].inst->seqNum == stallingStoreIsn) {
937 DPRINTF(LSQUnit, "Unstalling, stalling store [sn:%lli] "
938 "load idx:%i\n",
939 stallingStoreIsn, stallingLoadIdx);
940 stalled = false;
941 stallingStoreIsn = 0;
942 iewStage->replayMemInst(loadQueue[stallingLoadIdx]);
943 }
944
945 storeQueue[store_idx].inst->setCompleted();
946
947 // Tell the checker we've completed this instruction. Some stores
948 // may get reported twice to the checker, but the checker can
949 // handle that case.
950#if USE_CHECKER
951 if (cpu->checker) {
952 cpu->checker->verify(storeQueue[store_idx].inst);
953 }
954#endif
955}
956
957template <class Impl>
958void
959LSQUnit<Impl>::recvRetry()
960{
961 if (isStoreBlocked) {
962 assert(retryPkt != NULL);
963
964 if (dcachePort->sendTiming(retryPkt)) {
965 if (retryPkt->result == Packet::BadAddress) {
966 panic("LSQ sent out a bad address for a completed store!");
967 }
968 storePostSend(retryPkt);
969 retryPkt = NULL;
970 isStoreBlocked = false;
971 lsq->setRetryTid(-1);
972 } else {
973 // Still blocked!
974 ++lsqCacheBlocked;
975 lsq->setRetryTid(lsqID);
976 }
977 } else if (isLoadBlocked) {
978 DPRINTF(LSQUnit, "Loads squash themselves and all younger insts, "
979 "no need to resend packet.\n");
980 } else {
981 DPRINTF(LSQUnit, "Retry received but LSQ is no longer blocked.\n");
982 }
983}
984
985template <class Impl>
986inline void
987LSQUnit<Impl>::incrStIdx(int &store_idx)
988{
989 if (++store_idx >= SQEntries)
990 store_idx = 0;
991}
992
993template <class Impl>
994inline void
995LSQUnit<Impl>::decrStIdx(int &store_idx)
996{
997 if (--store_idx < 0)
998 store_idx += SQEntries;
999}
1000
1001template <class Impl>
1002inline void
1003LSQUnit<Impl>::incrLdIdx(int &load_idx)
1004{
1005 if (++load_idx >= LQEntries)
1006 load_idx = 0;
1007}
1008
1009template <class Impl>
1010inline void
1011LSQUnit<Impl>::decrLdIdx(int &load_idx)
1012{
1013 if (--load_idx < 0)
1014 load_idx += LQEntries;
1015}
1016
1017template <class Impl>
1018void
1019LSQUnit<Impl>::dumpInsts()
1020{
1021 cprintf("Load store queue: Dumping instructions.\n");
1022 cprintf("Load queue size: %i\n", loads);
1023 cprintf("Load queue: ");
1024
1025 int load_idx = loadHead;
1026
1027 while (load_idx != loadTail && loadQueue[load_idx]) {
1028 cprintf("%#x ", loadQueue[load_idx]->readPC());
1029
1030 incrLdIdx(load_idx);
1031 }
1032
1033 cprintf("Store queue size: %i\n", stores);
1034 cprintf("Store queue: ");
1035
1036 int store_idx = storeHead;
1037
1038 while (store_idx != storeTail && storeQueue[store_idx].inst) {
1039 cprintf("%#x ", storeQueue[store_idx].inst->readPC());
1040
1041 incrStIdx(store_idx);
1042 }
1043
1044 cprintf("\n");
1045}
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