1/*
2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Kevin Lim
29 * Korey Sewell
30 */
31
32#include "arch/locked_mem.hh"
33#include "config/use_checker.hh"
34
35#include "cpu/o3/lsq.hh"
36#include "cpu/o3/lsq_unit.hh"
37#include "base/str.hh"
38#include "mem/packet.hh"
39#include "mem/request.hh"
40
41#if USE_CHECKER
42#include "cpu/checker/cpu.hh"
43#endif
44
45template<class Impl>
46LSQUnit<Impl>::WritebackEvent::WritebackEvent(DynInstPtr &_inst, PacketPtr _pkt,
47 LSQUnit *lsq_ptr)
48 : Event(&mainEventQueue), inst(_inst), pkt(_pkt), lsqPtr(lsq_ptr)
49{
50 this->setFlags(Event::AutoDelete);
51}
52
53template<class Impl>
54void
55LSQUnit<Impl>::WritebackEvent::process()
56{
57 if (!lsqPtr->isSwitchedOut()) {
58 lsqPtr->writeback(inst, pkt);
59 }
60 delete pkt;
61}
62
63template<class Impl>
64const char *
65LSQUnit<Impl>::WritebackEvent::description()
66{
67 return "Store writeback event";
68}
69
70template<class Impl>
71void
72LSQUnit<Impl>::completeDataAccess(PacketPtr pkt)
73{
74 LSQSenderState *state = dynamic_cast<LSQSenderState *>(pkt->senderState);
75 DynInstPtr inst = state->inst;
76 DPRINTF(IEW, "Writeback event [sn:%lli]\n", inst->seqNum);
77 DPRINTF(Activity, "Activity: Writeback event [sn:%lli]\n", inst->seqNum);
78
79 //iewStage->ldstQueue.removeMSHR(inst->threadNumber,inst->seqNum);
80
81 if (isSwitchedOut() || inst->isSquashed()) {
82 iewStage->decrWb(inst->seqNum);
83 delete state;
84 delete pkt;
85 return;
86 } else {
87 if (!state->noWB) {
88 writeback(inst, pkt);
89 }
90
91 if (inst->isStore()) {
92 completeStore(state->idx);
93 }
94 }
95
96 delete state;
97 delete pkt;
98}
99
100template <class Impl>
101LSQUnit<Impl>::LSQUnit()
102 : loads(0), stores(0), storesToWB(0), stalled(false),
103 isStoreBlocked(false), isLoadBlocked(false),
104 loadBlockedHandled(false)
105{
106}
107
108template<class Impl>
109void
110LSQUnit<Impl>::init(Params *params, LSQ *lsq_ptr, unsigned maxLQEntries,
111 unsigned maxSQEntries, unsigned id)
112{
113 DPRINTF(LSQUnit, "Creating LSQUnit%i object.\n",id);
114
115 switchedOut = false;
116
117 lsq = lsq_ptr;
118
119 lsqID = id;
120
121 // Add 1 for the sentinel entry (they are circular queues).
122 LQEntries = maxLQEntries + 1;
123 SQEntries = maxSQEntries + 1;
124
125 loadQueue.resize(LQEntries);
126 storeQueue.resize(SQEntries);
127
128 loadHead = loadTail = 0;
129
130 storeHead = storeWBIdx = storeTail = 0;
131
132 usedPorts = 0;
133 cachePorts = params->cachePorts;
134
135 retryPkt = NULL;
136 memDepViolator = NULL;
137
138 blockedLoadSeqNum = 0;
139}
140
141template<class Impl>
142void
143LSQUnit<Impl>::setCPU(O3CPU *cpu_ptr)
144{
145 cpu = cpu_ptr;
146
147#if USE_CHECKER
148 if (cpu->checker) {
149 cpu->checker->setDcachePort(dcachePort);
150 }
151#endif
152}
153
154template<class Impl>
155std::string
156LSQUnit<Impl>::name() const
157{
158 if (Impl::MaxThreads == 1) {
159 return iewStage->name() + ".lsq";
160 } else {
161 return iewStage->name() + ".lsq.thread." + to_string(lsqID);
162 }
163}
164
165template<class Impl>
166void
167LSQUnit<Impl>::regStats()
168{
169 lsqForwLoads
170 .name(name() + ".forwLoads")
171 .desc("Number of loads that had data forwarded from stores");
172
173 invAddrLoads
174 .name(name() + ".invAddrLoads")
175 .desc("Number of loads ignored due to an invalid address");
176
177 lsqSquashedLoads
178 .name(name() + ".squashedLoads")
179 .desc("Number of loads squashed");
180
181 lsqIgnoredResponses
182 .name(name() + ".ignoredResponses")
183 .desc("Number of memory responses ignored because the instruction is squashed");
184
185 lsqMemOrderViolation
186 .name(name() + ".memOrderViolation")
187 .desc("Number of memory ordering violations");
188
189 lsqSquashedStores
190 .name(name() + ".squashedStores")
191 .desc("Number of stores squashed");
192
193 invAddrSwpfs
194 .name(name() + ".invAddrSwpfs")
195 .desc("Number of software prefetches ignored due to an invalid address");
196
197 lsqBlockedLoads
198 .name(name() + ".blockedLoads")
199 .desc("Number of blocked loads due to partial load-store forwarding");
200
201 lsqRescheduledLoads
202 .name(name() + ".rescheduledLoads")
203 .desc("Number of loads that were rescheduled");
204
205 lsqCacheBlocked
206 .name(name() + ".cacheBlocked")
207 .desc("Number of times an access to memory failed due to the cache being blocked");
208}
209
210template<class Impl>
211void
212LSQUnit<Impl>::clearLQ()
213{
214 loadQueue.clear();
215}
216
217template<class Impl>
218void
219LSQUnit<Impl>::clearSQ()
220{
221 storeQueue.clear();
222}
223
224template<class Impl>
225void
226LSQUnit<Impl>::switchOut()
227{
228 switchedOut = true;
229 for (int i = 0; i < loadQueue.size(); ++i) {
230 assert(!loadQueue[i]);
231 loadQueue[i] = NULL;
232 }
233
234 assert(storesToWB == 0);
235}
236
237template<class Impl>
238void
239LSQUnit<Impl>::takeOverFrom()
240{
241 switchedOut = false;
242 loads = stores = storesToWB = 0;
243
244 loadHead = loadTail = 0;
245
246 storeHead = storeWBIdx = storeTail = 0;
247
248 usedPorts = 0;
249
250 memDepViolator = NULL;
251
252 blockedLoadSeqNum = 0;
253
254 stalled = false;
255 isLoadBlocked = false;
256 loadBlockedHandled = false;
257}
258
259template<class Impl>
260void
261LSQUnit<Impl>::resizeLQ(unsigned size)
262{
263 unsigned size_plus_sentinel = size + 1;
264 assert(size_plus_sentinel >= LQEntries);
265
266 if (size_plus_sentinel > LQEntries) {
267 while (size_plus_sentinel > loadQueue.size()) {
268 DynInstPtr dummy;
269 loadQueue.push_back(dummy);
270 LQEntries++;
271 }
272 } else {
273 LQEntries = size_plus_sentinel;
274 }
275
276}
277
278template<class Impl>
279void
280LSQUnit<Impl>::resizeSQ(unsigned size)
281{
282 unsigned size_plus_sentinel = size + 1;
283 if (size_plus_sentinel > SQEntries) {
284 while (size_plus_sentinel > storeQueue.size()) {
285 SQEntry dummy;
286 storeQueue.push_back(dummy);
287 SQEntries++;
288 }
289 } else {
290 SQEntries = size_plus_sentinel;
291 }
292}
293
294template <class Impl>
295void
296LSQUnit<Impl>::insert(DynInstPtr &inst)
297{
298 assert(inst->isMemRef());
299
300 assert(inst->isLoad() || inst->isStore());
301
302 if (inst->isLoad()) {
303 insertLoad(inst);
304 } else {
305 insertStore(inst);
306 }
307
308 inst->setInLSQ();
309}
310
311template <class Impl>
312void
313LSQUnit<Impl>::insertLoad(DynInstPtr &load_inst)
314{
315 assert((loadTail + 1) % LQEntries != loadHead);
316 assert(loads < LQEntries);
317
318 DPRINTF(LSQUnit, "Inserting load PC %#x, idx:%i [sn:%lli]\n",
319 load_inst->readPC(), loadTail, load_inst->seqNum);
320
321 load_inst->lqIdx = loadTail;
322
323 if (stores == 0) {
324 load_inst->sqIdx = -1;
325 } else {
326 load_inst->sqIdx = storeTail;
327 }
328
329 loadQueue[loadTail] = load_inst;
330
331 incrLdIdx(loadTail);
332
333 ++loads;
334}
335
336template <class Impl>
337void
338LSQUnit<Impl>::insertStore(DynInstPtr &store_inst)
339{
340 // Make sure it is not full before inserting an instruction.
341 assert((storeTail + 1) % SQEntries != storeHead);
342 assert(stores < SQEntries);
343
344 DPRINTF(LSQUnit, "Inserting store PC %#x, idx:%i [sn:%lli]\n",
345 store_inst->readPC(), storeTail, store_inst->seqNum);
346
347 store_inst->sqIdx = storeTail;
348 store_inst->lqIdx = loadTail;
349
350 storeQueue[storeTail] = SQEntry(store_inst);
351
352 incrStIdx(storeTail);
353
354 ++stores;
355}
356
357template <class Impl>
358typename Impl::DynInstPtr
359LSQUnit<Impl>::getMemDepViolator()
360{
361 DynInstPtr temp = memDepViolator;
362
363 memDepViolator = NULL;
364
365 return temp;
366}
367
368template <class Impl>
369unsigned
370LSQUnit<Impl>::numFreeEntries()
371{
372 unsigned free_lq_entries = LQEntries - loads;
373 unsigned free_sq_entries = SQEntries - stores;
374
375 // Both the LQ and SQ entries have an extra dummy entry to differentiate
376 // empty/full conditions. Subtract 1 from the free entries.
377 if (free_lq_entries < free_sq_entries) {
378 return free_lq_entries - 1;
379 } else {
380 return free_sq_entries - 1;
381 }
382}
383
384template <class Impl>
385int
386LSQUnit<Impl>::numLoadsReady()
387{
388 int load_idx = loadHead;
389 int retval = 0;
390
391 while (load_idx != loadTail) {
392 assert(loadQueue[load_idx]);
393
394 if (loadQueue[load_idx]->readyToIssue()) {
395 ++retval;
396 }
397 }
398
399 return retval;
400}
401
402template <class Impl>
403Fault
404LSQUnit<Impl>::executeLoad(DynInstPtr &inst)
405{
406 // Execute a specific load.
407 Fault load_fault = NoFault;
408
409 DPRINTF(LSQUnit, "Executing load PC %#x, [sn:%lli]\n",
410 inst->readPC(),inst->seqNum);
411
412 load_fault = inst->initiateAcc();
413
414 // If the instruction faulted, then we need to send it along to commit
415 // without the instruction completing.
416 if (load_fault != NoFault) {
417 // Send this instruction to commit, also make sure iew stage
418 // realizes there is activity.
419 // Mark it as executed unless it is an uncached load that
420 // needs to hit the head of commit.
421 if (!(inst->req && inst->req->isUncacheable()) ||
422 inst->isAtCommit()) {
423 inst->setExecuted();
424 }
425 iewStage->instToCommit(inst);
426 iewStage->activityThisCycle();
427 }
428
429 return load_fault;
430}
431
432template <class Impl>
433Fault
434LSQUnit<Impl>::executeStore(DynInstPtr &store_inst)
435{
436 using namespace TheISA;
437 // Make sure that a store exists.
438 assert(stores != 0);
439
440 int store_idx = store_inst->sqIdx;
441
442 DPRINTF(LSQUnit, "Executing store PC %#x [sn:%lli]\n",
443 store_inst->readPC(), store_inst->seqNum);
444
445 // Check the recently completed loads to see if any match this store's
446 // address. If so, then we have a memory ordering violation.
447 int load_idx = store_inst->lqIdx;
448
449 Fault store_fault = store_inst->initiateAcc();
450
451 if (storeQueue[store_idx].size == 0) {
452 DPRINTF(LSQUnit,"Fault on Store PC %#x, [sn:%lli],Size = 0\n",
453 store_inst->readPC(),store_inst->seqNum);
454
455 return store_fault;
456 }
457
458 assert(store_fault == NoFault);
459
460 if (store_inst->isStoreConditional()) {
461 // Store conditionals need to set themselves as able to
462 // writeback if we haven't had a fault by here.
463 storeQueue[store_idx].canWB = true;
464
465 ++storesToWB;
466 }
467
468 if (!memDepViolator) {
469 while (load_idx != loadTail) {
470 // Really only need to check loads that have actually executed
471 // It's safe to check all loads because effAddr is set to
472 // InvalAddr when the dyn inst is created.
473
474 // @todo: For now this is extra conservative, detecting a
475 // violation if the addresses match assuming all accesses
476 // are quad word accesses.
477
478 // @todo: Fix this, magic number being used here
479 if ((loadQueue[load_idx]->effAddr >> 8) ==
480 (store_inst->effAddr >> 8)) {
481 // A load incorrectly passed this store. Squash and refetch.
482 // For now return a fault to show that it was unsuccessful.
483 memDepViolator = loadQueue[load_idx];
484 ++lsqMemOrderViolation;
485
486 return genMachineCheckFault();
487 }
488
489 incrLdIdx(load_idx);
490 }
491
492 // If we've reached this point, there was no violation.
493 memDepViolator = NULL;
494 }
495
496 return store_fault;
497}
498
499template <class Impl>
500void
501LSQUnit<Impl>::commitLoad()
502{
503 assert(loadQueue[loadHead]);
504
505 DPRINTF(LSQUnit, "Committing head load instruction, PC %#x\n",
506 loadQueue[loadHead]->readPC());
507
508 loadQueue[loadHead] = NULL;
509
510 incrLdIdx(loadHead);
511
512 --loads;
513}
514
515template <class Impl>
516void
517LSQUnit<Impl>::commitLoads(InstSeqNum &youngest_inst)
518{
519 assert(loads == 0 || loadQueue[loadHead]);
520
521 while (loads != 0 && loadQueue[loadHead]->seqNum <= youngest_inst) {
522 commitLoad();
523 }
524}
525
526template <class Impl>
527void
528LSQUnit<Impl>::commitStores(InstSeqNum &youngest_inst)
529{
530 assert(stores == 0 || storeQueue[storeHead].inst);
531
532 int store_idx = storeHead;
533
534 while (store_idx != storeTail) {
535 assert(storeQueue[store_idx].inst);
536 // Mark any stores that are now committed and have not yet
537 // been marked as able to write back.
538 if (!storeQueue[store_idx].canWB) {
539 if (storeQueue[store_idx].inst->seqNum > youngest_inst) {
540 break;
541 }
542 DPRINTF(LSQUnit, "Marking store as able to write back, PC "
543 "%#x [sn:%lli]\n",
544 storeQueue[store_idx].inst->readPC(),
545 storeQueue[store_idx].inst->seqNum);
546
547 storeQueue[store_idx].canWB = true;
548
549 ++storesToWB;
550 }
551
552 incrStIdx(store_idx);
553 }
554}
555
556template <class Impl>
557void
558LSQUnit<Impl>::writebackStores()
559{
560 while (storesToWB > 0 &&
561 storeWBIdx != storeTail &&
562 storeQueue[storeWBIdx].inst &&
563 storeQueue[storeWBIdx].canWB &&
564 usedPorts < cachePorts) {
565
566 if (isStoreBlocked || lsq->cacheBlocked()) {
567 DPRINTF(LSQUnit, "Unable to write back any more stores, cache"
568 " is blocked!\n");
569 break;
570 }
571
572 // Store didn't write any data so no need to write it back to
573 // memory.
574 if (storeQueue[storeWBIdx].size == 0) {
575 completeStore(storeWBIdx);
576
577 incrStIdx(storeWBIdx);
578
579 continue;
580 }
581
582 ++usedPorts;
583
584 if (storeQueue[storeWBIdx].inst->isDataPrefetch()) {
585 incrStIdx(storeWBIdx);
586
587 continue;
588 }
589
590 assert(storeQueue[storeWBIdx].req);
591 assert(!storeQueue[storeWBIdx].committed);
592
593 DynInstPtr inst = storeQueue[storeWBIdx].inst;
594
595 Request *req = storeQueue[storeWBIdx].req;
596 storeQueue[storeWBIdx].committed = true;
597
598 assert(!inst->memData);
599 inst->memData = new uint8_t[64];
600
601 TheISA::IntReg convertedData =
602 TheISA::htog(storeQueue[storeWBIdx].data);
603
604 //FIXME This is a hack to get SPARC working. It, along with endianness
605 //in the memory system in general, need to be straightened out more
606 //formally. The problem is that the data's endianness is swapped when
607 //it's in the 64 bit data field in the store queue. The data that you
608 //want won't start at the beginning of the field anymore unless it was
609 //a 64 bit access.
610 memcpy(inst->memData,
611 (uint8_t *)&convertedData +
612 (TheISA::ByteOrderDiffers ?
613 (sizeof(TheISA::IntReg) - req->getSize()) : 0),
614 req->getSize());
615
| 1/*
2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Kevin Lim
29 * Korey Sewell
30 */
31
32#include "arch/locked_mem.hh"
33#include "config/use_checker.hh"
34
35#include "cpu/o3/lsq.hh"
36#include "cpu/o3/lsq_unit.hh"
37#include "base/str.hh"
38#include "mem/packet.hh"
39#include "mem/request.hh"
40
41#if USE_CHECKER
42#include "cpu/checker/cpu.hh"
43#endif
44
45template<class Impl>
46LSQUnit<Impl>::WritebackEvent::WritebackEvent(DynInstPtr &_inst, PacketPtr _pkt,
47 LSQUnit *lsq_ptr)
48 : Event(&mainEventQueue), inst(_inst), pkt(_pkt), lsqPtr(lsq_ptr)
49{
50 this->setFlags(Event::AutoDelete);
51}
52
53template<class Impl>
54void
55LSQUnit<Impl>::WritebackEvent::process()
56{
57 if (!lsqPtr->isSwitchedOut()) {
58 lsqPtr->writeback(inst, pkt);
59 }
60 delete pkt;
61}
62
63template<class Impl>
64const char *
65LSQUnit<Impl>::WritebackEvent::description()
66{
67 return "Store writeback event";
68}
69
70template<class Impl>
71void
72LSQUnit<Impl>::completeDataAccess(PacketPtr pkt)
73{
74 LSQSenderState *state = dynamic_cast<LSQSenderState *>(pkt->senderState);
75 DynInstPtr inst = state->inst;
76 DPRINTF(IEW, "Writeback event [sn:%lli]\n", inst->seqNum);
77 DPRINTF(Activity, "Activity: Writeback event [sn:%lli]\n", inst->seqNum);
78
79 //iewStage->ldstQueue.removeMSHR(inst->threadNumber,inst->seqNum);
80
81 if (isSwitchedOut() || inst->isSquashed()) {
82 iewStage->decrWb(inst->seqNum);
83 delete state;
84 delete pkt;
85 return;
86 } else {
87 if (!state->noWB) {
88 writeback(inst, pkt);
89 }
90
91 if (inst->isStore()) {
92 completeStore(state->idx);
93 }
94 }
95
96 delete state;
97 delete pkt;
98}
99
100template <class Impl>
101LSQUnit<Impl>::LSQUnit()
102 : loads(0), stores(0), storesToWB(0), stalled(false),
103 isStoreBlocked(false), isLoadBlocked(false),
104 loadBlockedHandled(false)
105{
106}
107
108template<class Impl>
109void
110LSQUnit<Impl>::init(Params *params, LSQ *lsq_ptr, unsigned maxLQEntries,
111 unsigned maxSQEntries, unsigned id)
112{
113 DPRINTF(LSQUnit, "Creating LSQUnit%i object.\n",id);
114
115 switchedOut = false;
116
117 lsq = lsq_ptr;
118
119 lsqID = id;
120
121 // Add 1 for the sentinel entry (they are circular queues).
122 LQEntries = maxLQEntries + 1;
123 SQEntries = maxSQEntries + 1;
124
125 loadQueue.resize(LQEntries);
126 storeQueue.resize(SQEntries);
127
128 loadHead = loadTail = 0;
129
130 storeHead = storeWBIdx = storeTail = 0;
131
132 usedPorts = 0;
133 cachePorts = params->cachePorts;
134
135 retryPkt = NULL;
136 memDepViolator = NULL;
137
138 blockedLoadSeqNum = 0;
139}
140
141template<class Impl>
142void
143LSQUnit<Impl>::setCPU(O3CPU *cpu_ptr)
144{
145 cpu = cpu_ptr;
146
147#if USE_CHECKER
148 if (cpu->checker) {
149 cpu->checker->setDcachePort(dcachePort);
150 }
151#endif
152}
153
154template<class Impl>
155std::string
156LSQUnit<Impl>::name() const
157{
158 if (Impl::MaxThreads == 1) {
159 return iewStage->name() + ".lsq";
160 } else {
161 return iewStage->name() + ".lsq.thread." + to_string(lsqID);
162 }
163}
164
165template<class Impl>
166void
167LSQUnit<Impl>::regStats()
168{
169 lsqForwLoads
170 .name(name() + ".forwLoads")
171 .desc("Number of loads that had data forwarded from stores");
172
173 invAddrLoads
174 .name(name() + ".invAddrLoads")
175 .desc("Number of loads ignored due to an invalid address");
176
177 lsqSquashedLoads
178 .name(name() + ".squashedLoads")
179 .desc("Number of loads squashed");
180
181 lsqIgnoredResponses
182 .name(name() + ".ignoredResponses")
183 .desc("Number of memory responses ignored because the instruction is squashed");
184
185 lsqMemOrderViolation
186 .name(name() + ".memOrderViolation")
187 .desc("Number of memory ordering violations");
188
189 lsqSquashedStores
190 .name(name() + ".squashedStores")
191 .desc("Number of stores squashed");
192
193 invAddrSwpfs
194 .name(name() + ".invAddrSwpfs")
195 .desc("Number of software prefetches ignored due to an invalid address");
196
197 lsqBlockedLoads
198 .name(name() + ".blockedLoads")
199 .desc("Number of blocked loads due to partial load-store forwarding");
200
201 lsqRescheduledLoads
202 .name(name() + ".rescheduledLoads")
203 .desc("Number of loads that were rescheduled");
204
205 lsqCacheBlocked
206 .name(name() + ".cacheBlocked")
207 .desc("Number of times an access to memory failed due to the cache being blocked");
208}
209
210template<class Impl>
211void
212LSQUnit<Impl>::clearLQ()
213{
214 loadQueue.clear();
215}
216
217template<class Impl>
218void
219LSQUnit<Impl>::clearSQ()
220{
221 storeQueue.clear();
222}
223
224template<class Impl>
225void
226LSQUnit<Impl>::switchOut()
227{
228 switchedOut = true;
229 for (int i = 0; i < loadQueue.size(); ++i) {
230 assert(!loadQueue[i]);
231 loadQueue[i] = NULL;
232 }
233
234 assert(storesToWB == 0);
235}
236
237template<class Impl>
238void
239LSQUnit<Impl>::takeOverFrom()
240{
241 switchedOut = false;
242 loads = stores = storesToWB = 0;
243
244 loadHead = loadTail = 0;
245
246 storeHead = storeWBIdx = storeTail = 0;
247
248 usedPorts = 0;
249
250 memDepViolator = NULL;
251
252 blockedLoadSeqNum = 0;
253
254 stalled = false;
255 isLoadBlocked = false;
256 loadBlockedHandled = false;
257}
258
259template<class Impl>
260void
261LSQUnit<Impl>::resizeLQ(unsigned size)
262{
263 unsigned size_plus_sentinel = size + 1;
264 assert(size_plus_sentinel >= LQEntries);
265
266 if (size_plus_sentinel > LQEntries) {
267 while (size_plus_sentinel > loadQueue.size()) {
268 DynInstPtr dummy;
269 loadQueue.push_back(dummy);
270 LQEntries++;
271 }
272 } else {
273 LQEntries = size_plus_sentinel;
274 }
275
276}
277
278template<class Impl>
279void
280LSQUnit<Impl>::resizeSQ(unsigned size)
281{
282 unsigned size_plus_sentinel = size + 1;
283 if (size_plus_sentinel > SQEntries) {
284 while (size_plus_sentinel > storeQueue.size()) {
285 SQEntry dummy;
286 storeQueue.push_back(dummy);
287 SQEntries++;
288 }
289 } else {
290 SQEntries = size_plus_sentinel;
291 }
292}
293
294template <class Impl>
295void
296LSQUnit<Impl>::insert(DynInstPtr &inst)
297{
298 assert(inst->isMemRef());
299
300 assert(inst->isLoad() || inst->isStore());
301
302 if (inst->isLoad()) {
303 insertLoad(inst);
304 } else {
305 insertStore(inst);
306 }
307
308 inst->setInLSQ();
309}
310
311template <class Impl>
312void
313LSQUnit<Impl>::insertLoad(DynInstPtr &load_inst)
314{
315 assert((loadTail + 1) % LQEntries != loadHead);
316 assert(loads < LQEntries);
317
318 DPRINTF(LSQUnit, "Inserting load PC %#x, idx:%i [sn:%lli]\n",
319 load_inst->readPC(), loadTail, load_inst->seqNum);
320
321 load_inst->lqIdx = loadTail;
322
323 if (stores == 0) {
324 load_inst->sqIdx = -1;
325 } else {
326 load_inst->sqIdx = storeTail;
327 }
328
329 loadQueue[loadTail] = load_inst;
330
331 incrLdIdx(loadTail);
332
333 ++loads;
334}
335
336template <class Impl>
337void
338LSQUnit<Impl>::insertStore(DynInstPtr &store_inst)
339{
340 // Make sure it is not full before inserting an instruction.
341 assert((storeTail + 1) % SQEntries != storeHead);
342 assert(stores < SQEntries);
343
344 DPRINTF(LSQUnit, "Inserting store PC %#x, idx:%i [sn:%lli]\n",
345 store_inst->readPC(), storeTail, store_inst->seqNum);
346
347 store_inst->sqIdx = storeTail;
348 store_inst->lqIdx = loadTail;
349
350 storeQueue[storeTail] = SQEntry(store_inst);
351
352 incrStIdx(storeTail);
353
354 ++stores;
355}
356
357template <class Impl>
358typename Impl::DynInstPtr
359LSQUnit<Impl>::getMemDepViolator()
360{
361 DynInstPtr temp = memDepViolator;
362
363 memDepViolator = NULL;
364
365 return temp;
366}
367
368template <class Impl>
369unsigned
370LSQUnit<Impl>::numFreeEntries()
371{
372 unsigned free_lq_entries = LQEntries - loads;
373 unsigned free_sq_entries = SQEntries - stores;
374
375 // Both the LQ and SQ entries have an extra dummy entry to differentiate
376 // empty/full conditions. Subtract 1 from the free entries.
377 if (free_lq_entries < free_sq_entries) {
378 return free_lq_entries - 1;
379 } else {
380 return free_sq_entries - 1;
381 }
382}
383
384template <class Impl>
385int
386LSQUnit<Impl>::numLoadsReady()
387{
388 int load_idx = loadHead;
389 int retval = 0;
390
391 while (load_idx != loadTail) {
392 assert(loadQueue[load_idx]);
393
394 if (loadQueue[load_idx]->readyToIssue()) {
395 ++retval;
396 }
397 }
398
399 return retval;
400}
401
402template <class Impl>
403Fault
404LSQUnit<Impl>::executeLoad(DynInstPtr &inst)
405{
406 // Execute a specific load.
407 Fault load_fault = NoFault;
408
409 DPRINTF(LSQUnit, "Executing load PC %#x, [sn:%lli]\n",
410 inst->readPC(),inst->seqNum);
411
412 load_fault = inst->initiateAcc();
413
414 // If the instruction faulted, then we need to send it along to commit
415 // without the instruction completing.
416 if (load_fault != NoFault) {
417 // Send this instruction to commit, also make sure iew stage
418 // realizes there is activity.
419 // Mark it as executed unless it is an uncached load that
420 // needs to hit the head of commit.
421 if (!(inst->req && inst->req->isUncacheable()) ||
422 inst->isAtCommit()) {
423 inst->setExecuted();
424 }
425 iewStage->instToCommit(inst);
426 iewStage->activityThisCycle();
427 }
428
429 return load_fault;
430}
431
432template <class Impl>
433Fault
434LSQUnit<Impl>::executeStore(DynInstPtr &store_inst)
435{
436 using namespace TheISA;
437 // Make sure that a store exists.
438 assert(stores != 0);
439
440 int store_idx = store_inst->sqIdx;
441
442 DPRINTF(LSQUnit, "Executing store PC %#x [sn:%lli]\n",
443 store_inst->readPC(), store_inst->seqNum);
444
445 // Check the recently completed loads to see if any match this store's
446 // address. If so, then we have a memory ordering violation.
447 int load_idx = store_inst->lqIdx;
448
449 Fault store_fault = store_inst->initiateAcc();
450
451 if (storeQueue[store_idx].size == 0) {
452 DPRINTF(LSQUnit,"Fault on Store PC %#x, [sn:%lli],Size = 0\n",
453 store_inst->readPC(),store_inst->seqNum);
454
455 return store_fault;
456 }
457
458 assert(store_fault == NoFault);
459
460 if (store_inst->isStoreConditional()) {
461 // Store conditionals need to set themselves as able to
462 // writeback if we haven't had a fault by here.
463 storeQueue[store_idx].canWB = true;
464
465 ++storesToWB;
466 }
467
468 if (!memDepViolator) {
469 while (load_idx != loadTail) {
470 // Really only need to check loads that have actually executed
471 // It's safe to check all loads because effAddr is set to
472 // InvalAddr when the dyn inst is created.
473
474 // @todo: For now this is extra conservative, detecting a
475 // violation if the addresses match assuming all accesses
476 // are quad word accesses.
477
478 // @todo: Fix this, magic number being used here
479 if ((loadQueue[load_idx]->effAddr >> 8) ==
480 (store_inst->effAddr >> 8)) {
481 // A load incorrectly passed this store. Squash and refetch.
482 // For now return a fault to show that it was unsuccessful.
483 memDepViolator = loadQueue[load_idx];
484 ++lsqMemOrderViolation;
485
486 return genMachineCheckFault();
487 }
488
489 incrLdIdx(load_idx);
490 }
491
492 // If we've reached this point, there was no violation.
493 memDepViolator = NULL;
494 }
495
496 return store_fault;
497}
498
499template <class Impl>
500void
501LSQUnit<Impl>::commitLoad()
502{
503 assert(loadQueue[loadHead]);
504
505 DPRINTF(LSQUnit, "Committing head load instruction, PC %#x\n",
506 loadQueue[loadHead]->readPC());
507
508 loadQueue[loadHead] = NULL;
509
510 incrLdIdx(loadHead);
511
512 --loads;
513}
514
515template <class Impl>
516void
517LSQUnit<Impl>::commitLoads(InstSeqNum &youngest_inst)
518{
519 assert(loads == 0 || loadQueue[loadHead]);
520
521 while (loads != 0 && loadQueue[loadHead]->seqNum <= youngest_inst) {
522 commitLoad();
523 }
524}
525
526template <class Impl>
527void
528LSQUnit<Impl>::commitStores(InstSeqNum &youngest_inst)
529{
530 assert(stores == 0 || storeQueue[storeHead].inst);
531
532 int store_idx = storeHead;
533
534 while (store_idx != storeTail) {
535 assert(storeQueue[store_idx].inst);
536 // Mark any stores that are now committed and have not yet
537 // been marked as able to write back.
538 if (!storeQueue[store_idx].canWB) {
539 if (storeQueue[store_idx].inst->seqNum > youngest_inst) {
540 break;
541 }
542 DPRINTF(LSQUnit, "Marking store as able to write back, PC "
543 "%#x [sn:%lli]\n",
544 storeQueue[store_idx].inst->readPC(),
545 storeQueue[store_idx].inst->seqNum);
546
547 storeQueue[store_idx].canWB = true;
548
549 ++storesToWB;
550 }
551
552 incrStIdx(store_idx);
553 }
554}
555
556template <class Impl>
557void
558LSQUnit<Impl>::writebackStores()
559{
560 while (storesToWB > 0 &&
561 storeWBIdx != storeTail &&
562 storeQueue[storeWBIdx].inst &&
563 storeQueue[storeWBIdx].canWB &&
564 usedPorts < cachePorts) {
565
566 if (isStoreBlocked || lsq->cacheBlocked()) {
567 DPRINTF(LSQUnit, "Unable to write back any more stores, cache"
568 " is blocked!\n");
569 break;
570 }
571
572 // Store didn't write any data so no need to write it back to
573 // memory.
574 if (storeQueue[storeWBIdx].size == 0) {
575 completeStore(storeWBIdx);
576
577 incrStIdx(storeWBIdx);
578
579 continue;
580 }
581
582 ++usedPorts;
583
584 if (storeQueue[storeWBIdx].inst->isDataPrefetch()) {
585 incrStIdx(storeWBIdx);
586
587 continue;
588 }
589
590 assert(storeQueue[storeWBIdx].req);
591 assert(!storeQueue[storeWBIdx].committed);
592
593 DynInstPtr inst = storeQueue[storeWBIdx].inst;
594
595 Request *req = storeQueue[storeWBIdx].req;
596 storeQueue[storeWBIdx].committed = true;
597
598 assert(!inst->memData);
599 inst->memData = new uint8_t[64];
600
601 TheISA::IntReg convertedData =
602 TheISA::htog(storeQueue[storeWBIdx].data);
603
604 //FIXME This is a hack to get SPARC working. It, along with endianness
605 //in the memory system in general, need to be straightened out more
606 //formally. The problem is that the data's endianness is swapped when
607 //it's in the 64 bit data field in the store queue. The data that you
608 //want won't start at the beginning of the field anymore unless it was
609 //a 64 bit access.
610 memcpy(inst->memData,
611 (uint8_t *)&convertedData +
612 (TheISA::ByteOrderDiffers ?
613 (sizeof(TheISA::IntReg) - req->getSize()) : 0),
614 req->getSize());
615
|
617 data_pkt->dataStatic(inst->memData);
618
619 LSQSenderState *state = new LSQSenderState;
620 state->isLoad = false;
621 state->idx = storeWBIdx;
622 state->inst = inst;
623 data_pkt->senderState = state;
624
625 DPRINTF(LSQUnit, "D-Cache: Writing back store idx:%i PC:%#x "
626 "to Addr:%#x, data:%#x [sn:%lli]\n",
627 storeWBIdx, inst->readPC(),
628 req->getPaddr(), (int)*(inst->memData),
629 inst->seqNum);
630
631 // @todo: Remove this SC hack once the memory system handles it.
632 if (req->isLocked()) {
633 // Disable recording the result temporarily. Writing to
634 // misc regs normally updates the result, but this is not
635 // the desired behavior when handling store conditionals.
636 inst->recordResult = false;
637 bool success = TheISA::handleLockedWrite(inst.get(), req);
638 inst->recordResult = true;
639
640 if (!success) {
641 // Instantly complete this store.
642 DPRINTF(LSQUnit, "Store conditional [sn:%lli] failed. "
643 "Instantly completing it.\n",
644 inst->seqNum);
645 WritebackEvent *wb = new WritebackEvent(inst, data_pkt, this);
646 wb->schedule(curTick + 1);
647 delete state;
648 completeStore(storeWBIdx);
649 incrStIdx(storeWBIdx);
650 continue;
651 }
652 } else {
653 // Non-store conditionals do not need a writeback.
654 state->noWB = true;
655 }
656
657 if (!dcachePort->sendTiming(data_pkt)) {
658 if (data_pkt->result == Packet::BadAddress) {
659 panic("LSQ sent out a bad address for a completed store!");
660 }
661 // Need to handle becoming blocked on a store.
662 DPRINTF(IEW, "D-Cache became blcoked when writing [sn:%lli], will"
663 "retry later\n",
664 inst->seqNum);
665 isStoreBlocked = true;
666 ++lsqCacheBlocked;
667 assert(retryPkt == NULL);
668 retryPkt = data_pkt;
669 lsq->setRetryTid(lsqID);
670 } else {
671 storePostSend(data_pkt);
672 }
673 }
674
675 // Not sure this should set it to 0.
676 usedPorts = 0;
677
678 assert(stores >= 0 && storesToWB >= 0);
679}
680
681/*template <class Impl>
682void
683LSQUnit<Impl>::removeMSHR(InstSeqNum seqNum)
684{
685 list<InstSeqNum>::iterator mshr_it = find(mshrSeqNums.begin(),
686 mshrSeqNums.end(),
687 seqNum);
688
689 if (mshr_it != mshrSeqNums.end()) {
690 mshrSeqNums.erase(mshr_it);
691 DPRINTF(LSQUnit, "Removing MSHR. count = %i\n",mshrSeqNums.size());
692 }
693}*/
694
695template <class Impl>
696void
697LSQUnit<Impl>::squash(const InstSeqNum &squashed_num)
698{
699 DPRINTF(LSQUnit, "Squashing until [sn:%lli]!"
700 "(Loads:%i Stores:%i)\n", squashed_num, loads, stores);
701
702 int load_idx = loadTail;
703 decrLdIdx(load_idx);
704
705 while (loads != 0 && loadQueue[load_idx]->seqNum > squashed_num) {
706 DPRINTF(LSQUnit,"Load Instruction PC %#x squashed, "
707 "[sn:%lli]\n",
708 loadQueue[load_idx]->readPC(),
709 loadQueue[load_idx]->seqNum);
710
711 if (isStalled() && load_idx == stallingLoadIdx) {
712 stalled = false;
713 stallingStoreIsn = 0;
714 stallingLoadIdx = 0;
715 }
716
717 // Clear the smart pointer to make sure it is decremented.
718 loadQueue[load_idx]->setSquashed();
719 loadQueue[load_idx] = NULL;
720 --loads;
721
722 // Inefficient!
723 loadTail = load_idx;
724
725 decrLdIdx(load_idx);
726 ++lsqSquashedLoads;
727 }
728
729 if (isLoadBlocked) {
730 if (squashed_num < blockedLoadSeqNum) {
731 isLoadBlocked = false;
732 loadBlockedHandled = false;
733 blockedLoadSeqNum = 0;
734 }
735 }
736
737 int store_idx = storeTail;
738 decrStIdx(store_idx);
739
740 while (stores != 0 &&
741 storeQueue[store_idx].inst->seqNum > squashed_num) {
742 // Instructions marked as can WB are already committed.
743 if (storeQueue[store_idx].canWB) {
744 break;
745 }
746
747 DPRINTF(LSQUnit,"Store Instruction PC %#x squashed, "
748 "idx:%i [sn:%lli]\n",
749 storeQueue[store_idx].inst->readPC(),
750 store_idx, storeQueue[store_idx].inst->seqNum);
751
752 // I don't think this can happen. It should have been cleared
753 // by the stalling load.
754 if (isStalled() &&
755 storeQueue[store_idx].inst->seqNum == stallingStoreIsn) {
756 panic("Is stalled should have been cleared by stalling load!\n");
757 stalled = false;
758 stallingStoreIsn = 0;
759 }
760
761 // Clear the smart pointer to make sure it is decremented.
762 storeQueue[store_idx].inst->setSquashed();
763 storeQueue[store_idx].inst = NULL;
764 storeQueue[store_idx].canWB = 0;
765
766 storeQueue[store_idx].req = NULL;
767 --stores;
768
769 // Inefficient!
770 storeTail = store_idx;
771
772 decrStIdx(store_idx);
773 ++lsqSquashedStores;
774 }
775}
776
777template <class Impl>
778void
779LSQUnit<Impl>::storePostSend(PacketPtr pkt)
780{
781 if (isStalled() &&
782 storeQueue[storeWBIdx].inst->seqNum == stallingStoreIsn) {
783 DPRINTF(LSQUnit, "Unstalling, stalling store [sn:%lli] "
784 "load idx:%i\n",
785 stallingStoreIsn, stallingLoadIdx);
786 stalled = false;
787 stallingStoreIsn = 0;
788 iewStage->replayMemInst(loadQueue[stallingLoadIdx]);
789 }
790
791 if (!storeQueue[storeWBIdx].inst->isStoreConditional()) {
792 // The store is basically completed at this time. This
793 // only works so long as the checker doesn't try to
794 // verify the value in memory for stores.
795 storeQueue[storeWBIdx].inst->setCompleted();
796#if USE_CHECKER
797 if (cpu->checker) {
798 cpu->checker->verify(storeQueue[storeWBIdx].inst);
799 }
800#endif
801 }
802
803 if (pkt->result != Packet::Success) {
804 DPRINTF(LSQUnit,"D-Cache Write Miss on idx:%i!\n",
805 storeWBIdx);
806
807 DPRINTF(Activity, "Active st accessing mem miss [sn:%lli]\n",
808 storeQueue[storeWBIdx].inst->seqNum);
809
810 //mshrSeqNums.push_back(storeQueue[storeWBIdx].inst->seqNum);
811
812 //DPRINTF(LSQUnit, "Added MSHR. count = %i\n",mshrSeqNums.size());
813
814 // @todo: Increment stat here.
815 } else {
816 DPRINTF(LSQUnit,"D-Cache: Write Hit on idx:%i !\n",
817 storeWBIdx);
818
819 DPRINTF(Activity, "Active st accessing mem hit [sn:%lli]\n",
820 storeQueue[storeWBIdx].inst->seqNum);
821 }
822
823 incrStIdx(storeWBIdx);
824}
825
826template <class Impl>
827void
828LSQUnit<Impl>::writeback(DynInstPtr &inst, PacketPtr pkt)
829{
830 iewStage->wakeCPU();
831
832 // Squashed instructions do not need to complete their access.
833 if (inst->isSquashed()) {
834 iewStage->decrWb(inst->seqNum);
835 assert(!inst->isStore());
836 ++lsqIgnoredResponses;
837 return;
838 }
839
840 if (!inst->isExecuted()) {
841 inst->setExecuted();
842
843 // Complete access to copy data to proper place.
844 inst->completeAcc(pkt);
845 }
846
847 // Need to insert instruction into queue to commit
848 iewStage->instToCommit(inst);
849
850 iewStage->activityThisCycle();
851}
852
853template <class Impl>
854void
855LSQUnit<Impl>::completeStore(int store_idx)
856{
857 assert(storeQueue[store_idx].inst);
858 storeQueue[store_idx].completed = true;
859 --storesToWB;
860 // A bit conservative because a store completion may not free up entries,
861 // but hopefully avoids two store completions in one cycle from making
862 // the CPU tick twice.
863 cpu->wakeCPU();
864 cpu->activityThisCycle();
865
866 if (store_idx == storeHead) {
867 do {
868 incrStIdx(storeHead);
869
870 --stores;
871 } while (storeQueue[storeHead].completed &&
872 storeHead != storeTail);
873
874 iewStage->updateLSQNextCycle = true;
875 }
876
877 DPRINTF(LSQUnit, "Completing store [sn:%lli], idx:%i, store head "
878 "idx:%i\n",
879 storeQueue[store_idx].inst->seqNum, store_idx, storeHead);
880
881 if (isStalled() &&
882 storeQueue[store_idx].inst->seqNum == stallingStoreIsn) {
883 DPRINTF(LSQUnit, "Unstalling, stalling store [sn:%lli] "
884 "load idx:%i\n",
885 stallingStoreIsn, stallingLoadIdx);
886 stalled = false;
887 stallingStoreIsn = 0;
888 iewStage->replayMemInst(loadQueue[stallingLoadIdx]);
889 }
890
891 storeQueue[store_idx].inst->setCompleted();
892
893 // Tell the checker we've completed this instruction. Some stores
894 // may get reported twice to the checker, but the checker can
895 // handle that case.
896#if USE_CHECKER
897 if (cpu->checker) {
898 cpu->checker->verify(storeQueue[store_idx].inst);
899 }
900#endif
901}
902
903template <class Impl>
904void
905LSQUnit<Impl>::recvRetry()
906{
907 if (isStoreBlocked) {
908 assert(retryPkt != NULL);
909
910 if (dcachePort->sendTiming(retryPkt)) {
911 if (retryPkt->result == Packet::BadAddress) {
912 panic("LSQ sent out a bad address for a completed store!");
913 }
914 storePostSend(retryPkt);
915 retryPkt = NULL;
916 isStoreBlocked = false;
917 lsq->setRetryTid(-1);
918 } else {
919 // Still blocked!
920 ++lsqCacheBlocked;
921 lsq->setRetryTid(lsqID);
922 }
923 } else if (isLoadBlocked) {
924 DPRINTF(LSQUnit, "Loads squash themselves and all younger insts, "
925 "no need to resend packet.\n");
926 } else {
927 DPRINTF(LSQUnit, "Retry received but LSQ is no longer blocked.\n");
928 }
929}
930
931template <class Impl>
932inline void
933LSQUnit<Impl>::incrStIdx(int &store_idx)
934{
935 if (++store_idx >= SQEntries)
936 store_idx = 0;
937}
938
939template <class Impl>
940inline void
941LSQUnit<Impl>::decrStIdx(int &store_idx)
942{
943 if (--store_idx < 0)
944 store_idx += SQEntries;
945}
946
947template <class Impl>
948inline void
949LSQUnit<Impl>::incrLdIdx(int &load_idx)
950{
951 if (++load_idx >= LQEntries)
952 load_idx = 0;
953}
954
955template <class Impl>
956inline void
957LSQUnit<Impl>::decrLdIdx(int &load_idx)
958{
959 if (--load_idx < 0)
960 load_idx += LQEntries;
961}
962
963template <class Impl>
964void
965LSQUnit<Impl>::dumpInsts()
966{
967 cprintf("Load store queue: Dumping instructions.\n");
968 cprintf("Load queue size: %i\n", loads);
969 cprintf("Load queue: ");
970
971 int load_idx = loadHead;
972
973 while (load_idx != loadTail && loadQueue[load_idx]) {
974 cprintf("%#x ", loadQueue[load_idx]->readPC());
975
976 incrLdIdx(load_idx);
977 }
978
979 cprintf("Store queue size: %i\n", stores);
980 cprintf("Store queue: ");
981
982 int store_idx = storeHead;
983
984 while (store_idx != storeTail && storeQueue[store_idx].inst) {
985 cprintf("%#x ", storeQueue[store_idx].inst->readPC());
986
987 incrStIdx(store_idx);
988 }
989
990 cprintf("\n");
991}
| 618 data_pkt->dataStatic(inst->memData);
619
620 LSQSenderState *state = new LSQSenderState;
621 state->isLoad = false;
622 state->idx = storeWBIdx;
623 state->inst = inst;
624 data_pkt->senderState = state;
625
626 DPRINTF(LSQUnit, "D-Cache: Writing back store idx:%i PC:%#x "
627 "to Addr:%#x, data:%#x [sn:%lli]\n",
628 storeWBIdx, inst->readPC(),
629 req->getPaddr(), (int)*(inst->memData),
630 inst->seqNum);
631
632 // @todo: Remove this SC hack once the memory system handles it.
633 if (req->isLocked()) {
634 // Disable recording the result temporarily. Writing to
635 // misc regs normally updates the result, but this is not
636 // the desired behavior when handling store conditionals.
637 inst->recordResult = false;
638 bool success = TheISA::handleLockedWrite(inst.get(), req);
639 inst->recordResult = true;
640
641 if (!success) {
642 // Instantly complete this store.
643 DPRINTF(LSQUnit, "Store conditional [sn:%lli] failed. "
644 "Instantly completing it.\n",
645 inst->seqNum);
646 WritebackEvent *wb = new WritebackEvent(inst, data_pkt, this);
647 wb->schedule(curTick + 1);
648 delete state;
649 completeStore(storeWBIdx);
650 incrStIdx(storeWBIdx);
651 continue;
652 }
653 } else {
654 // Non-store conditionals do not need a writeback.
655 state->noWB = true;
656 }
657
658 if (!dcachePort->sendTiming(data_pkt)) {
659 if (data_pkt->result == Packet::BadAddress) {
660 panic("LSQ sent out a bad address for a completed store!");
661 }
662 // Need to handle becoming blocked on a store.
663 DPRINTF(IEW, "D-Cache became blcoked when writing [sn:%lli], will"
664 "retry later\n",
665 inst->seqNum);
666 isStoreBlocked = true;
667 ++lsqCacheBlocked;
668 assert(retryPkt == NULL);
669 retryPkt = data_pkt;
670 lsq->setRetryTid(lsqID);
671 } else {
672 storePostSend(data_pkt);
673 }
674 }
675
676 // Not sure this should set it to 0.
677 usedPorts = 0;
678
679 assert(stores >= 0 && storesToWB >= 0);
680}
681
682/*template <class Impl>
683void
684LSQUnit<Impl>::removeMSHR(InstSeqNum seqNum)
685{
686 list<InstSeqNum>::iterator mshr_it = find(mshrSeqNums.begin(),
687 mshrSeqNums.end(),
688 seqNum);
689
690 if (mshr_it != mshrSeqNums.end()) {
691 mshrSeqNums.erase(mshr_it);
692 DPRINTF(LSQUnit, "Removing MSHR. count = %i\n",mshrSeqNums.size());
693 }
694}*/
695
696template <class Impl>
697void
698LSQUnit<Impl>::squash(const InstSeqNum &squashed_num)
699{
700 DPRINTF(LSQUnit, "Squashing until [sn:%lli]!"
701 "(Loads:%i Stores:%i)\n", squashed_num, loads, stores);
702
703 int load_idx = loadTail;
704 decrLdIdx(load_idx);
705
706 while (loads != 0 && loadQueue[load_idx]->seqNum > squashed_num) {
707 DPRINTF(LSQUnit,"Load Instruction PC %#x squashed, "
708 "[sn:%lli]\n",
709 loadQueue[load_idx]->readPC(),
710 loadQueue[load_idx]->seqNum);
711
712 if (isStalled() && load_idx == stallingLoadIdx) {
713 stalled = false;
714 stallingStoreIsn = 0;
715 stallingLoadIdx = 0;
716 }
717
718 // Clear the smart pointer to make sure it is decremented.
719 loadQueue[load_idx]->setSquashed();
720 loadQueue[load_idx] = NULL;
721 --loads;
722
723 // Inefficient!
724 loadTail = load_idx;
725
726 decrLdIdx(load_idx);
727 ++lsqSquashedLoads;
728 }
729
730 if (isLoadBlocked) {
731 if (squashed_num < blockedLoadSeqNum) {
732 isLoadBlocked = false;
733 loadBlockedHandled = false;
734 blockedLoadSeqNum = 0;
735 }
736 }
737
738 int store_idx = storeTail;
739 decrStIdx(store_idx);
740
741 while (stores != 0 &&
742 storeQueue[store_idx].inst->seqNum > squashed_num) {
743 // Instructions marked as can WB are already committed.
744 if (storeQueue[store_idx].canWB) {
745 break;
746 }
747
748 DPRINTF(LSQUnit,"Store Instruction PC %#x squashed, "
749 "idx:%i [sn:%lli]\n",
750 storeQueue[store_idx].inst->readPC(),
751 store_idx, storeQueue[store_idx].inst->seqNum);
752
753 // I don't think this can happen. It should have been cleared
754 // by the stalling load.
755 if (isStalled() &&
756 storeQueue[store_idx].inst->seqNum == stallingStoreIsn) {
757 panic("Is stalled should have been cleared by stalling load!\n");
758 stalled = false;
759 stallingStoreIsn = 0;
760 }
761
762 // Clear the smart pointer to make sure it is decremented.
763 storeQueue[store_idx].inst->setSquashed();
764 storeQueue[store_idx].inst = NULL;
765 storeQueue[store_idx].canWB = 0;
766
767 storeQueue[store_idx].req = NULL;
768 --stores;
769
770 // Inefficient!
771 storeTail = store_idx;
772
773 decrStIdx(store_idx);
774 ++lsqSquashedStores;
775 }
776}
777
778template <class Impl>
779void
780LSQUnit<Impl>::storePostSend(PacketPtr pkt)
781{
782 if (isStalled() &&
783 storeQueue[storeWBIdx].inst->seqNum == stallingStoreIsn) {
784 DPRINTF(LSQUnit, "Unstalling, stalling store [sn:%lli] "
785 "load idx:%i\n",
786 stallingStoreIsn, stallingLoadIdx);
787 stalled = false;
788 stallingStoreIsn = 0;
789 iewStage->replayMemInst(loadQueue[stallingLoadIdx]);
790 }
791
792 if (!storeQueue[storeWBIdx].inst->isStoreConditional()) {
793 // The store is basically completed at this time. This
794 // only works so long as the checker doesn't try to
795 // verify the value in memory for stores.
796 storeQueue[storeWBIdx].inst->setCompleted();
797#if USE_CHECKER
798 if (cpu->checker) {
799 cpu->checker->verify(storeQueue[storeWBIdx].inst);
800 }
801#endif
802 }
803
804 if (pkt->result != Packet::Success) {
805 DPRINTF(LSQUnit,"D-Cache Write Miss on idx:%i!\n",
806 storeWBIdx);
807
808 DPRINTF(Activity, "Active st accessing mem miss [sn:%lli]\n",
809 storeQueue[storeWBIdx].inst->seqNum);
810
811 //mshrSeqNums.push_back(storeQueue[storeWBIdx].inst->seqNum);
812
813 //DPRINTF(LSQUnit, "Added MSHR. count = %i\n",mshrSeqNums.size());
814
815 // @todo: Increment stat here.
816 } else {
817 DPRINTF(LSQUnit,"D-Cache: Write Hit on idx:%i !\n",
818 storeWBIdx);
819
820 DPRINTF(Activity, "Active st accessing mem hit [sn:%lli]\n",
821 storeQueue[storeWBIdx].inst->seqNum);
822 }
823
824 incrStIdx(storeWBIdx);
825}
826
827template <class Impl>
828void
829LSQUnit<Impl>::writeback(DynInstPtr &inst, PacketPtr pkt)
830{
831 iewStage->wakeCPU();
832
833 // Squashed instructions do not need to complete their access.
834 if (inst->isSquashed()) {
835 iewStage->decrWb(inst->seqNum);
836 assert(!inst->isStore());
837 ++lsqIgnoredResponses;
838 return;
839 }
840
841 if (!inst->isExecuted()) {
842 inst->setExecuted();
843
844 // Complete access to copy data to proper place.
845 inst->completeAcc(pkt);
846 }
847
848 // Need to insert instruction into queue to commit
849 iewStage->instToCommit(inst);
850
851 iewStage->activityThisCycle();
852}
853
854template <class Impl>
855void
856LSQUnit<Impl>::completeStore(int store_idx)
857{
858 assert(storeQueue[store_idx].inst);
859 storeQueue[store_idx].completed = true;
860 --storesToWB;
861 // A bit conservative because a store completion may not free up entries,
862 // but hopefully avoids two store completions in one cycle from making
863 // the CPU tick twice.
864 cpu->wakeCPU();
865 cpu->activityThisCycle();
866
867 if (store_idx == storeHead) {
868 do {
869 incrStIdx(storeHead);
870
871 --stores;
872 } while (storeQueue[storeHead].completed &&
873 storeHead != storeTail);
874
875 iewStage->updateLSQNextCycle = true;
876 }
877
878 DPRINTF(LSQUnit, "Completing store [sn:%lli], idx:%i, store head "
879 "idx:%i\n",
880 storeQueue[store_idx].inst->seqNum, store_idx, storeHead);
881
882 if (isStalled() &&
883 storeQueue[store_idx].inst->seqNum == stallingStoreIsn) {
884 DPRINTF(LSQUnit, "Unstalling, stalling store [sn:%lli] "
885 "load idx:%i\n",
886 stallingStoreIsn, stallingLoadIdx);
887 stalled = false;
888 stallingStoreIsn = 0;
889 iewStage->replayMemInst(loadQueue[stallingLoadIdx]);
890 }
891
892 storeQueue[store_idx].inst->setCompleted();
893
894 // Tell the checker we've completed this instruction. Some stores
895 // may get reported twice to the checker, but the checker can
896 // handle that case.
897#if USE_CHECKER
898 if (cpu->checker) {
899 cpu->checker->verify(storeQueue[store_idx].inst);
900 }
901#endif
902}
903
904template <class Impl>
905void
906LSQUnit<Impl>::recvRetry()
907{
908 if (isStoreBlocked) {
909 assert(retryPkt != NULL);
910
911 if (dcachePort->sendTiming(retryPkt)) {
912 if (retryPkt->result == Packet::BadAddress) {
913 panic("LSQ sent out a bad address for a completed store!");
914 }
915 storePostSend(retryPkt);
916 retryPkt = NULL;
917 isStoreBlocked = false;
918 lsq->setRetryTid(-1);
919 } else {
920 // Still blocked!
921 ++lsqCacheBlocked;
922 lsq->setRetryTid(lsqID);
923 }
924 } else if (isLoadBlocked) {
925 DPRINTF(LSQUnit, "Loads squash themselves and all younger insts, "
926 "no need to resend packet.\n");
927 } else {
928 DPRINTF(LSQUnit, "Retry received but LSQ is no longer blocked.\n");
929 }
930}
931
932template <class Impl>
933inline void
934LSQUnit<Impl>::incrStIdx(int &store_idx)
935{
936 if (++store_idx >= SQEntries)
937 store_idx = 0;
938}
939
940template <class Impl>
941inline void
942LSQUnit<Impl>::decrStIdx(int &store_idx)
943{
944 if (--store_idx < 0)
945 store_idx += SQEntries;
946}
947
948template <class Impl>
949inline void
950LSQUnit<Impl>::incrLdIdx(int &load_idx)
951{
952 if (++load_idx >= LQEntries)
953 load_idx = 0;
954}
955
956template <class Impl>
957inline void
958LSQUnit<Impl>::decrLdIdx(int &load_idx)
959{
960 if (--load_idx < 0)
961 load_idx += LQEntries;
962}
963
964template <class Impl>
965void
966LSQUnit<Impl>::dumpInsts()
967{
968 cprintf("Load store queue: Dumping instructions.\n");
969 cprintf("Load queue size: %i\n", loads);
970 cprintf("Load queue: ");
971
972 int load_idx = loadHead;
973
974 while (load_idx != loadTail && loadQueue[load_idx]) {
975 cprintf("%#x ", loadQueue[load_idx]->readPC());
976
977 incrLdIdx(load_idx);
978 }
979
980 cprintf("Store queue size: %i\n", stores);
981 cprintf("Store queue: ");
982
983 int store_idx = storeHead;
984
985 while (store_idx != storeTail && storeQueue[store_idx].inst) {
986 cprintf("%#x ", storeQueue[store_idx].inst->readPC());
987
988 incrStIdx(store_idx);
989 }
990
991 cprintf("\n");
992}
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