1/*
2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Kevin Lim
29 * Korey Sewell
30 */
31
| 1/*
2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Kevin Lim
29 * Korey Sewell
30 */
31
|
| 32#include "arch/locked_mem.hh"
|
32#include "config/use_checker.hh"
33
34#include "cpu/o3/lsq.hh"
35#include "cpu/o3/lsq_unit.hh"
36#include "base/str.hh"
37#include "mem/packet.hh"
38#include "mem/request.hh"
39
40#if USE_CHECKER
41#include "cpu/checker/cpu.hh"
42#endif
43
44template<class Impl>
45LSQUnit<Impl>::WritebackEvent::WritebackEvent(DynInstPtr &_inst, PacketPtr _pkt,
46 LSQUnit *lsq_ptr)
47 : Event(&mainEventQueue), inst(_inst), pkt(_pkt), lsqPtr(lsq_ptr)
48{
49 this->setFlags(Event::AutoDelete);
50}
51
52template<class Impl>
53void
54LSQUnit<Impl>::WritebackEvent::process()
55{
56 if (!lsqPtr->isSwitchedOut()) {
57 lsqPtr->writeback(inst, pkt);
58 }
59 delete pkt;
60}
61
62template<class Impl>
63const char *
64LSQUnit<Impl>::WritebackEvent::description()
65{
66 return "Store writeback event";
67}
68
69template<class Impl>
70void
71LSQUnit<Impl>::completeDataAccess(PacketPtr pkt)
72{
73 LSQSenderState *state = dynamic_cast<LSQSenderState *>(pkt->senderState);
74 DynInstPtr inst = state->inst;
75 DPRINTF(IEW, "Writeback event [sn:%lli]\n", inst->seqNum);
76 DPRINTF(Activity, "Activity: Writeback event [sn:%lli]\n", inst->seqNum);
77
78 //iewStage->ldstQueue.removeMSHR(inst->threadNumber,inst->seqNum);
79
80 if (isSwitchedOut() || inst->isSquashed()) {
81 iewStage->decrWb(inst->seqNum);
82 delete state;
83 delete pkt;
84 return;
85 } else {
86 if (!state->noWB) {
87 writeback(inst, pkt);
88 }
89
90 if (inst->isStore()) {
91 completeStore(state->idx);
92 }
93 }
94
95 delete state;
96 delete pkt;
97}
98
99template <class Impl>
100LSQUnit<Impl>::LSQUnit()
101 : loads(0), stores(0), storesToWB(0), stalled(false),
102 isStoreBlocked(false), isLoadBlocked(false),
103 loadBlockedHandled(false)
104{
105}
106
107template<class Impl>
108void
109LSQUnit<Impl>::init(Params *params, LSQ *lsq_ptr, unsigned maxLQEntries,
110 unsigned maxSQEntries, unsigned id)
111{
112 DPRINTF(LSQUnit, "Creating LSQUnit%i object.\n",id);
113
114 switchedOut = false;
115
116 lsq = lsq_ptr;
117
118 lsqID = id;
119
120 // Add 1 for the sentinel entry (they are circular queues).
121 LQEntries = maxLQEntries + 1;
122 SQEntries = maxSQEntries + 1;
123
124 loadQueue.resize(LQEntries);
125 storeQueue.resize(SQEntries);
126
127 loadHead = loadTail = 0;
128
129 storeHead = storeWBIdx = storeTail = 0;
130
131 usedPorts = 0;
132 cachePorts = params->cachePorts;
133
134 memDepViolator = NULL;
135
136 blockedLoadSeqNum = 0;
137}
138
139template<class Impl>
140void
141LSQUnit<Impl>::setCPU(O3CPU *cpu_ptr)
142{
143 cpu = cpu_ptr;
144
145#if USE_CHECKER
146 if (cpu->checker) {
147 cpu->checker->setDcachePort(dcachePort);
148 }
149#endif
150}
151
152template<class Impl>
153std::string
154LSQUnit<Impl>::name() const
155{
156 if (Impl::MaxThreads == 1) {
157 return iewStage->name() + ".lsq";
158 } else {
159 return iewStage->name() + ".lsq.thread." + to_string(lsqID);
160 }
161}
162
163template<class Impl>
164void
165LSQUnit<Impl>::regStats()
166{
167 lsqForwLoads
168 .name(name() + ".forwLoads")
169 .desc("Number of loads that had data forwarded from stores");
170
171 invAddrLoads
172 .name(name() + ".invAddrLoads")
173 .desc("Number of loads ignored due to an invalid address");
174
175 lsqSquashedLoads
176 .name(name() + ".squashedLoads")
177 .desc("Number of loads squashed");
178
179 lsqIgnoredResponses
180 .name(name() + ".ignoredResponses")
181 .desc("Number of memory responses ignored because the instruction is squashed");
182
183 lsqMemOrderViolation
184 .name(name() + ".memOrderViolation")
185 .desc("Number of memory ordering violations");
186
187 lsqSquashedStores
188 .name(name() + ".squashedStores")
189 .desc("Number of stores squashed");
190
191 invAddrSwpfs
192 .name(name() + ".invAddrSwpfs")
193 .desc("Number of software prefetches ignored due to an invalid address");
194
195 lsqBlockedLoads
196 .name(name() + ".blockedLoads")
197 .desc("Number of blocked loads due to partial load-store forwarding");
198
199 lsqRescheduledLoads
200 .name(name() + ".rescheduledLoads")
201 .desc("Number of loads that were rescheduled");
202
203 lsqCacheBlocked
204 .name(name() + ".cacheBlocked")
205 .desc("Number of times an access to memory failed due to the cache being blocked");
206}
207
208template<class Impl>
209void
210LSQUnit<Impl>::clearLQ()
211{
212 loadQueue.clear();
213}
214
215template<class Impl>
216void
217LSQUnit<Impl>::clearSQ()
218{
219 storeQueue.clear();
220}
221
222template<class Impl>
223void
224LSQUnit<Impl>::switchOut()
225{
226 switchedOut = true;
227 for (int i = 0; i < loadQueue.size(); ++i) {
228 assert(!loadQueue[i]);
229 loadQueue[i] = NULL;
230 }
231
232 assert(storesToWB == 0);
233}
234
235template<class Impl>
236void
237LSQUnit<Impl>::takeOverFrom()
238{
239 switchedOut = false;
240 loads = stores = storesToWB = 0;
241
242 loadHead = loadTail = 0;
243
244 storeHead = storeWBIdx = storeTail = 0;
245
246 usedPorts = 0;
247
248 memDepViolator = NULL;
249
250 blockedLoadSeqNum = 0;
251
252 stalled = false;
253 isLoadBlocked = false;
254 loadBlockedHandled = false;
255}
256
257template<class Impl>
258void
259LSQUnit<Impl>::resizeLQ(unsigned size)
260{
261 unsigned size_plus_sentinel = size + 1;
262 assert(size_plus_sentinel >= LQEntries);
263
264 if (size_plus_sentinel > LQEntries) {
265 while (size_plus_sentinel > loadQueue.size()) {
266 DynInstPtr dummy;
267 loadQueue.push_back(dummy);
268 LQEntries++;
269 }
270 } else {
271 LQEntries = size_plus_sentinel;
272 }
273
274}
275
276template<class Impl>
277void
278LSQUnit<Impl>::resizeSQ(unsigned size)
279{
280 unsigned size_plus_sentinel = size + 1;
281 if (size_plus_sentinel > SQEntries) {
282 while (size_plus_sentinel > storeQueue.size()) {
283 SQEntry dummy;
284 storeQueue.push_back(dummy);
285 SQEntries++;
286 }
287 } else {
288 SQEntries = size_plus_sentinel;
289 }
290}
291
292template <class Impl>
293void
294LSQUnit<Impl>::insert(DynInstPtr &inst)
295{
296 assert(inst->isMemRef());
297
298 assert(inst->isLoad() || inst->isStore());
299
300 if (inst->isLoad()) {
301 insertLoad(inst);
302 } else {
303 insertStore(inst);
304 }
305
306 inst->setInLSQ();
307}
308
309template <class Impl>
310void
311LSQUnit<Impl>::insertLoad(DynInstPtr &load_inst)
312{
313 assert((loadTail + 1) % LQEntries != loadHead);
314 assert(loads < LQEntries);
315
316 DPRINTF(LSQUnit, "Inserting load PC %#x, idx:%i [sn:%lli]\n",
317 load_inst->readPC(), loadTail, load_inst->seqNum);
318
319 load_inst->lqIdx = loadTail;
320
321 if (stores == 0) {
322 load_inst->sqIdx = -1;
323 } else {
324 load_inst->sqIdx = storeTail;
325 }
326
327 loadQueue[loadTail] = load_inst;
328
329 incrLdIdx(loadTail);
330
331 ++loads;
332}
333
334template <class Impl>
335void
336LSQUnit<Impl>::insertStore(DynInstPtr &store_inst)
337{
338 // Make sure it is not full before inserting an instruction.
339 assert((storeTail + 1) % SQEntries != storeHead);
340 assert(stores < SQEntries);
341
342 DPRINTF(LSQUnit, "Inserting store PC %#x, idx:%i [sn:%lli]\n",
343 store_inst->readPC(), storeTail, store_inst->seqNum);
344
345 store_inst->sqIdx = storeTail;
346 store_inst->lqIdx = loadTail;
347
348 storeQueue[storeTail] = SQEntry(store_inst);
349
350 incrStIdx(storeTail);
351
352 ++stores;
353}
354
355template <class Impl>
356typename Impl::DynInstPtr
357LSQUnit<Impl>::getMemDepViolator()
358{
359 DynInstPtr temp = memDepViolator;
360
361 memDepViolator = NULL;
362
363 return temp;
364}
365
366template <class Impl>
367unsigned
368LSQUnit<Impl>::numFreeEntries()
369{
370 unsigned free_lq_entries = LQEntries - loads;
371 unsigned free_sq_entries = SQEntries - stores;
372
373 // Both the LQ and SQ entries have an extra dummy entry to differentiate
374 // empty/full conditions. Subtract 1 from the free entries.
375 if (free_lq_entries < free_sq_entries) {
376 return free_lq_entries - 1;
377 } else {
378 return free_sq_entries - 1;
379 }
380}
381
382template <class Impl>
383int
384LSQUnit<Impl>::numLoadsReady()
385{
386 int load_idx = loadHead;
387 int retval = 0;
388
389 while (load_idx != loadTail) {
390 assert(loadQueue[load_idx]);
391
392 if (loadQueue[load_idx]->readyToIssue()) {
393 ++retval;
394 }
395 }
396
397 return retval;
398}
399
400template <class Impl>
401Fault
402LSQUnit<Impl>::executeLoad(DynInstPtr &inst)
403{
404 // Execute a specific load.
405 Fault load_fault = NoFault;
406
407 DPRINTF(LSQUnit, "Executing load PC %#x, [sn:%lli]\n",
408 inst->readPC(),inst->seqNum);
409
410 load_fault = inst->initiateAcc();
411
412 // If the instruction faulted, then we need to send it along to commit
413 // without the instruction completing.
414 if (load_fault != NoFault) {
415 // Send this instruction to commit, also make sure iew stage
416 // realizes there is activity.
417 // Mark it as executed unless it is an uncached load that
418 // needs to hit the head of commit.
419 if (!(inst->req->isUncacheable()) || inst->isAtCommit()) {
420 inst->setExecuted();
421 }
422 iewStage->instToCommit(inst);
423 iewStage->activityThisCycle();
424 }
425
426 return load_fault;
427}
428
429template <class Impl>
430Fault
431LSQUnit<Impl>::executeStore(DynInstPtr &store_inst)
432{
433 using namespace TheISA;
434 // Make sure that a store exists.
435 assert(stores != 0);
436
437 int store_idx = store_inst->sqIdx;
438
439 DPRINTF(LSQUnit, "Executing store PC %#x [sn:%lli]\n",
440 store_inst->readPC(), store_inst->seqNum);
441
442 // Check the recently completed loads to see if any match this store's
443 // address. If so, then we have a memory ordering violation.
444 int load_idx = store_inst->lqIdx;
445
446 Fault store_fault = store_inst->initiateAcc();
447
448 if (storeQueue[store_idx].size == 0) {
449 DPRINTF(LSQUnit,"Fault on Store PC %#x, [sn:%lli],Size = 0\n",
450 store_inst->readPC(),store_inst->seqNum);
451
452 return store_fault;
453 }
454
455 assert(store_fault == NoFault);
456
457 if (store_inst->isStoreConditional()) {
458 // Store conditionals need to set themselves as able to
459 // writeback if we haven't had a fault by here.
460 storeQueue[store_idx].canWB = true;
461
462 ++storesToWB;
463 }
464
465 if (!memDepViolator) {
466 while (load_idx != loadTail) {
467 // Really only need to check loads that have actually executed
468 // It's safe to check all loads because effAddr is set to
469 // InvalAddr when the dyn inst is created.
470
471 // @todo: For now this is extra conservative, detecting a
472 // violation if the addresses match assuming all accesses
473 // are quad word accesses.
474
475 // @todo: Fix this, magic number being used here
476 if ((loadQueue[load_idx]->effAddr >> 8) ==
477 (store_inst->effAddr >> 8)) {
478 // A load incorrectly passed this store. Squash and refetch.
479 // For now return a fault to show that it was unsuccessful.
480 memDepViolator = loadQueue[load_idx];
481 ++lsqMemOrderViolation;
482
483 return genMachineCheckFault();
484 }
485
486 incrLdIdx(load_idx);
487 }
488
489 // If we've reached this point, there was no violation.
490 memDepViolator = NULL;
491 }
492
493 return store_fault;
494}
495
496template <class Impl>
497void
498LSQUnit<Impl>::commitLoad()
499{
500 assert(loadQueue[loadHead]);
501
502 DPRINTF(LSQUnit, "Committing head load instruction, PC %#x\n",
503 loadQueue[loadHead]->readPC());
504
505 loadQueue[loadHead] = NULL;
506
507 incrLdIdx(loadHead);
508
509 --loads;
510}
511
512template <class Impl>
513void
514LSQUnit<Impl>::commitLoads(InstSeqNum &youngest_inst)
515{
516 assert(loads == 0 || loadQueue[loadHead]);
517
518 while (loads != 0 && loadQueue[loadHead]->seqNum <= youngest_inst) {
519 commitLoad();
520 }
521}
522
523template <class Impl>
524void
525LSQUnit<Impl>::commitStores(InstSeqNum &youngest_inst)
526{
527 assert(stores == 0 || storeQueue[storeHead].inst);
528
529 int store_idx = storeHead;
530
531 while (store_idx != storeTail) {
532 assert(storeQueue[store_idx].inst);
533 // Mark any stores that are now committed and have not yet
534 // been marked as able to write back.
535 if (!storeQueue[store_idx].canWB) {
536 if (storeQueue[store_idx].inst->seqNum > youngest_inst) {
537 break;
538 }
539 DPRINTF(LSQUnit, "Marking store as able to write back, PC "
540 "%#x [sn:%lli]\n",
541 storeQueue[store_idx].inst->readPC(),
542 storeQueue[store_idx].inst->seqNum);
543
544 storeQueue[store_idx].canWB = true;
545
546 ++storesToWB;
547 }
548
549 incrStIdx(store_idx);
550 }
551}
552
553template <class Impl>
554void
555LSQUnit<Impl>::writebackStores()
556{
557 while (storesToWB > 0 &&
558 storeWBIdx != storeTail &&
559 storeQueue[storeWBIdx].inst &&
560 storeQueue[storeWBIdx].canWB &&
561 usedPorts < cachePorts) {
562
563 if (isStoreBlocked || lsq->cacheBlocked()) {
564 DPRINTF(LSQUnit, "Unable to write back any more stores, cache"
565 " is blocked!\n");
566 break;
567 }
568
569 // Store didn't write any data so no need to write it back to
570 // memory.
571 if (storeQueue[storeWBIdx].size == 0) {
572 completeStore(storeWBIdx);
573
574 incrStIdx(storeWBIdx);
575
576 continue;
577 }
578
579 ++usedPorts;
580
581 if (storeQueue[storeWBIdx].inst->isDataPrefetch()) {
582 incrStIdx(storeWBIdx);
583
584 continue;
585 }
586
587 assert(storeQueue[storeWBIdx].req);
588 assert(!storeQueue[storeWBIdx].committed);
589
590 DynInstPtr inst = storeQueue[storeWBIdx].inst;
591
592 Request *req = storeQueue[storeWBIdx].req;
593 storeQueue[storeWBIdx].committed = true;
594
595 assert(!inst->memData);
596 inst->memData = new uint8_t[64];
597 memcpy(inst->memData, (uint8_t *)&storeQueue[storeWBIdx].data,
598 req->getSize());
599
600 PacketPtr data_pkt = new Packet(req, Packet::WriteReq, Packet::Broadcast);
601 data_pkt->dataStatic(inst->memData);
602
603 LSQSenderState *state = new LSQSenderState;
604 state->isLoad = false;
605 state->idx = storeWBIdx;
606 state->inst = inst;
607 data_pkt->senderState = state;
608
609 DPRINTF(LSQUnit, "D-Cache: Writing back store idx:%i PC:%#x "
610 "to Addr:%#x, data:%#x [sn:%lli]\n",
611 storeWBIdx, inst->readPC(),
612 req->getPaddr(), *(inst->memData),
613 inst->seqNum);
614
615 // @todo: Remove this SC hack once the memory system handles it.
616 if (req->isLocked()) {
| 33#include "config/use_checker.hh"
34
35#include "cpu/o3/lsq.hh"
36#include "cpu/o3/lsq_unit.hh"
37#include "base/str.hh"
38#include "mem/packet.hh"
39#include "mem/request.hh"
40
41#if USE_CHECKER
42#include "cpu/checker/cpu.hh"
43#endif
44
45template<class Impl>
46LSQUnit<Impl>::WritebackEvent::WritebackEvent(DynInstPtr &_inst, PacketPtr _pkt,
47 LSQUnit *lsq_ptr)
48 : Event(&mainEventQueue), inst(_inst), pkt(_pkt), lsqPtr(lsq_ptr)
49{
50 this->setFlags(Event::AutoDelete);
51}
52
53template<class Impl>
54void
55LSQUnit<Impl>::WritebackEvent::process()
56{
57 if (!lsqPtr->isSwitchedOut()) {
58 lsqPtr->writeback(inst, pkt);
59 }
60 delete pkt;
61}
62
63template<class Impl>
64const char *
65LSQUnit<Impl>::WritebackEvent::description()
66{
67 return "Store writeback event";
68}
69
70template<class Impl>
71void
72LSQUnit<Impl>::completeDataAccess(PacketPtr pkt)
73{
74 LSQSenderState *state = dynamic_cast<LSQSenderState *>(pkt->senderState);
75 DynInstPtr inst = state->inst;
76 DPRINTF(IEW, "Writeback event [sn:%lli]\n", inst->seqNum);
77 DPRINTF(Activity, "Activity: Writeback event [sn:%lli]\n", inst->seqNum);
78
79 //iewStage->ldstQueue.removeMSHR(inst->threadNumber,inst->seqNum);
80
81 if (isSwitchedOut() || inst->isSquashed()) {
82 iewStage->decrWb(inst->seqNum);
83 delete state;
84 delete pkt;
85 return;
86 } else {
87 if (!state->noWB) {
88 writeback(inst, pkt);
89 }
90
91 if (inst->isStore()) {
92 completeStore(state->idx);
93 }
94 }
95
96 delete state;
97 delete pkt;
98}
99
100template <class Impl>
101LSQUnit<Impl>::LSQUnit()
102 : loads(0), stores(0), storesToWB(0), stalled(false),
103 isStoreBlocked(false), isLoadBlocked(false),
104 loadBlockedHandled(false)
105{
106}
107
108template<class Impl>
109void
110LSQUnit<Impl>::init(Params *params, LSQ *lsq_ptr, unsigned maxLQEntries,
111 unsigned maxSQEntries, unsigned id)
112{
113 DPRINTF(LSQUnit, "Creating LSQUnit%i object.\n",id);
114
115 switchedOut = false;
116
117 lsq = lsq_ptr;
118
119 lsqID = id;
120
121 // Add 1 for the sentinel entry (they are circular queues).
122 LQEntries = maxLQEntries + 1;
123 SQEntries = maxSQEntries + 1;
124
125 loadQueue.resize(LQEntries);
126 storeQueue.resize(SQEntries);
127
128 loadHead = loadTail = 0;
129
130 storeHead = storeWBIdx = storeTail = 0;
131
132 usedPorts = 0;
133 cachePorts = params->cachePorts;
134
135 memDepViolator = NULL;
136
137 blockedLoadSeqNum = 0;
138}
139
140template<class Impl>
141void
142LSQUnit<Impl>::setCPU(O3CPU *cpu_ptr)
143{
144 cpu = cpu_ptr;
145
146#if USE_CHECKER
147 if (cpu->checker) {
148 cpu->checker->setDcachePort(dcachePort);
149 }
150#endif
151}
152
153template<class Impl>
154std::string
155LSQUnit<Impl>::name() const
156{
157 if (Impl::MaxThreads == 1) {
158 return iewStage->name() + ".lsq";
159 } else {
160 return iewStage->name() + ".lsq.thread." + to_string(lsqID);
161 }
162}
163
164template<class Impl>
165void
166LSQUnit<Impl>::regStats()
167{
168 lsqForwLoads
169 .name(name() + ".forwLoads")
170 .desc("Number of loads that had data forwarded from stores");
171
172 invAddrLoads
173 .name(name() + ".invAddrLoads")
174 .desc("Number of loads ignored due to an invalid address");
175
176 lsqSquashedLoads
177 .name(name() + ".squashedLoads")
178 .desc("Number of loads squashed");
179
180 lsqIgnoredResponses
181 .name(name() + ".ignoredResponses")
182 .desc("Number of memory responses ignored because the instruction is squashed");
183
184 lsqMemOrderViolation
185 .name(name() + ".memOrderViolation")
186 .desc("Number of memory ordering violations");
187
188 lsqSquashedStores
189 .name(name() + ".squashedStores")
190 .desc("Number of stores squashed");
191
192 invAddrSwpfs
193 .name(name() + ".invAddrSwpfs")
194 .desc("Number of software prefetches ignored due to an invalid address");
195
196 lsqBlockedLoads
197 .name(name() + ".blockedLoads")
198 .desc("Number of blocked loads due to partial load-store forwarding");
199
200 lsqRescheduledLoads
201 .name(name() + ".rescheduledLoads")
202 .desc("Number of loads that were rescheduled");
203
204 lsqCacheBlocked
205 .name(name() + ".cacheBlocked")
206 .desc("Number of times an access to memory failed due to the cache being blocked");
207}
208
209template<class Impl>
210void
211LSQUnit<Impl>::clearLQ()
212{
213 loadQueue.clear();
214}
215
216template<class Impl>
217void
218LSQUnit<Impl>::clearSQ()
219{
220 storeQueue.clear();
221}
222
223template<class Impl>
224void
225LSQUnit<Impl>::switchOut()
226{
227 switchedOut = true;
228 for (int i = 0; i < loadQueue.size(); ++i) {
229 assert(!loadQueue[i]);
230 loadQueue[i] = NULL;
231 }
232
233 assert(storesToWB == 0);
234}
235
236template<class Impl>
237void
238LSQUnit<Impl>::takeOverFrom()
239{
240 switchedOut = false;
241 loads = stores = storesToWB = 0;
242
243 loadHead = loadTail = 0;
244
245 storeHead = storeWBIdx = storeTail = 0;
246
247 usedPorts = 0;
248
249 memDepViolator = NULL;
250
251 blockedLoadSeqNum = 0;
252
253 stalled = false;
254 isLoadBlocked = false;
255 loadBlockedHandled = false;
256}
257
258template<class Impl>
259void
260LSQUnit<Impl>::resizeLQ(unsigned size)
261{
262 unsigned size_plus_sentinel = size + 1;
263 assert(size_plus_sentinel >= LQEntries);
264
265 if (size_plus_sentinel > LQEntries) {
266 while (size_plus_sentinel > loadQueue.size()) {
267 DynInstPtr dummy;
268 loadQueue.push_back(dummy);
269 LQEntries++;
270 }
271 } else {
272 LQEntries = size_plus_sentinel;
273 }
274
275}
276
277template<class Impl>
278void
279LSQUnit<Impl>::resizeSQ(unsigned size)
280{
281 unsigned size_plus_sentinel = size + 1;
282 if (size_plus_sentinel > SQEntries) {
283 while (size_plus_sentinel > storeQueue.size()) {
284 SQEntry dummy;
285 storeQueue.push_back(dummy);
286 SQEntries++;
287 }
288 } else {
289 SQEntries = size_plus_sentinel;
290 }
291}
292
293template <class Impl>
294void
295LSQUnit<Impl>::insert(DynInstPtr &inst)
296{
297 assert(inst->isMemRef());
298
299 assert(inst->isLoad() || inst->isStore());
300
301 if (inst->isLoad()) {
302 insertLoad(inst);
303 } else {
304 insertStore(inst);
305 }
306
307 inst->setInLSQ();
308}
309
310template <class Impl>
311void
312LSQUnit<Impl>::insertLoad(DynInstPtr &load_inst)
313{
314 assert((loadTail + 1) % LQEntries != loadHead);
315 assert(loads < LQEntries);
316
317 DPRINTF(LSQUnit, "Inserting load PC %#x, idx:%i [sn:%lli]\n",
318 load_inst->readPC(), loadTail, load_inst->seqNum);
319
320 load_inst->lqIdx = loadTail;
321
322 if (stores == 0) {
323 load_inst->sqIdx = -1;
324 } else {
325 load_inst->sqIdx = storeTail;
326 }
327
328 loadQueue[loadTail] = load_inst;
329
330 incrLdIdx(loadTail);
331
332 ++loads;
333}
334
335template <class Impl>
336void
337LSQUnit<Impl>::insertStore(DynInstPtr &store_inst)
338{
339 // Make sure it is not full before inserting an instruction.
340 assert((storeTail + 1) % SQEntries != storeHead);
341 assert(stores < SQEntries);
342
343 DPRINTF(LSQUnit, "Inserting store PC %#x, idx:%i [sn:%lli]\n",
344 store_inst->readPC(), storeTail, store_inst->seqNum);
345
346 store_inst->sqIdx = storeTail;
347 store_inst->lqIdx = loadTail;
348
349 storeQueue[storeTail] = SQEntry(store_inst);
350
351 incrStIdx(storeTail);
352
353 ++stores;
354}
355
356template <class Impl>
357typename Impl::DynInstPtr
358LSQUnit<Impl>::getMemDepViolator()
359{
360 DynInstPtr temp = memDepViolator;
361
362 memDepViolator = NULL;
363
364 return temp;
365}
366
367template <class Impl>
368unsigned
369LSQUnit<Impl>::numFreeEntries()
370{
371 unsigned free_lq_entries = LQEntries - loads;
372 unsigned free_sq_entries = SQEntries - stores;
373
374 // Both the LQ and SQ entries have an extra dummy entry to differentiate
375 // empty/full conditions. Subtract 1 from the free entries.
376 if (free_lq_entries < free_sq_entries) {
377 return free_lq_entries - 1;
378 } else {
379 return free_sq_entries - 1;
380 }
381}
382
383template <class Impl>
384int
385LSQUnit<Impl>::numLoadsReady()
386{
387 int load_idx = loadHead;
388 int retval = 0;
389
390 while (load_idx != loadTail) {
391 assert(loadQueue[load_idx]);
392
393 if (loadQueue[load_idx]->readyToIssue()) {
394 ++retval;
395 }
396 }
397
398 return retval;
399}
400
401template <class Impl>
402Fault
403LSQUnit<Impl>::executeLoad(DynInstPtr &inst)
404{
405 // Execute a specific load.
406 Fault load_fault = NoFault;
407
408 DPRINTF(LSQUnit, "Executing load PC %#x, [sn:%lli]\n",
409 inst->readPC(),inst->seqNum);
410
411 load_fault = inst->initiateAcc();
412
413 // If the instruction faulted, then we need to send it along to commit
414 // without the instruction completing.
415 if (load_fault != NoFault) {
416 // Send this instruction to commit, also make sure iew stage
417 // realizes there is activity.
418 // Mark it as executed unless it is an uncached load that
419 // needs to hit the head of commit.
420 if (!(inst->req->isUncacheable()) || inst->isAtCommit()) {
421 inst->setExecuted();
422 }
423 iewStage->instToCommit(inst);
424 iewStage->activityThisCycle();
425 }
426
427 return load_fault;
428}
429
430template <class Impl>
431Fault
432LSQUnit<Impl>::executeStore(DynInstPtr &store_inst)
433{
434 using namespace TheISA;
435 // Make sure that a store exists.
436 assert(stores != 0);
437
438 int store_idx = store_inst->sqIdx;
439
440 DPRINTF(LSQUnit, "Executing store PC %#x [sn:%lli]\n",
441 store_inst->readPC(), store_inst->seqNum);
442
443 // Check the recently completed loads to see if any match this store's
444 // address. If so, then we have a memory ordering violation.
445 int load_idx = store_inst->lqIdx;
446
447 Fault store_fault = store_inst->initiateAcc();
448
449 if (storeQueue[store_idx].size == 0) {
450 DPRINTF(LSQUnit,"Fault on Store PC %#x, [sn:%lli],Size = 0\n",
451 store_inst->readPC(),store_inst->seqNum);
452
453 return store_fault;
454 }
455
456 assert(store_fault == NoFault);
457
458 if (store_inst->isStoreConditional()) {
459 // Store conditionals need to set themselves as able to
460 // writeback if we haven't had a fault by here.
461 storeQueue[store_idx].canWB = true;
462
463 ++storesToWB;
464 }
465
466 if (!memDepViolator) {
467 while (load_idx != loadTail) {
468 // Really only need to check loads that have actually executed
469 // It's safe to check all loads because effAddr is set to
470 // InvalAddr when the dyn inst is created.
471
472 // @todo: For now this is extra conservative, detecting a
473 // violation if the addresses match assuming all accesses
474 // are quad word accesses.
475
476 // @todo: Fix this, magic number being used here
477 if ((loadQueue[load_idx]->effAddr >> 8) ==
478 (store_inst->effAddr >> 8)) {
479 // A load incorrectly passed this store. Squash and refetch.
480 // For now return a fault to show that it was unsuccessful.
481 memDepViolator = loadQueue[load_idx];
482 ++lsqMemOrderViolation;
483
484 return genMachineCheckFault();
485 }
486
487 incrLdIdx(load_idx);
488 }
489
490 // If we've reached this point, there was no violation.
491 memDepViolator = NULL;
492 }
493
494 return store_fault;
495}
496
497template <class Impl>
498void
499LSQUnit<Impl>::commitLoad()
500{
501 assert(loadQueue[loadHead]);
502
503 DPRINTF(LSQUnit, "Committing head load instruction, PC %#x\n",
504 loadQueue[loadHead]->readPC());
505
506 loadQueue[loadHead] = NULL;
507
508 incrLdIdx(loadHead);
509
510 --loads;
511}
512
513template <class Impl>
514void
515LSQUnit<Impl>::commitLoads(InstSeqNum &youngest_inst)
516{
517 assert(loads == 0 || loadQueue[loadHead]);
518
519 while (loads != 0 && loadQueue[loadHead]->seqNum <= youngest_inst) {
520 commitLoad();
521 }
522}
523
524template <class Impl>
525void
526LSQUnit<Impl>::commitStores(InstSeqNum &youngest_inst)
527{
528 assert(stores == 0 || storeQueue[storeHead].inst);
529
530 int store_idx = storeHead;
531
532 while (store_idx != storeTail) {
533 assert(storeQueue[store_idx].inst);
534 // Mark any stores that are now committed and have not yet
535 // been marked as able to write back.
536 if (!storeQueue[store_idx].canWB) {
537 if (storeQueue[store_idx].inst->seqNum > youngest_inst) {
538 break;
539 }
540 DPRINTF(LSQUnit, "Marking store as able to write back, PC "
541 "%#x [sn:%lli]\n",
542 storeQueue[store_idx].inst->readPC(),
543 storeQueue[store_idx].inst->seqNum);
544
545 storeQueue[store_idx].canWB = true;
546
547 ++storesToWB;
548 }
549
550 incrStIdx(store_idx);
551 }
552}
553
554template <class Impl>
555void
556LSQUnit<Impl>::writebackStores()
557{
558 while (storesToWB > 0 &&
559 storeWBIdx != storeTail &&
560 storeQueue[storeWBIdx].inst &&
561 storeQueue[storeWBIdx].canWB &&
562 usedPorts < cachePorts) {
563
564 if (isStoreBlocked || lsq->cacheBlocked()) {
565 DPRINTF(LSQUnit, "Unable to write back any more stores, cache"
566 " is blocked!\n");
567 break;
568 }
569
570 // Store didn't write any data so no need to write it back to
571 // memory.
572 if (storeQueue[storeWBIdx].size == 0) {
573 completeStore(storeWBIdx);
574
575 incrStIdx(storeWBIdx);
576
577 continue;
578 }
579
580 ++usedPorts;
581
582 if (storeQueue[storeWBIdx].inst->isDataPrefetch()) {
583 incrStIdx(storeWBIdx);
584
585 continue;
586 }
587
588 assert(storeQueue[storeWBIdx].req);
589 assert(!storeQueue[storeWBIdx].committed);
590
591 DynInstPtr inst = storeQueue[storeWBIdx].inst;
592
593 Request *req = storeQueue[storeWBIdx].req;
594 storeQueue[storeWBIdx].committed = true;
595
596 assert(!inst->memData);
597 inst->memData = new uint8_t[64];
598 memcpy(inst->memData, (uint8_t *)&storeQueue[storeWBIdx].data,
599 req->getSize());
600
601 PacketPtr data_pkt = new Packet(req, Packet::WriteReq, Packet::Broadcast);
602 data_pkt->dataStatic(inst->memData);
603
604 LSQSenderState *state = new LSQSenderState;
605 state->isLoad = false;
606 state->idx = storeWBIdx;
607 state->inst = inst;
608 data_pkt->senderState = state;
609
610 DPRINTF(LSQUnit, "D-Cache: Writing back store idx:%i PC:%#x "
611 "to Addr:%#x, data:%#x [sn:%lli]\n",
612 storeWBIdx, inst->readPC(),
613 req->getPaddr(), *(inst->memData),
614 inst->seqNum);
615
616 // @todo: Remove this SC hack once the memory system handles it.
617 if (req->isLocked()) {
|
617 if (req->isUncacheable()) {
618 req->setScResult(2);
619 } else {
620 if (cpu->lockFlag) {
621 req->setScResult(1);
622 DPRINTF(LSQUnit, "Store conditional [sn:%lli] succeeded.",
623 inst->seqNum);
624 } else {
625 req->setScResult(0);
626 // Hack: Instantly complete this store.
627// completeDataAccess(data_pkt);
628 DPRINTF(LSQUnit, "Store conditional [sn:%lli] failed. "
629 "Instantly completing it.\n",
630 inst->seqNum);
631 WritebackEvent *wb = new WritebackEvent(inst, data_pkt, this);
632 wb->schedule(curTick + 1);
633 delete state;
634 completeStore(storeWBIdx);
635 incrStIdx(storeWBIdx);
636 continue;
637 }
| 618 // Disable recording the result temporarily. Writing to
619 // misc regs normally updates the result, but this is not
620 // the desired behavior when handling store conditionals.
621 inst->recordResult = false;
622 bool success = TheISA::handleLockedWrite(inst.get(), req);
623 inst->recordResult = true;
624
625 if (!success) {
626 // Instantly complete this store.
627 DPRINTF(LSQUnit, "Store conditional [sn:%lli] failed. "
628 "Instantly completing it.\n",
629 inst->seqNum);
630 WritebackEvent *wb = new WritebackEvent(inst, data_pkt, this);
631 wb->schedule(curTick + 1);
632 delete state;
633 completeStore(storeWBIdx);
634 incrStIdx(storeWBIdx);
635 continue;
|
638 }
639 } else {
640 // Non-store conditionals do not need a writeback.
641 state->noWB = true;
642 }
643
644 if (!dcachePort->sendTiming(data_pkt)) {
645 if (data_pkt->result == Packet::BadAddress) {
646 panic("LSQ sent out a bad address for a completed store!");
647 }
648 // Need to handle becoming blocked on a store.
649 DPRINTF(IEW, "D-Cache became blcoked when writing [sn:%lli], will"
650 "retry later\n",
651 inst->seqNum);
652 isStoreBlocked = true;
653 ++lsqCacheBlocked;
654 assert(retryPkt == NULL);
655 retryPkt = data_pkt;
656 lsq->setRetryTid(lsqID);
657 } else {
658 storePostSend(data_pkt);
659 }
660 }
661
662 // Not sure this should set it to 0.
663 usedPorts = 0;
664
665 assert(stores >= 0 && storesToWB >= 0);
666}
667
668/*template <class Impl>
669void
670LSQUnit<Impl>::removeMSHR(InstSeqNum seqNum)
671{
672 list<InstSeqNum>::iterator mshr_it = find(mshrSeqNums.begin(),
673 mshrSeqNums.end(),
674 seqNum);
675
676 if (mshr_it != mshrSeqNums.end()) {
677 mshrSeqNums.erase(mshr_it);
678 DPRINTF(LSQUnit, "Removing MSHR. count = %i\n",mshrSeqNums.size());
679 }
680}*/
681
682template <class Impl>
683void
684LSQUnit<Impl>::squash(const InstSeqNum &squashed_num)
685{
686 DPRINTF(LSQUnit, "Squashing until [sn:%lli]!"
687 "(Loads:%i Stores:%i)\n", squashed_num, loads, stores);
688
689 int load_idx = loadTail;
690 decrLdIdx(load_idx);
691
692 while (loads != 0 && loadQueue[load_idx]->seqNum > squashed_num) {
693 DPRINTF(LSQUnit,"Load Instruction PC %#x squashed, "
694 "[sn:%lli]\n",
695 loadQueue[load_idx]->readPC(),
696 loadQueue[load_idx]->seqNum);
697
698 if (isStalled() && load_idx == stallingLoadIdx) {
699 stalled = false;
700 stallingStoreIsn = 0;
701 stallingLoadIdx = 0;
702 }
703
704 // Clear the smart pointer to make sure it is decremented.
705 loadQueue[load_idx]->setSquashed();
706 loadQueue[load_idx] = NULL;
707 --loads;
708
709 // Inefficient!
710 loadTail = load_idx;
711
712 decrLdIdx(load_idx);
713 ++lsqSquashedLoads;
714 }
715
716 if (isLoadBlocked) {
717 if (squashed_num < blockedLoadSeqNum) {
718 isLoadBlocked = false;
719 loadBlockedHandled = false;
720 blockedLoadSeqNum = 0;
721 }
722 }
723
724 int store_idx = storeTail;
725 decrStIdx(store_idx);
726
727 while (stores != 0 &&
728 storeQueue[store_idx].inst->seqNum > squashed_num) {
729 // Instructions marked as can WB are already committed.
730 if (storeQueue[store_idx].canWB) {
731 break;
732 }
733
734 DPRINTF(LSQUnit,"Store Instruction PC %#x squashed, "
735 "idx:%i [sn:%lli]\n",
736 storeQueue[store_idx].inst->readPC(),
737 store_idx, storeQueue[store_idx].inst->seqNum);
738
739 // I don't think this can happen. It should have been cleared
740 // by the stalling load.
741 if (isStalled() &&
742 storeQueue[store_idx].inst->seqNum == stallingStoreIsn) {
743 panic("Is stalled should have been cleared by stalling load!\n");
744 stalled = false;
745 stallingStoreIsn = 0;
746 }
747
748 // Clear the smart pointer to make sure it is decremented.
749 storeQueue[store_idx].inst->setSquashed();
750 storeQueue[store_idx].inst = NULL;
751 storeQueue[store_idx].canWB = 0;
752
753 storeQueue[store_idx].req = NULL;
754 --stores;
755
756 // Inefficient!
757 storeTail = store_idx;
758
759 decrStIdx(store_idx);
760 ++lsqSquashedStores;
761 }
762}
763
764template <class Impl>
765void
766LSQUnit<Impl>::storePostSend(Packet *pkt)
767{
768 if (isStalled() &&
769 storeQueue[storeWBIdx].inst->seqNum == stallingStoreIsn) {
770 DPRINTF(LSQUnit, "Unstalling, stalling store [sn:%lli] "
771 "load idx:%i\n",
772 stallingStoreIsn, stallingLoadIdx);
773 stalled = false;
774 stallingStoreIsn = 0;
775 iewStage->replayMemInst(loadQueue[stallingLoadIdx]);
776 }
777
778 if (!storeQueue[storeWBIdx].inst->isStoreConditional()) {
779 // The store is basically completed at this time. This
780 // only works so long as the checker doesn't try to
781 // verify the value in memory for stores.
782 storeQueue[storeWBIdx].inst->setCompleted();
783#if USE_CHECKER
784 if (cpu->checker) {
785 cpu->checker->verify(storeQueue[storeWBIdx].inst);
786 }
787#endif
788 }
789
790 if (pkt->result != Packet::Success) {
791 DPRINTF(LSQUnit,"D-Cache Write Miss on idx:%i!\n",
792 storeWBIdx);
793
794 DPRINTF(Activity, "Active st accessing mem miss [sn:%lli]\n",
795 storeQueue[storeWBIdx].inst->seqNum);
796
797 //mshrSeqNums.push_back(storeQueue[storeWBIdx].inst->seqNum);
798
799 //DPRINTF(LSQUnit, "Added MSHR. count = %i\n",mshrSeqNums.size());
800
801 // @todo: Increment stat here.
802 } else {
803 DPRINTF(LSQUnit,"D-Cache: Write Hit on idx:%i !\n",
804 storeWBIdx);
805
806 DPRINTF(Activity, "Active st accessing mem hit [sn:%lli]\n",
807 storeQueue[storeWBIdx].inst->seqNum);
808 }
809
810 incrStIdx(storeWBIdx);
811}
812
813template <class Impl>
814void
815LSQUnit<Impl>::writeback(DynInstPtr &inst, PacketPtr pkt)
816{
817 iewStage->wakeCPU();
818
819 // Squashed instructions do not need to complete their access.
820 if (inst->isSquashed()) {
821 iewStage->decrWb(inst->seqNum);
822 assert(!inst->isStore());
823 ++lsqIgnoredResponses;
824 return;
825 }
826
827 if (!inst->isExecuted()) {
828 inst->setExecuted();
829
830 // Complete access to copy data to proper place.
831 inst->completeAcc(pkt);
832 }
833
834 // Need to insert instruction into queue to commit
835 iewStage->instToCommit(inst);
836
837 iewStage->activityThisCycle();
838}
839
840template <class Impl>
841void
842LSQUnit<Impl>::completeStore(int store_idx)
843{
844 assert(storeQueue[store_idx].inst);
845 storeQueue[store_idx].completed = true;
846 --storesToWB;
847 // A bit conservative because a store completion may not free up entries,
848 // but hopefully avoids two store completions in one cycle from making
849 // the CPU tick twice.
850 cpu->wakeCPU();
851 cpu->activityThisCycle();
852
853 if (store_idx == storeHead) {
854 do {
855 incrStIdx(storeHead);
856
857 --stores;
858 } while (storeQueue[storeHead].completed &&
859 storeHead != storeTail);
860
861 iewStage->updateLSQNextCycle = true;
862 }
863
864 DPRINTF(LSQUnit, "Completing store [sn:%lli], idx:%i, store head "
865 "idx:%i\n",
866 storeQueue[store_idx].inst->seqNum, store_idx, storeHead);
867
868 if (isStalled() &&
869 storeQueue[store_idx].inst->seqNum == stallingStoreIsn) {
870 DPRINTF(LSQUnit, "Unstalling, stalling store [sn:%lli] "
871 "load idx:%i\n",
872 stallingStoreIsn, stallingLoadIdx);
873 stalled = false;
874 stallingStoreIsn = 0;
875 iewStage->replayMemInst(loadQueue[stallingLoadIdx]);
876 }
877
878 storeQueue[store_idx].inst->setCompleted();
879
880 // Tell the checker we've completed this instruction. Some stores
881 // may get reported twice to the checker, but the checker can
882 // handle that case.
883#if USE_CHECKER
884 if (cpu->checker) {
885 cpu->checker->verify(storeQueue[store_idx].inst);
886 }
887#endif
888}
889
890template <class Impl>
891void
892LSQUnit<Impl>::recvRetry()
893{
894 if (isStoreBlocked) {
895 assert(retryPkt != NULL);
896
897 if (dcachePort->sendTiming(retryPkt)) {
898 if (retryPkt->result == Packet::BadAddress) {
899 panic("LSQ sent out a bad address for a completed store!");
900 }
901 storePostSend(retryPkt);
902 retryPkt = NULL;
903 isStoreBlocked = false;
904 lsq->setRetryTid(-1);
905 } else {
906 // Still blocked!
907 ++lsqCacheBlocked;
908 lsq->setRetryTid(lsqID);
909 }
910 } else if (isLoadBlocked) {
911 DPRINTF(LSQUnit, "Loads squash themselves and all younger insts, "
912 "no need to resend packet.\n");
913 } else {
914 DPRINTF(LSQUnit, "Retry received but LSQ is no longer blocked.\n");
915 }
916}
917
918template <class Impl>
919inline void
920LSQUnit<Impl>::incrStIdx(int &store_idx)
921{
922 if (++store_idx >= SQEntries)
923 store_idx = 0;
924}
925
926template <class Impl>
927inline void
928LSQUnit<Impl>::decrStIdx(int &store_idx)
929{
930 if (--store_idx < 0)
931 store_idx += SQEntries;
932}
933
934template <class Impl>
935inline void
936LSQUnit<Impl>::incrLdIdx(int &load_idx)
937{
938 if (++load_idx >= LQEntries)
939 load_idx = 0;
940}
941
942template <class Impl>
943inline void
944LSQUnit<Impl>::decrLdIdx(int &load_idx)
945{
946 if (--load_idx < 0)
947 load_idx += LQEntries;
948}
949
950template <class Impl>
951void
952LSQUnit<Impl>::dumpInsts()
953{
954 cprintf("Load store queue: Dumping instructions.\n");
955 cprintf("Load queue size: %i\n", loads);
956 cprintf("Load queue: ");
957
958 int load_idx = loadHead;
959
960 while (load_idx != loadTail && loadQueue[load_idx]) {
961 cprintf("%#x ", loadQueue[load_idx]->readPC());
962
963 incrLdIdx(load_idx);
964 }
965
966 cprintf("Store queue size: %i\n", stores);
967 cprintf("Store queue: ");
968
969 int store_idx = storeHead;
970
971 while (store_idx != storeTail && storeQueue[store_idx].inst) {
972 cprintf("%#x ", storeQueue[store_idx].inst->readPC());
973
974 incrStIdx(store_idx);
975 }
976
977 cprintf("\n");
978}
| 636 }
637 } else {
638 // Non-store conditionals do not need a writeback.
639 state->noWB = true;
640 }
641
642 if (!dcachePort->sendTiming(data_pkt)) {
643 if (data_pkt->result == Packet::BadAddress) {
644 panic("LSQ sent out a bad address for a completed store!");
645 }
646 // Need to handle becoming blocked on a store.
647 DPRINTF(IEW, "D-Cache became blcoked when writing [sn:%lli], will"
648 "retry later\n",
649 inst->seqNum);
650 isStoreBlocked = true;
651 ++lsqCacheBlocked;
652 assert(retryPkt == NULL);
653 retryPkt = data_pkt;
654 lsq->setRetryTid(lsqID);
655 } else {
656 storePostSend(data_pkt);
657 }
658 }
659
660 // Not sure this should set it to 0.
661 usedPorts = 0;
662
663 assert(stores >= 0 && storesToWB >= 0);
664}
665
666/*template <class Impl>
667void
668LSQUnit<Impl>::removeMSHR(InstSeqNum seqNum)
669{
670 list<InstSeqNum>::iterator mshr_it = find(mshrSeqNums.begin(),
671 mshrSeqNums.end(),
672 seqNum);
673
674 if (mshr_it != mshrSeqNums.end()) {
675 mshrSeqNums.erase(mshr_it);
676 DPRINTF(LSQUnit, "Removing MSHR. count = %i\n",mshrSeqNums.size());
677 }
678}*/
679
680template <class Impl>
681void
682LSQUnit<Impl>::squash(const InstSeqNum &squashed_num)
683{
684 DPRINTF(LSQUnit, "Squashing until [sn:%lli]!"
685 "(Loads:%i Stores:%i)\n", squashed_num, loads, stores);
686
687 int load_idx = loadTail;
688 decrLdIdx(load_idx);
689
690 while (loads != 0 && loadQueue[load_idx]->seqNum > squashed_num) {
691 DPRINTF(LSQUnit,"Load Instruction PC %#x squashed, "
692 "[sn:%lli]\n",
693 loadQueue[load_idx]->readPC(),
694 loadQueue[load_idx]->seqNum);
695
696 if (isStalled() && load_idx == stallingLoadIdx) {
697 stalled = false;
698 stallingStoreIsn = 0;
699 stallingLoadIdx = 0;
700 }
701
702 // Clear the smart pointer to make sure it is decremented.
703 loadQueue[load_idx]->setSquashed();
704 loadQueue[load_idx] = NULL;
705 --loads;
706
707 // Inefficient!
708 loadTail = load_idx;
709
710 decrLdIdx(load_idx);
711 ++lsqSquashedLoads;
712 }
713
714 if (isLoadBlocked) {
715 if (squashed_num < blockedLoadSeqNum) {
716 isLoadBlocked = false;
717 loadBlockedHandled = false;
718 blockedLoadSeqNum = 0;
719 }
720 }
721
722 int store_idx = storeTail;
723 decrStIdx(store_idx);
724
725 while (stores != 0 &&
726 storeQueue[store_idx].inst->seqNum > squashed_num) {
727 // Instructions marked as can WB are already committed.
728 if (storeQueue[store_idx].canWB) {
729 break;
730 }
731
732 DPRINTF(LSQUnit,"Store Instruction PC %#x squashed, "
733 "idx:%i [sn:%lli]\n",
734 storeQueue[store_idx].inst->readPC(),
735 store_idx, storeQueue[store_idx].inst->seqNum);
736
737 // I don't think this can happen. It should have been cleared
738 // by the stalling load.
739 if (isStalled() &&
740 storeQueue[store_idx].inst->seqNum == stallingStoreIsn) {
741 panic("Is stalled should have been cleared by stalling load!\n");
742 stalled = false;
743 stallingStoreIsn = 0;
744 }
745
746 // Clear the smart pointer to make sure it is decremented.
747 storeQueue[store_idx].inst->setSquashed();
748 storeQueue[store_idx].inst = NULL;
749 storeQueue[store_idx].canWB = 0;
750
751 storeQueue[store_idx].req = NULL;
752 --stores;
753
754 // Inefficient!
755 storeTail = store_idx;
756
757 decrStIdx(store_idx);
758 ++lsqSquashedStores;
759 }
760}
761
762template <class Impl>
763void
764LSQUnit<Impl>::storePostSend(Packet *pkt)
765{
766 if (isStalled() &&
767 storeQueue[storeWBIdx].inst->seqNum == stallingStoreIsn) {
768 DPRINTF(LSQUnit, "Unstalling, stalling store [sn:%lli] "
769 "load idx:%i\n",
770 stallingStoreIsn, stallingLoadIdx);
771 stalled = false;
772 stallingStoreIsn = 0;
773 iewStage->replayMemInst(loadQueue[stallingLoadIdx]);
774 }
775
776 if (!storeQueue[storeWBIdx].inst->isStoreConditional()) {
777 // The store is basically completed at this time. This
778 // only works so long as the checker doesn't try to
779 // verify the value in memory for stores.
780 storeQueue[storeWBIdx].inst->setCompleted();
781#if USE_CHECKER
782 if (cpu->checker) {
783 cpu->checker->verify(storeQueue[storeWBIdx].inst);
784 }
785#endif
786 }
787
788 if (pkt->result != Packet::Success) {
789 DPRINTF(LSQUnit,"D-Cache Write Miss on idx:%i!\n",
790 storeWBIdx);
791
792 DPRINTF(Activity, "Active st accessing mem miss [sn:%lli]\n",
793 storeQueue[storeWBIdx].inst->seqNum);
794
795 //mshrSeqNums.push_back(storeQueue[storeWBIdx].inst->seqNum);
796
797 //DPRINTF(LSQUnit, "Added MSHR. count = %i\n",mshrSeqNums.size());
798
799 // @todo: Increment stat here.
800 } else {
801 DPRINTF(LSQUnit,"D-Cache: Write Hit on idx:%i !\n",
802 storeWBIdx);
803
804 DPRINTF(Activity, "Active st accessing mem hit [sn:%lli]\n",
805 storeQueue[storeWBIdx].inst->seqNum);
806 }
807
808 incrStIdx(storeWBIdx);
809}
810
811template <class Impl>
812void
813LSQUnit<Impl>::writeback(DynInstPtr &inst, PacketPtr pkt)
814{
815 iewStage->wakeCPU();
816
817 // Squashed instructions do not need to complete their access.
818 if (inst->isSquashed()) {
819 iewStage->decrWb(inst->seqNum);
820 assert(!inst->isStore());
821 ++lsqIgnoredResponses;
822 return;
823 }
824
825 if (!inst->isExecuted()) {
826 inst->setExecuted();
827
828 // Complete access to copy data to proper place.
829 inst->completeAcc(pkt);
830 }
831
832 // Need to insert instruction into queue to commit
833 iewStage->instToCommit(inst);
834
835 iewStage->activityThisCycle();
836}
837
838template <class Impl>
839void
840LSQUnit<Impl>::completeStore(int store_idx)
841{
842 assert(storeQueue[store_idx].inst);
843 storeQueue[store_idx].completed = true;
844 --storesToWB;
845 // A bit conservative because a store completion may not free up entries,
846 // but hopefully avoids two store completions in one cycle from making
847 // the CPU tick twice.
848 cpu->wakeCPU();
849 cpu->activityThisCycle();
850
851 if (store_idx == storeHead) {
852 do {
853 incrStIdx(storeHead);
854
855 --stores;
856 } while (storeQueue[storeHead].completed &&
857 storeHead != storeTail);
858
859 iewStage->updateLSQNextCycle = true;
860 }
861
862 DPRINTF(LSQUnit, "Completing store [sn:%lli], idx:%i, store head "
863 "idx:%i\n",
864 storeQueue[store_idx].inst->seqNum, store_idx, storeHead);
865
866 if (isStalled() &&
867 storeQueue[store_idx].inst->seqNum == stallingStoreIsn) {
868 DPRINTF(LSQUnit, "Unstalling, stalling store [sn:%lli] "
869 "load idx:%i\n",
870 stallingStoreIsn, stallingLoadIdx);
871 stalled = false;
872 stallingStoreIsn = 0;
873 iewStage->replayMemInst(loadQueue[stallingLoadIdx]);
874 }
875
876 storeQueue[store_idx].inst->setCompleted();
877
878 // Tell the checker we've completed this instruction. Some stores
879 // may get reported twice to the checker, but the checker can
880 // handle that case.
881#if USE_CHECKER
882 if (cpu->checker) {
883 cpu->checker->verify(storeQueue[store_idx].inst);
884 }
885#endif
886}
887
888template <class Impl>
889void
890LSQUnit<Impl>::recvRetry()
891{
892 if (isStoreBlocked) {
893 assert(retryPkt != NULL);
894
895 if (dcachePort->sendTiming(retryPkt)) {
896 if (retryPkt->result == Packet::BadAddress) {
897 panic("LSQ sent out a bad address for a completed store!");
898 }
899 storePostSend(retryPkt);
900 retryPkt = NULL;
901 isStoreBlocked = false;
902 lsq->setRetryTid(-1);
903 } else {
904 // Still blocked!
905 ++lsqCacheBlocked;
906 lsq->setRetryTid(lsqID);
907 }
908 } else if (isLoadBlocked) {
909 DPRINTF(LSQUnit, "Loads squash themselves and all younger insts, "
910 "no need to resend packet.\n");
911 } else {
912 DPRINTF(LSQUnit, "Retry received but LSQ is no longer blocked.\n");
913 }
914}
915
916template <class Impl>
917inline void
918LSQUnit<Impl>::incrStIdx(int &store_idx)
919{
920 if (++store_idx >= SQEntries)
921 store_idx = 0;
922}
923
924template <class Impl>
925inline void
926LSQUnit<Impl>::decrStIdx(int &store_idx)
927{
928 if (--store_idx < 0)
929 store_idx += SQEntries;
930}
931
932template <class Impl>
933inline void
934LSQUnit<Impl>::incrLdIdx(int &load_idx)
935{
936 if (++load_idx >= LQEntries)
937 load_idx = 0;
938}
939
940template <class Impl>
941inline void
942LSQUnit<Impl>::decrLdIdx(int &load_idx)
943{
944 if (--load_idx < 0)
945 load_idx += LQEntries;
946}
947
948template <class Impl>
949void
950LSQUnit<Impl>::dumpInsts()
951{
952 cprintf("Load store queue: Dumping instructions.\n");
953 cprintf("Load queue size: %i\n", loads);
954 cprintf("Load queue: ");
955
956 int load_idx = loadHead;
957
958 while (load_idx != loadTail && loadQueue[load_idx]) {
959 cprintf("%#x ", loadQueue[load_idx]->readPC());
960
961 incrLdIdx(load_idx);
962 }
963
964 cprintf("Store queue size: %i\n", stores);
965 cprintf("Store queue: ");
966
967 int store_idx = storeHead;
968
969 while (store_idx != storeTail && storeQueue[store_idx].inst) {
970 cprintf("%#x ", storeQueue[store_idx].inst->readPC());
971
972 incrStIdx(store_idx);
973 }
974
975 cprintf("\n");
976}
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