35#include "mem/request.hh"
36
37template<class Impl>
38LSQUnit<Impl>::WritebackEvent::WritebackEvent(DynInstPtr &_inst, PacketPtr _pkt,
39 LSQUnit *lsq_ptr)
40 : Event(&mainEventQueue), inst(_inst), pkt(_pkt), lsqPtr(lsq_ptr)
41{
42 this->setFlags(Event::AutoDelete);
43}
44
45template<class Impl>
46void
47LSQUnit<Impl>::WritebackEvent::process()
48{
49 if (!lsqPtr->isSwitchedOut()) {
50 lsqPtr->writeback(inst, pkt);
51 }
52 delete pkt;
53}
54
55template<class Impl>
56const char *
57LSQUnit<Impl>::WritebackEvent::description()
58{
59 return "Store writeback event";
60}
61
62template<class Impl>
63void
64LSQUnit<Impl>::completeDataAccess(PacketPtr pkt)
65{
66 LSQSenderState *state = dynamic_cast<LSQSenderState *>(pkt->senderState);
67 DynInstPtr inst = state->inst;
68 DPRINTF(IEW, "Writeback event [sn:%lli]\n", inst->seqNum);
69 DPRINTF(Activity, "Activity: Writeback event [sn:%lli]\n", inst->seqNum);
70
71 //iewStage->ldstQueue.removeMSHR(inst->threadNumber,inst->seqNum);
72
73 if (isSwitchedOut() || inst->isSquashed()) {
74 delete state;
75 delete pkt;
76 return;
77 } else {
78 if (!state->noWB) {
79 writeback(inst, pkt);
80 }
81
82 if (inst->isStore()) {
83 completeStore(state->idx);
84 }
85 }
86
87 delete state;
88 delete pkt;
89}
90
91template <class Impl>
92Tick
93LSQUnit<Impl>::DcachePort::recvAtomic(PacketPtr pkt)
94{
95 panic("O3CPU model does not work with atomic mode!");
96 return curTick;
97}
98
99template <class Impl>
100void
101LSQUnit<Impl>::DcachePort::recvFunctional(PacketPtr pkt)
102{
103 panic("O3CPU doesn't expect recvFunctional callback!");
104}
105
106template <class Impl>
107void
108LSQUnit<Impl>::DcachePort::recvStatusChange(Status status)
109{
110 if (status == RangeChange)
111 return;
112
113 panic("O3CPU doesn't expect recvStatusChange callback!");
114}
115
116template <class Impl>
117bool
118LSQUnit<Impl>::DcachePort::recvTiming(PacketPtr pkt)
119{
120 lsq->completeDataAccess(pkt);
121 return true;
122}
123
124template <class Impl>
125void
126LSQUnit<Impl>::DcachePort::recvRetry()
127{
128 lsq->recvRetry();
129}
130
131template <class Impl>
132LSQUnit<Impl>::LSQUnit()
133 : loads(0), stores(0), storesToWB(0), stalled(false),
134 isStoreBlocked(false), isLoadBlocked(false),
135 loadBlockedHandled(false)
136{
137}
138
139template<class Impl>
140void
141LSQUnit<Impl>::init(Params *params, unsigned maxLQEntries,
142 unsigned maxSQEntries, unsigned id)
143{
144 DPRINTF(LSQUnit, "Creating LSQUnit%i object.\n",id);
145
146 switchedOut = false;
147
148 lsqID = id;
149
150 // Add 1 for the sentinel entry (they are circular queues).
151 LQEntries = maxLQEntries + 1;
152 SQEntries = maxSQEntries + 1;
153
154 loadQueue.resize(LQEntries);
155 storeQueue.resize(SQEntries);
156
157 loadHead = loadTail = 0;
158
159 storeHead = storeWBIdx = storeTail = 0;
160
161 usedPorts = 0;
162 cachePorts = params->cachePorts;
163
164 mem = params->mem;
165
166 memDepViolator = NULL;
167
168 blockedLoadSeqNum = 0;
169}
170
171template<class Impl>
172void
173LSQUnit<Impl>::setCPU(FullCPU *cpu_ptr)
174{
175 cpu = cpu_ptr;
176 dcachePort = new DcachePort(cpu, this);
177
178 Port *mem_dport = mem->getPort("");
179 dcachePort->setPeer(mem_dport);
180 mem_dport->setPeer(dcachePort);
181
182 if (cpu->checker) {
183 cpu->checker->setDcachePort(dcachePort);
184 }
185}
186
187template<class Impl>
188std::string
189LSQUnit<Impl>::name() const
190{
191 if (Impl::MaxThreads == 1) {
192 return iewStage->name() + ".lsq";
193 } else {
194 return iewStage->name() + ".lsq.thread." + to_string(lsqID);
195 }
196}
197
198template<class Impl>
199void
200LSQUnit<Impl>::clearLQ()
201{
202 loadQueue.clear();
203}
204
205template<class Impl>
206void
207LSQUnit<Impl>::clearSQ()
208{
209 storeQueue.clear();
210}
211
212template<class Impl>
213void
214LSQUnit<Impl>::switchOut()
215{
216 switchedOut = true;
217 for (int i = 0; i < loadQueue.size(); ++i)
218 loadQueue[i] = NULL;
219
220 assert(storesToWB == 0);
221}
222
223template<class Impl>
224void
225LSQUnit<Impl>::takeOverFrom()
226{
227 switchedOut = false;
228 loads = stores = storesToWB = 0;
229
230 loadHead = loadTail = 0;
231
232 storeHead = storeWBIdx = storeTail = 0;
233
234 usedPorts = 0;
235
236 memDepViolator = NULL;
237
238 blockedLoadSeqNum = 0;
239
240 stalled = false;
241 isLoadBlocked = false;
242 loadBlockedHandled = false;
243}
244
245template<class Impl>
246void
247LSQUnit<Impl>::resizeLQ(unsigned size)
248{
249 unsigned size_plus_sentinel = size + 1;
250 assert(size_plus_sentinel >= LQEntries);
251
252 if (size_plus_sentinel > LQEntries) {
253 while (size_plus_sentinel > loadQueue.size()) {
254 DynInstPtr dummy;
255 loadQueue.push_back(dummy);
256 LQEntries++;
257 }
258 } else {
259 LQEntries = size_plus_sentinel;
260 }
261
262}
263
264template<class Impl>
265void
266LSQUnit<Impl>::resizeSQ(unsigned size)
267{
268 unsigned size_plus_sentinel = size + 1;
269 if (size_plus_sentinel > SQEntries) {
270 while (size_plus_sentinel > storeQueue.size()) {
271 SQEntry dummy;
272 storeQueue.push_back(dummy);
273 SQEntries++;
274 }
275 } else {
276 SQEntries = size_plus_sentinel;
277 }
278}
279
280template <class Impl>
281void
282LSQUnit<Impl>::insert(DynInstPtr &inst)
283{
284 assert(inst->isMemRef());
285
286 assert(inst->isLoad() || inst->isStore());
287
288 if (inst->isLoad()) {
289 insertLoad(inst);
290 } else {
291 insertStore(inst);
292 }
293
294 inst->setInLSQ();
295}
296
297template <class Impl>
298void
299LSQUnit<Impl>::insertLoad(DynInstPtr &load_inst)
300{
301 assert((loadTail + 1) % LQEntries != loadHead);
302 assert(loads < LQEntries);
303
304 DPRINTF(LSQUnit, "Inserting load PC %#x, idx:%i [sn:%lli]\n",
305 load_inst->readPC(), loadTail, load_inst->seqNum);
306
307 load_inst->lqIdx = loadTail;
308
309 if (stores == 0) {
310 load_inst->sqIdx = -1;
311 } else {
312 load_inst->sqIdx = storeTail;
313 }
314
315 loadQueue[loadTail] = load_inst;
316
317 incrLdIdx(loadTail);
318
319 ++loads;
320}
321
322template <class Impl>
323void
324LSQUnit<Impl>::insertStore(DynInstPtr &store_inst)
325{
326 // Make sure it is not full before inserting an instruction.
327 assert((storeTail + 1) % SQEntries != storeHead);
328 assert(stores < SQEntries);
329
330 DPRINTF(LSQUnit, "Inserting store PC %#x, idx:%i [sn:%lli]\n",
331 store_inst->readPC(), storeTail, store_inst->seqNum);
332
333 store_inst->sqIdx = storeTail;
334 store_inst->lqIdx = loadTail;
335
336 storeQueue[storeTail] = SQEntry(store_inst);
337
338 incrStIdx(storeTail);
339
340 ++stores;
341}
342
343template <class Impl>
344typename Impl::DynInstPtr
345LSQUnit<Impl>::getMemDepViolator()
346{
347 DynInstPtr temp = memDepViolator;
348
349 memDepViolator = NULL;
350
351 return temp;
352}
353
354template <class Impl>
355unsigned
356LSQUnit<Impl>::numFreeEntries()
357{
358 unsigned free_lq_entries = LQEntries - loads;
359 unsigned free_sq_entries = SQEntries - stores;
360
361 // Both the LQ and SQ entries have an extra dummy entry to differentiate
362 // empty/full conditions. Subtract 1 from the free entries.
363 if (free_lq_entries < free_sq_entries) {
364 return free_lq_entries - 1;
365 } else {
366 return free_sq_entries - 1;
367 }
368}
369
370template <class Impl>
371int
372LSQUnit<Impl>::numLoadsReady()
373{
374 int load_idx = loadHead;
375 int retval = 0;
376
377 while (load_idx != loadTail) {
378 assert(loadQueue[load_idx]);
379
380 if (loadQueue[load_idx]->readyToIssue()) {
381 ++retval;
382 }
383 }
384
385 return retval;
386}
387
388template <class Impl>
389Fault
390LSQUnit<Impl>::executeLoad(DynInstPtr &inst)
391{
392 // Execute a specific load.
393 Fault load_fault = NoFault;
394
395 DPRINTF(LSQUnit, "Executing load PC %#x, [sn:%lli]\n",
396 inst->readPC(),inst->seqNum);
397
398 load_fault = inst->initiateAcc();
399
400 // If the instruction faulted, then we need to send it along to commit
401 // without the instruction completing.
402 if (load_fault != NoFault) {
403 // Send this instruction to commit, also make sure iew stage
404 // realizes there is activity.
405 iewStage->instToCommit(inst);
406 iewStage->activityThisCycle();
407 }
408
409 return load_fault;
410}
411
412template <class Impl>
413Fault
414LSQUnit<Impl>::executeStore(DynInstPtr &store_inst)
415{
416 using namespace TheISA;
417 // Make sure that a store exists.
418 assert(stores != 0);
419
420 int store_idx = store_inst->sqIdx;
421
422 DPRINTF(LSQUnit, "Executing store PC %#x [sn:%lli]\n",
423 store_inst->readPC(), store_inst->seqNum);
424
425 // Check the recently completed loads to see if any match this store's
426 // address. If so, then we have a memory ordering violation.
427 int load_idx = store_inst->lqIdx;
428
429 Fault store_fault = store_inst->initiateAcc();
430
431 if (storeQueue[store_idx].size == 0) {
432 DPRINTF(LSQUnit,"Fault on Store PC %#x, [sn:%lli],Size = 0\n",
433 store_inst->readPC(),store_inst->seqNum);
434
435 return store_fault;
436 }
437
438 assert(store_fault == NoFault);
439
440 if (store_inst->isStoreConditional()) {
441 // Store conditionals need to set themselves as able to
442 // writeback if we haven't had a fault by here.
443 storeQueue[store_idx].canWB = true;
444
445 ++storesToWB;
446 }
447
448 if (!memDepViolator) {
449 while (load_idx != loadTail) {
450 // Really only need to check loads that have actually executed
451 // It's safe to check all loads because effAddr is set to
452 // InvalAddr when the dyn inst is created.
453
454 // @todo: For now this is extra conservative, detecting a
455 // violation if the addresses match assuming all accesses
456 // are quad word accesses.
457
458 // @todo: Fix this, magic number being used here
459 if ((loadQueue[load_idx]->effAddr >> 8) ==
460 (store_inst->effAddr >> 8)) {
461 // A load incorrectly passed this store. Squash and refetch.
462 // For now return a fault to show that it was unsuccessful.
463 memDepViolator = loadQueue[load_idx];
464
465 return genMachineCheckFault();
466 }
467
468 incrLdIdx(load_idx);
469 }
470
471 // If we've reached this point, there was no violation.
472 memDepViolator = NULL;
473 }
474
475 return store_fault;
476}
477
478template <class Impl>
479void
480LSQUnit<Impl>::commitLoad()
481{
482 assert(loadQueue[loadHead]);
483
484 DPRINTF(LSQUnit, "Committing head load instruction, PC %#x\n",
485 loadQueue[loadHead]->readPC());
486
487 loadQueue[loadHead] = NULL;
488
489 incrLdIdx(loadHead);
490
491 --loads;
492}
493
494template <class Impl>
495void
496LSQUnit<Impl>::commitLoads(InstSeqNum &youngest_inst)
497{
498 assert(loads == 0 || loadQueue[loadHead]);
499
500 while (loads != 0 && loadQueue[loadHead]->seqNum <= youngest_inst) {
501 commitLoad();
502 }
503}
504
505template <class Impl>
506void
507LSQUnit<Impl>::commitStores(InstSeqNum &youngest_inst)
508{
509 assert(stores == 0 || storeQueue[storeHead].inst);
510
511 int store_idx = storeHead;
512
513 while (store_idx != storeTail) {
514 assert(storeQueue[store_idx].inst);
515 // Mark any stores that are now committed and have not yet
516 // been marked as able to write back.
517 if (!storeQueue[store_idx].canWB) {
518 if (storeQueue[store_idx].inst->seqNum > youngest_inst) {
519 break;
520 }
521 DPRINTF(LSQUnit, "Marking store as able to write back, PC "
522 "%#x [sn:%lli]\n",
523 storeQueue[store_idx].inst->readPC(),
524 storeQueue[store_idx].inst->seqNum);
525
526 storeQueue[store_idx].canWB = true;
527
528 ++storesToWB;
529 }
530
531 incrStIdx(store_idx);
532 }
533}
534
535template <class Impl>
536void
537LSQUnit<Impl>::writebackStores()
538{
539 while (storesToWB > 0 &&
540 storeWBIdx != storeTail &&
541 storeQueue[storeWBIdx].inst &&
542 storeQueue[storeWBIdx].canWB &&
543 usedPorts < cachePorts) {
544
545 if (isStoreBlocked) {
546 DPRINTF(LSQUnit, "Unable to write back any more stores, cache"
547 " is blocked!\n");
548 break;
549 }
550
551 // Store didn't write any data so no need to write it back to
552 // memory.
553 if (storeQueue[storeWBIdx].size == 0) {
554 completeStore(storeWBIdx);
555
556 incrStIdx(storeWBIdx);
557
558 continue;
559 }
560
561 ++usedPorts;
562
563 if (storeQueue[storeWBIdx].inst->isDataPrefetch()) {
564 incrStIdx(storeWBIdx);
565
566 continue;
567 }
568
569 assert(storeQueue[storeWBIdx].req);
570 assert(!storeQueue[storeWBIdx].committed);
571
572 DynInstPtr inst = storeQueue[storeWBIdx].inst;
573
574 Request *req = storeQueue[storeWBIdx].req;
575 storeQueue[storeWBIdx].committed = true;
576
577 assert(!inst->memData);
578 inst->memData = new uint8_t[64];
579 memcpy(inst->memData, (uint8_t *)&storeQueue[storeWBIdx].data,
580 req->getSize());
581
582 PacketPtr data_pkt = new Packet(req, Packet::WriteReq, Packet::Broadcast);
583 data_pkt->dataStatic(inst->memData);
584
585 LSQSenderState *state = new LSQSenderState;
586 state->isLoad = false;
587 state->idx = storeWBIdx;
588 state->inst = inst;
589 data_pkt->senderState = state;
590
591 DPRINTF(LSQUnit, "D-Cache: Writing back store idx:%i PC:%#x "
592 "to Addr:%#x, data:%#x [sn:%lli]\n",
593 storeWBIdx, storeQueue[storeWBIdx].inst->readPC(),
594 req->getPaddr(), *(inst->memData),
595 storeQueue[storeWBIdx].inst->seqNum);
596
597 // @todo: Remove this SC hack once the memory system handles it.
598 if (req->getFlags() & LOCKED) {
599 if (req->getFlags() & UNCACHEABLE) {
600 req->setScResult(2);
601 } else {
602 if (cpu->lockFlag) {
603 req->setScResult(1);
604 } else {
605 req->setScResult(0);
606 // Hack: Instantly complete this store.
607 completeDataAccess(data_pkt);
608 incrStIdx(storeWBIdx);
609 continue;
610 }
611 }
612 } else {
613 // Non-store conditionals do not need a writeback.
614 state->noWB = true;
615 }
616
617 if (!dcachePort->sendTiming(data_pkt)) {
618 // Need to handle becoming blocked on a store.
619 isStoreBlocked = true;
620
621 assert(retryPkt == NULL);
622 retryPkt = data_pkt;
623 } else {
624 storePostSend(data_pkt);
625 }
626 }
627
628 // Not sure this should set it to 0.
629 usedPorts = 0;
630
631 assert(stores >= 0 && storesToWB >= 0);
632}
633
634/*template <class Impl>
635void
636LSQUnit<Impl>::removeMSHR(InstSeqNum seqNum)
637{
638 list<InstSeqNum>::iterator mshr_it = find(mshrSeqNums.begin(),
639 mshrSeqNums.end(),
640 seqNum);
641
642 if (mshr_it != mshrSeqNums.end()) {
643 mshrSeqNums.erase(mshr_it);
644 DPRINTF(LSQUnit, "Removing MSHR. count = %i\n",mshrSeqNums.size());
645 }
646}*/
647
648template <class Impl>
649void
650LSQUnit<Impl>::squash(const InstSeqNum &squashed_num)
651{
652 DPRINTF(LSQUnit, "Squashing until [sn:%lli]!"
653 "(Loads:%i Stores:%i)\n", squashed_num, loads, stores);
654
655 int load_idx = loadTail;
656 decrLdIdx(load_idx);
657
658 while (loads != 0 && loadQueue[load_idx]->seqNum > squashed_num) {
659 DPRINTF(LSQUnit,"Load Instruction PC %#x squashed, "
660 "[sn:%lli]\n",
661 loadQueue[load_idx]->readPC(),
662 loadQueue[load_idx]->seqNum);
663
664 if (isStalled() && load_idx == stallingLoadIdx) {
665 stalled = false;
666 stallingStoreIsn = 0;
667 stallingLoadIdx = 0;
668 }
669
670 // Clear the smart pointer to make sure it is decremented.
671 loadQueue[load_idx]->squashed = true;
672 loadQueue[load_idx] = NULL;
673 --loads;
674
675 // Inefficient!
676 loadTail = load_idx;
677
678 decrLdIdx(load_idx);
679 }
680
681 if (isLoadBlocked) {
682 if (squashed_num < blockedLoadSeqNum) {
683 isLoadBlocked = false;
684 loadBlockedHandled = false;
685 blockedLoadSeqNum = 0;
686 }
687 }
688
689 int store_idx = storeTail;
690 decrStIdx(store_idx);
691
692 while (stores != 0 &&
693 storeQueue[store_idx].inst->seqNum > squashed_num) {
694 // Instructions marked as can WB are already committed.
695 if (storeQueue[store_idx].canWB) {
696 break;
697 }
698
699 DPRINTF(LSQUnit,"Store Instruction PC %#x squashed, "
700 "idx:%i [sn:%lli]\n",
701 storeQueue[store_idx].inst->readPC(),
702 store_idx, storeQueue[store_idx].inst->seqNum);
703
704 // I don't think this can happen. It should have been cleared
705 // by the stalling load.
706 if (isStalled() &&
707 storeQueue[store_idx].inst->seqNum == stallingStoreIsn) {
708 panic("Is stalled should have been cleared by stalling load!\n");
709 stalled = false;
710 stallingStoreIsn = 0;
711 }
712
713 // Clear the smart pointer to make sure it is decremented.
714 storeQueue[store_idx].inst->squashed = true;
715 storeQueue[store_idx].inst = NULL;
716 storeQueue[store_idx].canWB = 0;
717
718 storeQueue[store_idx].req = NULL;
719 --stores;
720
721 // Inefficient!
722 storeTail = store_idx;
723
724 decrStIdx(store_idx);
725 }
726}
727
728template <class Impl>
729void
730LSQUnit<Impl>::storePostSend(Packet *pkt)
731{
732 if (isStalled() &&
733 storeQueue[storeWBIdx].inst->seqNum == stallingStoreIsn) {
734 DPRINTF(LSQUnit, "Unstalling, stalling store [sn:%lli] "
735 "load idx:%i\n",
736 stallingStoreIsn, stallingLoadIdx);
737 stalled = false;
738 stallingStoreIsn = 0;
739 iewStage->replayMemInst(loadQueue[stallingLoadIdx]);
740 }
741
742 if (!storeQueue[storeWBIdx].inst->isStoreConditional()) {
743 // The store is basically completed at this time. This
744 // only works so long as the checker doesn't try to
745 // verify the value in memory for stores.
746 storeQueue[storeWBIdx].inst->setCompleted();
747 if (cpu->checker) {
748 cpu->checker->tick(storeQueue[storeWBIdx].inst);
749 }
750 }
751
752 if (pkt->result != Packet::Success) {
753 DPRINTF(LSQUnit,"D-Cache Write Miss on idx:%i!\n",
754 storeWBIdx);
755
756 DPRINTF(Activity, "Active st accessing mem miss [sn:%lli]\n",
757 storeQueue[storeWBIdx].inst->seqNum);
758
759 //mshrSeqNums.push_back(storeQueue[storeWBIdx].inst->seqNum);
760
761 //DPRINTF(LSQUnit, "Added MSHR. count = %i\n",mshrSeqNums.size());
762
763 // @todo: Increment stat here.
764 } else {
765 DPRINTF(LSQUnit,"D-Cache: Write Hit on idx:%i !\n",
766 storeWBIdx);
767
768 DPRINTF(Activity, "Active st accessing mem hit [sn:%lli]\n",
769 storeQueue[storeWBIdx].inst->seqNum);
770 }
771
772 incrStIdx(storeWBIdx);
773}
774
775template <class Impl>
776void
777LSQUnit<Impl>::writeback(DynInstPtr &inst, PacketPtr pkt)
778{
779 iewStage->wakeCPU();
780
781 // Squashed instructions do not need to complete their access.
782 if (inst->isSquashed()) {
783 assert(!inst->isStore());
784 return;
785 }
786
787 if (!inst->isExecuted()) {
788 inst->setExecuted();
789
790 // Complete access to copy data to proper place.
791 inst->completeAcc(pkt);
792 }
793
794 // Need to insert instruction into queue to commit
795 iewStage->instToCommit(inst);
796
797 iewStage->activityThisCycle();
798}
799
800template <class Impl>
801void
802LSQUnit<Impl>::completeStore(int store_idx)
803{
804 assert(storeQueue[store_idx].inst);
805 storeQueue[store_idx].completed = true;
806 --storesToWB;
807 // A bit conservative because a store completion may not free up entries,
808 // but hopefully avoids two store completions in one cycle from making
809 // the CPU tick twice.
810 cpu->activityThisCycle();
811
812 if (store_idx == storeHead) {
813 do {
814 incrStIdx(storeHead);
815
816 --stores;
817 } while (storeQueue[storeHead].completed &&
818 storeHead != storeTail);
819
820 iewStage->updateLSQNextCycle = true;
821 }
822
823 DPRINTF(LSQUnit, "Completing store [sn:%lli], idx:%i, store head "
824 "idx:%i\n",
825 storeQueue[store_idx].inst->seqNum, store_idx, storeHead);
826
827 if (isStalled() &&
828 storeQueue[store_idx].inst->seqNum == stallingStoreIsn) {
829 DPRINTF(LSQUnit, "Unstalling, stalling store [sn:%lli] "
830 "load idx:%i\n",
831 stallingStoreIsn, stallingLoadIdx);
832 stalled = false;
833 stallingStoreIsn = 0;
834 iewStage->replayMemInst(loadQueue[stallingLoadIdx]);
835 }
836
837 storeQueue[store_idx].inst->setCompleted();
838
839 // Tell the checker we've completed this instruction. Some stores
840 // may get reported twice to the checker, but the checker can
841 // handle that case.
842 if (cpu->checker) {
843 cpu->checker->tick(storeQueue[store_idx].inst);
844 }
845}
846
847template <class Impl>
848void
849LSQUnit<Impl>::recvRetry()
850{
851 if (isStoreBlocked) {
852 assert(retryPkt != NULL);
853
854 if (dcachePort->sendTiming(retryPkt)) {
855 storePostSend(retryPkt);
856 retryPkt = NULL;
857 isStoreBlocked = false;
858 } else {
859 // Still blocked!
860 }
861 } else if (isLoadBlocked) {
862 DPRINTF(LSQUnit, "Loads squash themselves and all younger insts, "
863 "no need to resend packet.\n");
864 } else {
865 DPRINTF(LSQUnit, "Retry received but LSQ is no longer blocked.\n");
866 }
867}
868
869template <class Impl>
870inline void
871LSQUnit<Impl>::incrStIdx(int &store_idx)
872{
873 if (++store_idx >= SQEntries)
874 store_idx = 0;
875}
876
877template <class Impl>
878inline void
879LSQUnit<Impl>::decrStIdx(int &store_idx)
880{
881 if (--store_idx < 0)
882 store_idx += SQEntries;
883}
884
885template <class Impl>
886inline void
887LSQUnit<Impl>::incrLdIdx(int &load_idx)
888{
889 if (++load_idx >= LQEntries)
890 load_idx = 0;
891}
892
893template <class Impl>
894inline void
895LSQUnit<Impl>::decrLdIdx(int &load_idx)
896{
897 if (--load_idx < 0)
898 load_idx += LQEntries;
899}
900
901template <class Impl>
902void
903LSQUnit<Impl>::dumpInsts()
904{
905 cprintf("Load store queue: Dumping instructions.\n");
906 cprintf("Load queue size: %i\n", loads);
907 cprintf("Load queue: ");
908
909 int load_idx = loadHead;
910
911 while (load_idx != loadTail && loadQueue[load_idx]) {
912 cprintf("%#x ", loadQueue[load_idx]->readPC());
913
914 incrLdIdx(load_idx);
915 }
916
917 cprintf("Store queue size: %i\n", stores);
918 cprintf("Store queue: ");
919
920 int store_idx = storeHead;
921
922 while (store_idx != storeTail && storeQueue[store_idx].inst) {
923 cprintf("%#x ", storeQueue[store_idx].inst->readPC());
924
925 incrStIdx(store_idx);
926 }
927
928 cprintf("\n");
929}
| 36#include "mem/request.hh"
37
38template<class Impl>
39LSQUnit<Impl>::WritebackEvent::WritebackEvent(DynInstPtr &_inst, PacketPtr _pkt,
40 LSQUnit *lsq_ptr)
41 : Event(&mainEventQueue), inst(_inst), pkt(_pkt), lsqPtr(lsq_ptr)
42{
43 this->setFlags(Event::AutoDelete);
44}
45
46template<class Impl>
47void
48LSQUnit<Impl>::WritebackEvent::process()
49{
50 if (!lsqPtr->isSwitchedOut()) {
51 lsqPtr->writeback(inst, pkt);
52 }
53 delete pkt;
54}
55
56template<class Impl>
57const char *
58LSQUnit<Impl>::WritebackEvent::description()
59{
60 return "Store writeback event";
61}
62
63template<class Impl>
64void
65LSQUnit<Impl>::completeDataAccess(PacketPtr pkt)
66{
67 LSQSenderState *state = dynamic_cast<LSQSenderState *>(pkt->senderState);
68 DynInstPtr inst = state->inst;
69 DPRINTF(IEW, "Writeback event [sn:%lli]\n", inst->seqNum);
70 DPRINTF(Activity, "Activity: Writeback event [sn:%lli]\n", inst->seqNum);
71
72 //iewStage->ldstQueue.removeMSHR(inst->threadNumber,inst->seqNum);
73
74 if (isSwitchedOut() || inst->isSquashed()) {
75 delete state;
76 delete pkt;
77 return;
78 } else {
79 if (!state->noWB) {
80 writeback(inst, pkt);
81 }
82
83 if (inst->isStore()) {
84 completeStore(state->idx);
85 }
86 }
87
88 delete state;
89 delete pkt;
90}
91
92template <class Impl>
93Tick
94LSQUnit<Impl>::DcachePort::recvAtomic(PacketPtr pkt)
95{
96 panic("O3CPU model does not work with atomic mode!");
97 return curTick;
98}
99
100template <class Impl>
101void
102LSQUnit<Impl>::DcachePort::recvFunctional(PacketPtr pkt)
103{
104 panic("O3CPU doesn't expect recvFunctional callback!");
105}
106
107template <class Impl>
108void
109LSQUnit<Impl>::DcachePort::recvStatusChange(Status status)
110{
111 if (status == RangeChange)
112 return;
113
114 panic("O3CPU doesn't expect recvStatusChange callback!");
115}
116
117template <class Impl>
118bool
119LSQUnit<Impl>::DcachePort::recvTiming(PacketPtr pkt)
120{
121 lsq->completeDataAccess(pkt);
122 return true;
123}
124
125template <class Impl>
126void
127LSQUnit<Impl>::DcachePort::recvRetry()
128{
129 lsq->recvRetry();
130}
131
132template <class Impl>
133LSQUnit<Impl>::LSQUnit()
134 : loads(0), stores(0), storesToWB(0), stalled(false),
135 isStoreBlocked(false), isLoadBlocked(false),
136 loadBlockedHandled(false)
137{
138}
139
140template<class Impl>
141void
142LSQUnit<Impl>::init(Params *params, unsigned maxLQEntries,
143 unsigned maxSQEntries, unsigned id)
144{
145 DPRINTF(LSQUnit, "Creating LSQUnit%i object.\n",id);
146
147 switchedOut = false;
148
149 lsqID = id;
150
151 // Add 1 for the sentinel entry (they are circular queues).
152 LQEntries = maxLQEntries + 1;
153 SQEntries = maxSQEntries + 1;
154
155 loadQueue.resize(LQEntries);
156 storeQueue.resize(SQEntries);
157
158 loadHead = loadTail = 0;
159
160 storeHead = storeWBIdx = storeTail = 0;
161
162 usedPorts = 0;
163 cachePorts = params->cachePorts;
164
165 mem = params->mem;
166
167 memDepViolator = NULL;
168
169 blockedLoadSeqNum = 0;
170}
171
172template<class Impl>
173void
174LSQUnit<Impl>::setCPU(FullCPU *cpu_ptr)
175{
176 cpu = cpu_ptr;
177 dcachePort = new DcachePort(cpu, this);
178
179 Port *mem_dport = mem->getPort("");
180 dcachePort->setPeer(mem_dport);
181 mem_dport->setPeer(dcachePort);
182
183 if (cpu->checker) {
184 cpu->checker->setDcachePort(dcachePort);
185 }
186}
187
188template<class Impl>
189std::string
190LSQUnit<Impl>::name() const
191{
192 if (Impl::MaxThreads == 1) {
193 return iewStage->name() + ".lsq";
194 } else {
195 return iewStage->name() + ".lsq.thread." + to_string(lsqID);
196 }
197}
198
199template<class Impl>
200void
201LSQUnit<Impl>::clearLQ()
202{
203 loadQueue.clear();
204}
205
206template<class Impl>
207void
208LSQUnit<Impl>::clearSQ()
209{
210 storeQueue.clear();
211}
212
213template<class Impl>
214void
215LSQUnit<Impl>::switchOut()
216{
217 switchedOut = true;
218 for (int i = 0; i < loadQueue.size(); ++i)
219 loadQueue[i] = NULL;
220
221 assert(storesToWB == 0);
222}
223
224template<class Impl>
225void
226LSQUnit<Impl>::takeOverFrom()
227{
228 switchedOut = false;
229 loads = stores = storesToWB = 0;
230
231 loadHead = loadTail = 0;
232
233 storeHead = storeWBIdx = storeTail = 0;
234
235 usedPorts = 0;
236
237 memDepViolator = NULL;
238
239 blockedLoadSeqNum = 0;
240
241 stalled = false;
242 isLoadBlocked = false;
243 loadBlockedHandled = false;
244}
245
246template<class Impl>
247void
248LSQUnit<Impl>::resizeLQ(unsigned size)
249{
250 unsigned size_plus_sentinel = size + 1;
251 assert(size_plus_sentinel >= LQEntries);
252
253 if (size_plus_sentinel > LQEntries) {
254 while (size_plus_sentinel > loadQueue.size()) {
255 DynInstPtr dummy;
256 loadQueue.push_back(dummy);
257 LQEntries++;
258 }
259 } else {
260 LQEntries = size_plus_sentinel;
261 }
262
263}
264
265template<class Impl>
266void
267LSQUnit<Impl>::resizeSQ(unsigned size)
268{
269 unsigned size_plus_sentinel = size + 1;
270 if (size_plus_sentinel > SQEntries) {
271 while (size_plus_sentinel > storeQueue.size()) {
272 SQEntry dummy;
273 storeQueue.push_back(dummy);
274 SQEntries++;
275 }
276 } else {
277 SQEntries = size_plus_sentinel;
278 }
279}
280
281template <class Impl>
282void
283LSQUnit<Impl>::insert(DynInstPtr &inst)
284{
285 assert(inst->isMemRef());
286
287 assert(inst->isLoad() || inst->isStore());
288
289 if (inst->isLoad()) {
290 insertLoad(inst);
291 } else {
292 insertStore(inst);
293 }
294
295 inst->setInLSQ();
296}
297
298template <class Impl>
299void
300LSQUnit<Impl>::insertLoad(DynInstPtr &load_inst)
301{
302 assert((loadTail + 1) % LQEntries != loadHead);
303 assert(loads < LQEntries);
304
305 DPRINTF(LSQUnit, "Inserting load PC %#x, idx:%i [sn:%lli]\n",
306 load_inst->readPC(), loadTail, load_inst->seqNum);
307
308 load_inst->lqIdx = loadTail;
309
310 if (stores == 0) {
311 load_inst->sqIdx = -1;
312 } else {
313 load_inst->sqIdx = storeTail;
314 }
315
316 loadQueue[loadTail] = load_inst;
317
318 incrLdIdx(loadTail);
319
320 ++loads;
321}
322
323template <class Impl>
324void
325LSQUnit<Impl>::insertStore(DynInstPtr &store_inst)
326{
327 // Make sure it is not full before inserting an instruction.
328 assert((storeTail + 1) % SQEntries != storeHead);
329 assert(stores < SQEntries);
330
331 DPRINTF(LSQUnit, "Inserting store PC %#x, idx:%i [sn:%lli]\n",
332 store_inst->readPC(), storeTail, store_inst->seqNum);
333
334 store_inst->sqIdx = storeTail;
335 store_inst->lqIdx = loadTail;
336
337 storeQueue[storeTail] = SQEntry(store_inst);
338
339 incrStIdx(storeTail);
340
341 ++stores;
342}
343
344template <class Impl>
345typename Impl::DynInstPtr
346LSQUnit<Impl>::getMemDepViolator()
347{
348 DynInstPtr temp = memDepViolator;
349
350 memDepViolator = NULL;
351
352 return temp;
353}
354
355template <class Impl>
356unsigned
357LSQUnit<Impl>::numFreeEntries()
358{
359 unsigned free_lq_entries = LQEntries - loads;
360 unsigned free_sq_entries = SQEntries - stores;
361
362 // Both the LQ and SQ entries have an extra dummy entry to differentiate
363 // empty/full conditions. Subtract 1 from the free entries.
364 if (free_lq_entries < free_sq_entries) {
365 return free_lq_entries - 1;
366 } else {
367 return free_sq_entries - 1;
368 }
369}
370
371template <class Impl>
372int
373LSQUnit<Impl>::numLoadsReady()
374{
375 int load_idx = loadHead;
376 int retval = 0;
377
378 while (load_idx != loadTail) {
379 assert(loadQueue[load_idx]);
380
381 if (loadQueue[load_idx]->readyToIssue()) {
382 ++retval;
383 }
384 }
385
386 return retval;
387}
388
389template <class Impl>
390Fault
391LSQUnit<Impl>::executeLoad(DynInstPtr &inst)
392{
393 // Execute a specific load.
394 Fault load_fault = NoFault;
395
396 DPRINTF(LSQUnit, "Executing load PC %#x, [sn:%lli]\n",
397 inst->readPC(),inst->seqNum);
398
399 load_fault = inst->initiateAcc();
400
401 // If the instruction faulted, then we need to send it along to commit
402 // without the instruction completing.
403 if (load_fault != NoFault) {
404 // Send this instruction to commit, also make sure iew stage
405 // realizes there is activity.
406 iewStage->instToCommit(inst);
407 iewStage->activityThisCycle();
408 }
409
410 return load_fault;
411}
412
413template <class Impl>
414Fault
415LSQUnit<Impl>::executeStore(DynInstPtr &store_inst)
416{
417 using namespace TheISA;
418 // Make sure that a store exists.
419 assert(stores != 0);
420
421 int store_idx = store_inst->sqIdx;
422
423 DPRINTF(LSQUnit, "Executing store PC %#x [sn:%lli]\n",
424 store_inst->readPC(), store_inst->seqNum);
425
426 // Check the recently completed loads to see if any match this store's
427 // address. If so, then we have a memory ordering violation.
428 int load_idx = store_inst->lqIdx;
429
430 Fault store_fault = store_inst->initiateAcc();
431
432 if (storeQueue[store_idx].size == 0) {
433 DPRINTF(LSQUnit,"Fault on Store PC %#x, [sn:%lli],Size = 0\n",
434 store_inst->readPC(),store_inst->seqNum);
435
436 return store_fault;
437 }
438
439 assert(store_fault == NoFault);
440
441 if (store_inst->isStoreConditional()) {
442 // Store conditionals need to set themselves as able to
443 // writeback if we haven't had a fault by here.
444 storeQueue[store_idx].canWB = true;
445
446 ++storesToWB;
447 }
448
449 if (!memDepViolator) {
450 while (load_idx != loadTail) {
451 // Really only need to check loads that have actually executed
452 // It's safe to check all loads because effAddr is set to
453 // InvalAddr when the dyn inst is created.
454
455 // @todo: For now this is extra conservative, detecting a
456 // violation if the addresses match assuming all accesses
457 // are quad word accesses.
458
459 // @todo: Fix this, magic number being used here
460 if ((loadQueue[load_idx]->effAddr >> 8) ==
461 (store_inst->effAddr >> 8)) {
462 // A load incorrectly passed this store. Squash and refetch.
463 // For now return a fault to show that it was unsuccessful.
464 memDepViolator = loadQueue[load_idx];
465
466 return genMachineCheckFault();
467 }
468
469 incrLdIdx(load_idx);
470 }
471
472 // If we've reached this point, there was no violation.
473 memDepViolator = NULL;
474 }
475
476 return store_fault;
477}
478
479template <class Impl>
480void
481LSQUnit<Impl>::commitLoad()
482{
483 assert(loadQueue[loadHead]);
484
485 DPRINTF(LSQUnit, "Committing head load instruction, PC %#x\n",
486 loadQueue[loadHead]->readPC());
487
488 loadQueue[loadHead] = NULL;
489
490 incrLdIdx(loadHead);
491
492 --loads;
493}
494
495template <class Impl>
496void
497LSQUnit<Impl>::commitLoads(InstSeqNum &youngest_inst)
498{
499 assert(loads == 0 || loadQueue[loadHead]);
500
501 while (loads != 0 && loadQueue[loadHead]->seqNum <= youngest_inst) {
502 commitLoad();
503 }
504}
505
506template <class Impl>
507void
508LSQUnit<Impl>::commitStores(InstSeqNum &youngest_inst)
509{
510 assert(stores == 0 || storeQueue[storeHead].inst);
511
512 int store_idx = storeHead;
513
514 while (store_idx != storeTail) {
515 assert(storeQueue[store_idx].inst);
516 // Mark any stores that are now committed and have not yet
517 // been marked as able to write back.
518 if (!storeQueue[store_idx].canWB) {
519 if (storeQueue[store_idx].inst->seqNum > youngest_inst) {
520 break;
521 }
522 DPRINTF(LSQUnit, "Marking store as able to write back, PC "
523 "%#x [sn:%lli]\n",
524 storeQueue[store_idx].inst->readPC(),
525 storeQueue[store_idx].inst->seqNum);
526
527 storeQueue[store_idx].canWB = true;
528
529 ++storesToWB;
530 }
531
532 incrStIdx(store_idx);
533 }
534}
535
536template <class Impl>
537void
538LSQUnit<Impl>::writebackStores()
539{
540 while (storesToWB > 0 &&
541 storeWBIdx != storeTail &&
542 storeQueue[storeWBIdx].inst &&
543 storeQueue[storeWBIdx].canWB &&
544 usedPorts < cachePorts) {
545
546 if (isStoreBlocked) {
547 DPRINTF(LSQUnit, "Unable to write back any more stores, cache"
548 " is blocked!\n");
549 break;
550 }
551
552 // Store didn't write any data so no need to write it back to
553 // memory.
554 if (storeQueue[storeWBIdx].size == 0) {
555 completeStore(storeWBIdx);
556
557 incrStIdx(storeWBIdx);
558
559 continue;
560 }
561
562 ++usedPorts;
563
564 if (storeQueue[storeWBIdx].inst->isDataPrefetch()) {
565 incrStIdx(storeWBIdx);
566
567 continue;
568 }
569
570 assert(storeQueue[storeWBIdx].req);
571 assert(!storeQueue[storeWBIdx].committed);
572
573 DynInstPtr inst = storeQueue[storeWBIdx].inst;
574
575 Request *req = storeQueue[storeWBIdx].req;
576 storeQueue[storeWBIdx].committed = true;
577
578 assert(!inst->memData);
579 inst->memData = new uint8_t[64];
580 memcpy(inst->memData, (uint8_t *)&storeQueue[storeWBIdx].data,
581 req->getSize());
582
583 PacketPtr data_pkt = new Packet(req, Packet::WriteReq, Packet::Broadcast);
584 data_pkt->dataStatic(inst->memData);
585
586 LSQSenderState *state = new LSQSenderState;
587 state->isLoad = false;
588 state->idx = storeWBIdx;
589 state->inst = inst;
590 data_pkt->senderState = state;
591
592 DPRINTF(LSQUnit, "D-Cache: Writing back store idx:%i PC:%#x "
593 "to Addr:%#x, data:%#x [sn:%lli]\n",
594 storeWBIdx, storeQueue[storeWBIdx].inst->readPC(),
595 req->getPaddr(), *(inst->memData),
596 storeQueue[storeWBIdx].inst->seqNum);
597
598 // @todo: Remove this SC hack once the memory system handles it.
599 if (req->getFlags() & LOCKED) {
600 if (req->getFlags() & UNCACHEABLE) {
601 req->setScResult(2);
602 } else {
603 if (cpu->lockFlag) {
604 req->setScResult(1);
605 } else {
606 req->setScResult(0);
607 // Hack: Instantly complete this store.
608 completeDataAccess(data_pkt);
609 incrStIdx(storeWBIdx);
610 continue;
611 }
612 }
613 } else {
614 // Non-store conditionals do not need a writeback.
615 state->noWB = true;
616 }
617
618 if (!dcachePort->sendTiming(data_pkt)) {
619 // Need to handle becoming blocked on a store.
620 isStoreBlocked = true;
621
622 assert(retryPkt == NULL);
623 retryPkt = data_pkt;
624 } else {
625 storePostSend(data_pkt);
626 }
627 }
628
629 // Not sure this should set it to 0.
630 usedPorts = 0;
631
632 assert(stores >= 0 && storesToWB >= 0);
633}
634
635/*template <class Impl>
636void
637LSQUnit<Impl>::removeMSHR(InstSeqNum seqNum)
638{
639 list<InstSeqNum>::iterator mshr_it = find(mshrSeqNums.begin(),
640 mshrSeqNums.end(),
641 seqNum);
642
643 if (mshr_it != mshrSeqNums.end()) {
644 mshrSeqNums.erase(mshr_it);
645 DPRINTF(LSQUnit, "Removing MSHR. count = %i\n",mshrSeqNums.size());
646 }
647}*/
648
649template <class Impl>
650void
651LSQUnit<Impl>::squash(const InstSeqNum &squashed_num)
652{
653 DPRINTF(LSQUnit, "Squashing until [sn:%lli]!"
654 "(Loads:%i Stores:%i)\n", squashed_num, loads, stores);
655
656 int load_idx = loadTail;
657 decrLdIdx(load_idx);
658
659 while (loads != 0 && loadQueue[load_idx]->seqNum > squashed_num) {
660 DPRINTF(LSQUnit,"Load Instruction PC %#x squashed, "
661 "[sn:%lli]\n",
662 loadQueue[load_idx]->readPC(),
663 loadQueue[load_idx]->seqNum);
664
665 if (isStalled() && load_idx == stallingLoadIdx) {
666 stalled = false;
667 stallingStoreIsn = 0;
668 stallingLoadIdx = 0;
669 }
670
671 // Clear the smart pointer to make sure it is decremented.
672 loadQueue[load_idx]->squashed = true;
673 loadQueue[load_idx] = NULL;
674 --loads;
675
676 // Inefficient!
677 loadTail = load_idx;
678
679 decrLdIdx(load_idx);
680 }
681
682 if (isLoadBlocked) {
683 if (squashed_num < blockedLoadSeqNum) {
684 isLoadBlocked = false;
685 loadBlockedHandled = false;
686 blockedLoadSeqNum = 0;
687 }
688 }
689
690 int store_idx = storeTail;
691 decrStIdx(store_idx);
692
693 while (stores != 0 &&
694 storeQueue[store_idx].inst->seqNum > squashed_num) {
695 // Instructions marked as can WB are already committed.
696 if (storeQueue[store_idx].canWB) {
697 break;
698 }
699
700 DPRINTF(LSQUnit,"Store Instruction PC %#x squashed, "
701 "idx:%i [sn:%lli]\n",
702 storeQueue[store_idx].inst->readPC(),
703 store_idx, storeQueue[store_idx].inst->seqNum);
704
705 // I don't think this can happen. It should have been cleared
706 // by the stalling load.
707 if (isStalled() &&
708 storeQueue[store_idx].inst->seqNum == stallingStoreIsn) {
709 panic("Is stalled should have been cleared by stalling load!\n");
710 stalled = false;
711 stallingStoreIsn = 0;
712 }
713
714 // Clear the smart pointer to make sure it is decremented.
715 storeQueue[store_idx].inst->squashed = true;
716 storeQueue[store_idx].inst = NULL;
717 storeQueue[store_idx].canWB = 0;
718
719 storeQueue[store_idx].req = NULL;
720 --stores;
721
722 // Inefficient!
723 storeTail = store_idx;
724
725 decrStIdx(store_idx);
726 }
727}
728
729template <class Impl>
730void
731LSQUnit<Impl>::storePostSend(Packet *pkt)
732{
733 if (isStalled() &&
734 storeQueue[storeWBIdx].inst->seqNum == stallingStoreIsn) {
735 DPRINTF(LSQUnit, "Unstalling, stalling store [sn:%lli] "
736 "load idx:%i\n",
737 stallingStoreIsn, stallingLoadIdx);
738 stalled = false;
739 stallingStoreIsn = 0;
740 iewStage->replayMemInst(loadQueue[stallingLoadIdx]);
741 }
742
743 if (!storeQueue[storeWBIdx].inst->isStoreConditional()) {
744 // The store is basically completed at this time. This
745 // only works so long as the checker doesn't try to
746 // verify the value in memory for stores.
747 storeQueue[storeWBIdx].inst->setCompleted();
748 if (cpu->checker) {
749 cpu->checker->tick(storeQueue[storeWBIdx].inst);
750 }
751 }
752
753 if (pkt->result != Packet::Success) {
754 DPRINTF(LSQUnit,"D-Cache Write Miss on idx:%i!\n",
755 storeWBIdx);
756
757 DPRINTF(Activity, "Active st accessing mem miss [sn:%lli]\n",
758 storeQueue[storeWBIdx].inst->seqNum);
759
760 //mshrSeqNums.push_back(storeQueue[storeWBIdx].inst->seqNum);
761
762 //DPRINTF(LSQUnit, "Added MSHR. count = %i\n",mshrSeqNums.size());
763
764 // @todo: Increment stat here.
765 } else {
766 DPRINTF(LSQUnit,"D-Cache: Write Hit on idx:%i !\n",
767 storeWBIdx);
768
769 DPRINTF(Activity, "Active st accessing mem hit [sn:%lli]\n",
770 storeQueue[storeWBIdx].inst->seqNum);
771 }
772
773 incrStIdx(storeWBIdx);
774}
775
776template <class Impl>
777void
778LSQUnit<Impl>::writeback(DynInstPtr &inst, PacketPtr pkt)
779{
780 iewStage->wakeCPU();
781
782 // Squashed instructions do not need to complete their access.
783 if (inst->isSquashed()) {
784 assert(!inst->isStore());
785 return;
786 }
787
788 if (!inst->isExecuted()) {
789 inst->setExecuted();
790
791 // Complete access to copy data to proper place.
792 inst->completeAcc(pkt);
793 }
794
795 // Need to insert instruction into queue to commit
796 iewStage->instToCommit(inst);
797
798 iewStage->activityThisCycle();
799}
800
801template <class Impl>
802void
803LSQUnit<Impl>::completeStore(int store_idx)
804{
805 assert(storeQueue[store_idx].inst);
806 storeQueue[store_idx].completed = true;
807 --storesToWB;
808 // A bit conservative because a store completion may not free up entries,
809 // but hopefully avoids two store completions in one cycle from making
810 // the CPU tick twice.
811 cpu->activityThisCycle();
812
813 if (store_idx == storeHead) {
814 do {
815 incrStIdx(storeHead);
816
817 --stores;
818 } while (storeQueue[storeHead].completed &&
819 storeHead != storeTail);
820
821 iewStage->updateLSQNextCycle = true;
822 }
823
824 DPRINTF(LSQUnit, "Completing store [sn:%lli], idx:%i, store head "
825 "idx:%i\n",
826 storeQueue[store_idx].inst->seqNum, store_idx, storeHead);
827
828 if (isStalled() &&
829 storeQueue[store_idx].inst->seqNum == stallingStoreIsn) {
830 DPRINTF(LSQUnit, "Unstalling, stalling store [sn:%lli] "
831 "load idx:%i\n",
832 stallingStoreIsn, stallingLoadIdx);
833 stalled = false;
834 stallingStoreIsn = 0;
835 iewStage->replayMemInst(loadQueue[stallingLoadIdx]);
836 }
837
838 storeQueue[store_idx].inst->setCompleted();
839
840 // Tell the checker we've completed this instruction. Some stores
841 // may get reported twice to the checker, but the checker can
842 // handle that case.
843 if (cpu->checker) {
844 cpu->checker->tick(storeQueue[store_idx].inst);
845 }
846}
847
848template <class Impl>
849void
850LSQUnit<Impl>::recvRetry()
851{
852 if (isStoreBlocked) {
853 assert(retryPkt != NULL);
854
855 if (dcachePort->sendTiming(retryPkt)) {
856 storePostSend(retryPkt);
857 retryPkt = NULL;
858 isStoreBlocked = false;
859 } else {
860 // Still blocked!
861 }
862 } else if (isLoadBlocked) {
863 DPRINTF(LSQUnit, "Loads squash themselves and all younger insts, "
864 "no need to resend packet.\n");
865 } else {
866 DPRINTF(LSQUnit, "Retry received but LSQ is no longer blocked.\n");
867 }
868}
869
870template <class Impl>
871inline void
872LSQUnit<Impl>::incrStIdx(int &store_idx)
873{
874 if (++store_idx >= SQEntries)
875 store_idx = 0;
876}
877
878template <class Impl>
879inline void
880LSQUnit<Impl>::decrStIdx(int &store_idx)
881{
882 if (--store_idx < 0)
883 store_idx += SQEntries;
884}
885
886template <class Impl>
887inline void
888LSQUnit<Impl>::incrLdIdx(int &load_idx)
889{
890 if (++load_idx >= LQEntries)
891 load_idx = 0;
892}
893
894template <class Impl>
895inline void
896LSQUnit<Impl>::decrLdIdx(int &load_idx)
897{
898 if (--load_idx < 0)
899 load_idx += LQEntries;
900}
901
902template <class Impl>
903void
904LSQUnit<Impl>::dumpInsts()
905{
906 cprintf("Load store queue: Dumping instructions.\n");
907 cprintf("Load queue size: %i\n", loads);
908 cprintf("Load queue: ");
909
910 int load_idx = loadHead;
911
912 while (load_idx != loadTail && loadQueue[load_idx]) {
913 cprintf("%#x ", loadQueue[load_idx]->readPC());
914
915 incrLdIdx(load_idx);
916 }
917
918 cprintf("Store queue size: %i\n", stores);
919 cprintf("Store queue: ");
920
921 int store_idx = storeHead;
922
923 while (store_idx != storeTail && storeQueue[store_idx].inst) {
924 cprintf("%#x ", storeQueue[store_idx].inst->readPC());
925
926 incrStIdx(store_idx);
927 }
928
929 cprintf("\n");
930}
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