1
2/*
3 * Copyright (c) 2010-2014, 2017 ARM Limited
4 * Copyright (c) 2013 Advanced Micro Devices, Inc.
5 * All rights reserved
6 *
7 * The license below extends only to copyright in the software and shall
8 * not be construed as granting a license to any other intellectual
9 * property including but not limited to intellectual property relating
10 * to a hardware implementation of the functionality of the software
11 * licensed hereunder. You may use the software subject to the license
12 * terms below provided that you ensure that this notice is replicated
13 * unmodified and in its entirety in all distributions of the software,
14 * modified or unmodified, in source code or in binary form.
15 *
16 * Copyright (c) 2004-2005 The Regents of The University of Michigan
17 * All rights reserved.
18 *
19 * Redistribution and use in source and binary forms, with or without
20 * modification, are permitted provided that the following conditions are
21 * met: redistributions of source code must retain the above copyright
22 * notice, this list of conditions and the following disclaimer;
23 * redistributions in binary form must reproduce the above copyright
24 * notice, this list of conditions and the following disclaimer in the
25 * documentation and/or other materials provided with the distribution;
26 * neither the name of the copyright holders nor the names of its
27 * contributors may be used to endorse or promote products derived from
28 * this software without specific prior written permission.
29 *
30 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
31 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
32 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
33 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
34 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
35 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
36 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
37 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
38 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
39 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
40 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
41 *
42 * Authors: Kevin Lim
43 * Korey Sewell
44 */
45
46#ifndef __CPU_O3_LSQ_UNIT_IMPL_HH__
47#define __CPU_O3_LSQ_UNIT_IMPL_HH__
48
49#include "arch/generic/debugfaults.hh"
50#include "arch/locked_mem.hh"
51#include "base/str.hh"
52#include "config/the_isa.hh"
53#include "cpu/checker/cpu.hh"
54#include "cpu/o3/lsq.hh"
55#include "cpu/o3/lsq_unit.hh"
56#include "debug/Activity.hh"
57#include "debug/IEW.hh"
58#include "debug/LSQUnit.hh"
59#include "debug/O3PipeView.hh"
60#include "mem/packet.hh"
61#include "mem/request.hh"
62
63template<class Impl>
64LSQUnit<Impl>::WritebackEvent::WritebackEvent(const DynInstPtr &_inst,
65 PacketPtr _pkt, LSQUnit *lsq_ptr)
66 : Event(Default_Pri, AutoDelete),
67 inst(_inst), pkt(_pkt), lsqPtr(lsq_ptr)
68{
69}
70
71template<class Impl>
72void
73LSQUnit<Impl>::WritebackEvent::process()
74{
75 assert(!lsqPtr->cpu->switchedOut());
76
77 lsqPtr->writeback(inst, pkt);
78
79 if (pkt->senderState)
80 delete pkt->senderState;
81
82 delete pkt;
83}
84
85template<class Impl>
86const char *
87LSQUnit<Impl>::WritebackEvent::description() const
88{
89 return "Store writeback";
90}
91
92template<class Impl>
93void
94LSQUnit<Impl>::completeDataAccess(PacketPtr pkt)
95{
96 LSQSenderState *state = dynamic_cast<LSQSenderState *>(pkt->senderState);
97 DynInstPtr inst = state->inst;
98 DPRINTF(IEW, "Writeback event [sn:%lli].\n", inst->seqNum);
99 DPRINTF(Activity, "Activity: Writeback event [sn:%lli].\n", inst->seqNum);
100
101 if (state->cacheBlocked) {
102 // This is the first half of a previous split load,
103 // where the 2nd half blocked, ignore this response
104 DPRINTF(IEW, "[sn:%lli]: Response from first half of earlier "
105 "blocked split load recieved. Ignoring.\n", inst->seqNum);
106 delete state;
107 return;
108 }
109
110 // If this is a split access, wait until all packets are received.
111 if (TheISA::HasUnalignedMemAcc && !state->complete()) {
112 return;
113 }
114
115 assert(!cpu->switchedOut());
116 if (!inst->isSquashed()) {
117 if (!state->noWB) {
118 // Only loads and store conditionals perform the writeback
119 // after receving the response from the memory
120 assert(inst->isLoad() || inst->isStoreConditional());
121 if (!TheISA::HasUnalignedMemAcc || !state->isSplit ||
122 !state->isLoad) {
123 writeback(inst, pkt);
124 } else {
125 writeback(inst, state->mainPkt);
126 }
127 }
128
129 if (inst->isStore()) {
130 completeStore(state->idx);
131 }
132 }
133
134 if (TheISA::HasUnalignedMemAcc && state->isSplit && state->isLoad) {
135 delete state->mainPkt;
136 }
137
138 pkt->req->setAccessLatency();
139 cpu->ppDataAccessComplete->notify(std::make_pair(inst, pkt));
140
141 delete state;
142}
143
144template <class Impl>
| 1
2/*
3 * Copyright (c) 2010-2014, 2017 ARM Limited
4 * Copyright (c) 2013 Advanced Micro Devices, Inc.
5 * All rights reserved
6 *
7 * The license below extends only to copyright in the software and shall
8 * not be construed as granting a license to any other intellectual
9 * property including but not limited to intellectual property relating
10 * to a hardware implementation of the functionality of the software
11 * licensed hereunder. You may use the software subject to the license
12 * terms below provided that you ensure that this notice is replicated
13 * unmodified and in its entirety in all distributions of the software,
14 * modified or unmodified, in source code or in binary form.
15 *
16 * Copyright (c) 2004-2005 The Regents of The University of Michigan
17 * All rights reserved.
18 *
19 * Redistribution and use in source and binary forms, with or without
20 * modification, are permitted provided that the following conditions are
21 * met: redistributions of source code must retain the above copyright
22 * notice, this list of conditions and the following disclaimer;
23 * redistributions in binary form must reproduce the above copyright
24 * notice, this list of conditions and the following disclaimer in the
25 * documentation and/or other materials provided with the distribution;
26 * neither the name of the copyright holders nor the names of its
27 * contributors may be used to endorse or promote products derived from
28 * this software without specific prior written permission.
29 *
30 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
31 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
32 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
33 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
34 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
35 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
36 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
37 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
38 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
39 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
40 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
41 *
42 * Authors: Kevin Lim
43 * Korey Sewell
44 */
45
46#ifndef __CPU_O3_LSQ_UNIT_IMPL_HH__
47#define __CPU_O3_LSQ_UNIT_IMPL_HH__
48
49#include "arch/generic/debugfaults.hh"
50#include "arch/locked_mem.hh"
51#include "base/str.hh"
52#include "config/the_isa.hh"
53#include "cpu/checker/cpu.hh"
54#include "cpu/o3/lsq.hh"
55#include "cpu/o3/lsq_unit.hh"
56#include "debug/Activity.hh"
57#include "debug/IEW.hh"
58#include "debug/LSQUnit.hh"
59#include "debug/O3PipeView.hh"
60#include "mem/packet.hh"
61#include "mem/request.hh"
62
63template<class Impl>
64LSQUnit<Impl>::WritebackEvent::WritebackEvent(const DynInstPtr &_inst,
65 PacketPtr _pkt, LSQUnit *lsq_ptr)
66 : Event(Default_Pri, AutoDelete),
67 inst(_inst), pkt(_pkt), lsqPtr(lsq_ptr)
68{
69}
70
71template<class Impl>
72void
73LSQUnit<Impl>::WritebackEvent::process()
74{
75 assert(!lsqPtr->cpu->switchedOut());
76
77 lsqPtr->writeback(inst, pkt);
78
79 if (pkt->senderState)
80 delete pkt->senderState;
81
82 delete pkt;
83}
84
85template<class Impl>
86const char *
87LSQUnit<Impl>::WritebackEvent::description() const
88{
89 return "Store writeback";
90}
91
92template<class Impl>
93void
94LSQUnit<Impl>::completeDataAccess(PacketPtr pkt)
95{
96 LSQSenderState *state = dynamic_cast<LSQSenderState *>(pkt->senderState);
97 DynInstPtr inst = state->inst;
98 DPRINTF(IEW, "Writeback event [sn:%lli].\n", inst->seqNum);
99 DPRINTF(Activity, "Activity: Writeback event [sn:%lli].\n", inst->seqNum);
100
101 if (state->cacheBlocked) {
102 // This is the first half of a previous split load,
103 // where the 2nd half blocked, ignore this response
104 DPRINTF(IEW, "[sn:%lli]: Response from first half of earlier "
105 "blocked split load recieved. Ignoring.\n", inst->seqNum);
106 delete state;
107 return;
108 }
109
110 // If this is a split access, wait until all packets are received.
111 if (TheISA::HasUnalignedMemAcc && !state->complete()) {
112 return;
113 }
114
115 assert(!cpu->switchedOut());
116 if (!inst->isSquashed()) {
117 if (!state->noWB) {
118 // Only loads and store conditionals perform the writeback
119 // after receving the response from the memory
120 assert(inst->isLoad() || inst->isStoreConditional());
121 if (!TheISA::HasUnalignedMemAcc || !state->isSplit ||
122 !state->isLoad) {
123 writeback(inst, pkt);
124 } else {
125 writeback(inst, state->mainPkt);
126 }
127 }
128
129 if (inst->isStore()) {
130 completeStore(state->idx);
131 }
132 }
133
134 if (TheISA::HasUnalignedMemAcc && state->isSplit && state->isLoad) {
135 delete state->mainPkt;
136 }
137
138 pkt->req->setAccessLatency();
139 cpu->ppDataAccessComplete->notify(std::make_pair(inst, pkt));
140
141 delete state;
142}
143
144template <class Impl>
|
178 depCheckShift = params->LSQDepCheckShift;
179 checkLoads = params->LSQCheckLoads;
180 cacheStorePorts = params->cacheStorePorts;
181 needsTSO = params->needsTSO;
182
183 resetState();
184}
185
186
187template<class Impl>
188void
189LSQUnit<Impl>::resetState()
190{
191 loads = stores = storesToWB = 0;
192
193 loadHead = loadTail = 0;
194
195 storeHead = storeWBIdx = storeTail = 0;
196
197 usedStorePorts = 0;
198
199 retryPkt = NULL;
200 memDepViolator = NULL;
201
202 stalled = false;
203
204 cacheBlockMask = ~(cpu->cacheLineSize() - 1);
205}
206
207template<class Impl>
208std::string
209LSQUnit<Impl>::name() const
210{
211 if (Impl::MaxThreads == 1) {
212 return iewStage->name() + ".lsq";
213 } else {
214 return iewStage->name() + ".lsq.thread" + std::to_string(lsqID);
215 }
216}
217
218template<class Impl>
219void
220LSQUnit<Impl>::regStats()
221{
222 lsqForwLoads
223 .name(name() + ".forwLoads")
224 .desc("Number of loads that had data forwarded from stores");
225
226 invAddrLoads
227 .name(name() + ".invAddrLoads")
228 .desc("Number of loads ignored due to an invalid address");
229
230 lsqSquashedLoads
231 .name(name() + ".squashedLoads")
232 .desc("Number of loads squashed");
233
234 lsqIgnoredResponses
235 .name(name() + ".ignoredResponses")
236 .desc("Number of memory responses ignored because the instruction is squashed");
237
238 lsqMemOrderViolation
239 .name(name() + ".memOrderViolation")
240 .desc("Number of memory ordering violations");
241
242 lsqSquashedStores
243 .name(name() + ".squashedStores")
244 .desc("Number of stores squashed");
245
246 invAddrSwpfs
247 .name(name() + ".invAddrSwpfs")
248 .desc("Number of software prefetches ignored due to an invalid address");
249
250 lsqBlockedLoads
251 .name(name() + ".blockedLoads")
252 .desc("Number of blocked loads due to partial load-store forwarding");
253
254 lsqRescheduledLoads
255 .name(name() + ".rescheduledLoads")
256 .desc("Number of loads that were rescheduled");
257
258 lsqCacheBlocked
259 .name(name() + ".cacheBlocked")
260 .desc("Number of times an access to memory failed due to the cache being blocked");
261}
262
263template<class Impl>
264void
265LSQUnit<Impl>::setDcachePort(MasterPort *dcache_port)
266{
267 dcachePort = dcache_port;
268}
269
270template<class Impl>
271void
272LSQUnit<Impl>::clearLQ()
273{
274 loadQueue.clear();
275}
276
277template<class Impl>
278void
279LSQUnit<Impl>::clearSQ()
280{
281 storeQueue.clear();
282}
283
284template<class Impl>
285void
286LSQUnit<Impl>::drainSanityCheck() const
287{
288 for (int i = 0; i < loadQueue.size(); ++i)
289 assert(!loadQueue[i]);
290
291 assert(storesToWB == 0);
292 assert(!retryPkt);
293}
294
295template<class Impl>
296void
297LSQUnit<Impl>::takeOverFrom()
298{
299 resetState();
300}
301
302template<class Impl>
303void
304LSQUnit<Impl>::resizeLQ(unsigned size)
305{
306 unsigned size_plus_sentinel = size + 1;
307 assert(size_plus_sentinel >= LQEntries);
308
309 if (size_plus_sentinel > LQEntries) {
310 while (size_plus_sentinel > loadQueue.size()) {
311 DynInstPtr dummy;
312 loadQueue.push_back(dummy);
313 LQEntries++;
314 }
315 } else {
316 LQEntries = size_plus_sentinel;
317 }
318
319 assert(LQEntries <= 256);
320}
321
322template<class Impl>
323void
324LSQUnit<Impl>::resizeSQ(unsigned size)
325{
326 unsigned size_plus_sentinel = size + 1;
327 if (size_plus_sentinel > SQEntries) {
328 while (size_plus_sentinel > storeQueue.size()) {
329 SQEntry dummy;
330 storeQueue.push_back(dummy);
331 SQEntries++;
332 }
333 } else {
334 SQEntries = size_plus_sentinel;
335 }
336
337 assert(SQEntries <= 256);
338}
339
340template <class Impl>
341void
342LSQUnit<Impl>::insert(const DynInstPtr &inst)
343{
344 assert(inst->isMemRef());
345
346 assert(inst->isLoad() || inst->isStore());
347
348 if (inst->isLoad()) {
349 insertLoad(inst);
350 } else {
351 insertStore(inst);
352 }
353
354 inst->setInLSQ();
355}
356
357template <class Impl>
358void
359LSQUnit<Impl>::insertLoad(const DynInstPtr &load_inst)
360{
361 assert((loadTail + 1) % LQEntries != loadHead);
362 assert(loads < LQEntries);
363
364 DPRINTF(LSQUnit, "Inserting load PC %s, idx:%i [sn:%lli]\n",
365 load_inst->pcState(), loadTail, load_inst->seqNum);
366
367 load_inst->lqIdx = loadTail;
368
369 if (stores == 0) {
370 load_inst->sqIdx = -1;
371 } else {
372 load_inst->sqIdx = storeTail;
373 }
374
375 loadQueue[loadTail] = load_inst;
376
377 incrLdIdx(loadTail);
378
379 ++loads;
380}
381
382template <class Impl>
383void
384LSQUnit<Impl>::insertStore(const DynInstPtr &store_inst)
385{
386 // Make sure it is not full before inserting an instruction.
387 assert((storeTail + 1) % SQEntries != storeHead);
388 assert(stores < SQEntries);
389
390 DPRINTF(LSQUnit, "Inserting store PC %s, idx:%i [sn:%lli]\n",
391 store_inst->pcState(), storeTail, store_inst->seqNum);
392
393 store_inst->sqIdx = storeTail;
394 store_inst->lqIdx = loadTail;
395
396 storeQueue[storeTail] = SQEntry(store_inst);
397
398 incrStIdx(storeTail);
399
400 ++stores;
401}
402
403template <class Impl>
404typename Impl::DynInstPtr
405LSQUnit<Impl>::getMemDepViolator()
406{
407 DynInstPtr temp = memDepViolator;
408
409 memDepViolator = NULL;
410
411 return temp;
412}
413
414template <class Impl>
415unsigned
416LSQUnit<Impl>::numFreeLoadEntries()
417{
418 //LQ has an extra dummy entry to differentiate
419 //empty/full conditions. Subtract 1 from the free entries.
420 DPRINTF(LSQUnit, "LQ size: %d, #loads occupied: %d\n", LQEntries, loads);
421 return LQEntries - loads - 1;
422}
423
424template <class Impl>
425unsigned
426LSQUnit<Impl>::numFreeStoreEntries()
427{
428 //SQ has an extra dummy entry to differentiate
429 //empty/full conditions. Subtract 1 from the free entries.
430 DPRINTF(LSQUnit, "SQ size: %d, #stores occupied: %d\n", SQEntries, stores);
431 return SQEntries - stores - 1;
432
433 }
434
435template <class Impl>
436void
437LSQUnit<Impl>::checkSnoop(PacketPtr pkt)
438{
439 // Should only ever get invalidations in here
440 assert(pkt->isInvalidate());
441
442 int load_idx = loadHead;
443 DPRINTF(LSQUnit, "Got snoop for address %#x\n", pkt->getAddr());
444
445 // Only Invalidate packet calls checkSnoop
446 assert(pkt->isInvalidate());
447 for (int x = 0; x < cpu->numContexts(); x++) {
448 ThreadContext *tc = cpu->getContext(x);
449 bool no_squash = cpu->thread[x]->noSquashFromTC;
450 cpu->thread[x]->noSquashFromTC = true;
451 TheISA::handleLockedSnoop(tc, pkt, cacheBlockMask);
452 cpu->thread[x]->noSquashFromTC = no_squash;
453 }
454
455 Addr invalidate_addr = pkt->getAddr() & cacheBlockMask;
456
457 DynInstPtr ld_inst = loadQueue[load_idx];
458 if (ld_inst) {
459 Addr load_addr_low = ld_inst->physEffAddrLow & cacheBlockMask;
460 Addr load_addr_high = ld_inst->physEffAddrHigh & cacheBlockMask;
461
462 // Check that this snoop didn't just invalidate our lock flag
463 if (ld_inst->effAddrValid() && (load_addr_low == invalidate_addr
464 || load_addr_high == invalidate_addr)
465 && ld_inst->memReqFlags & Request::LLSC)
466 TheISA::handleLockedSnoopHit(ld_inst.get());
467 }
468
469 // If this is the only load in the LSQ we don't care
470 if (load_idx == loadTail)
471 return;
472
473 incrLdIdx(load_idx);
474
475 bool force_squash = false;
476
477 while (load_idx != loadTail) {
478 DynInstPtr ld_inst = loadQueue[load_idx];
479
480 if (!ld_inst->effAddrValid() || ld_inst->strictlyOrdered()) {
481 incrLdIdx(load_idx);
482 continue;
483 }
484
485 Addr load_addr_low = ld_inst->physEffAddrLow & cacheBlockMask;
486 Addr load_addr_high = ld_inst->physEffAddrHigh & cacheBlockMask;
487
488 DPRINTF(LSQUnit, "-- inst [sn:%lli] load_addr: %#x to pktAddr:%#x\n",
489 ld_inst->seqNum, load_addr_low, invalidate_addr);
490
491 if ((load_addr_low == invalidate_addr
492 || load_addr_high == invalidate_addr) || force_squash) {
493 if (needsTSO) {
494 // If we have a TSO system, as all loads must be ordered with
495 // all other loads, this load as well as *all* subsequent loads
496 // need to be squashed to prevent possible load reordering.
497 force_squash = true;
498 }
499 if (ld_inst->possibleLoadViolation() || force_squash) {
500 DPRINTF(LSQUnit, "Conflicting load at addr %#x [sn:%lli]\n",
501 pkt->getAddr(), ld_inst->seqNum);
502
503 // Mark the load for re-execution
504 ld_inst->fault = std::make_shared<ReExec>();
505 } else {
506 DPRINTF(LSQUnit, "HitExternal Snoop for addr %#x [sn:%lli]\n",
507 pkt->getAddr(), ld_inst->seqNum);
508
509 // Make sure that we don't lose a snoop hitting a LOCKED
510 // address since the LOCK* flags don't get updated until
511 // commit.
512 if (ld_inst->memReqFlags & Request::LLSC)
513 TheISA::handleLockedSnoopHit(ld_inst.get());
514
515 // If a older load checks this and it's true
516 // then we might have missed the snoop
517 // in which case we need to invalidate to be sure
518 ld_inst->hitExternalSnoop(true);
519 }
520 }
521 incrLdIdx(load_idx);
522 }
523 return;
524}
525
526template <class Impl>
527Fault
528LSQUnit<Impl>::checkViolations(int load_idx, const DynInstPtr &inst)
529{
530 Addr inst_eff_addr1 = inst->effAddr >> depCheckShift;
531 Addr inst_eff_addr2 = (inst->effAddr + inst->effSize - 1) >> depCheckShift;
532
533 /** @todo in theory you only need to check an instruction that has executed
534 * however, there isn't a good way in the pipeline at the moment to check
535 * all instructions that will execute before the store writes back. Thus,
536 * like the implementation that came before it, we're overly conservative.
537 */
538 while (load_idx != loadTail) {
539 DynInstPtr ld_inst = loadQueue[load_idx];
540 if (!ld_inst->effAddrValid() || ld_inst->strictlyOrdered()) {
541 incrLdIdx(load_idx);
542 continue;
543 }
544
545 Addr ld_eff_addr1 = ld_inst->effAddr >> depCheckShift;
546 Addr ld_eff_addr2 =
547 (ld_inst->effAddr + ld_inst->effSize - 1) >> depCheckShift;
548
549 if (inst_eff_addr2 >= ld_eff_addr1 && inst_eff_addr1 <= ld_eff_addr2) {
550 if (inst->isLoad()) {
551 // If this load is to the same block as an external snoop
552 // invalidate that we've observed then the load needs to be
553 // squashed as it could have newer data
554 if (ld_inst->hitExternalSnoop()) {
555 if (!memDepViolator ||
556 ld_inst->seqNum < memDepViolator->seqNum) {
557 DPRINTF(LSQUnit, "Detected fault with inst [sn:%lli] "
558 "and [sn:%lli] at address %#x\n",
559 inst->seqNum, ld_inst->seqNum, ld_eff_addr1);
560 memDepViolator = ld_inst;
561
562 ++lsqMemOrderViolation;
563
564 return std::make_shared<GenericISA::M5PanicFault>(
565 "Detected fault with inst [sn:%lli] and "
566 "[sn:%lli] at address %#x\n",
567 inst->seqNum, ld_inst->seqNum, ld_eff_addr1);
568 }
569 }
570
571 // Otherwise, mark the load has a possible load violation
572 // and if we see a snoop before it's commited, we need to squash
573 ld_inst->possibleLoadViolation(true);
574 DPRINTF(LSQUnit, "Found possible load violation at addr: %#x"
575 " between instructions [sn:%lli] and [sn:%lli]\n",
576 inst_eff_addr1, inst->seqNum, ld_inst->seqNum);
577 } else {
578 // A load/store incorrectly passed this store.
579 // Check if we already have a violator, or if it's newer
580 // squash and refetch.
581 if (memDepViolator && ld_inst->seqNum > memDepViolator->seqNum)
582 break;
583
584 DPRINTF(LSQUnit, "Detected fault with inst [sn:%lli] and "
585 "[sn:%lli] at address %#x\n",
586 inst->seqNum, ld_inst->seqNum, ld_eff_addr1);
587 memDepViolator = ld_inst;
588
589 ++lsqMemOrderViolation;
590
591 return std::make_shared<GenericISA::M5PanicFault>(
592 "Detected fault with "
593 "inst [sn:%lli] and [sn:%lli] at address %#x\n",
594 inst->seqNum, ld_inst->seqNum, ld_eff_addr1);
595 }
596 }
597
598 incrLdIdx(load_idx);
599 }
600 return NoFault;
601}
602
603
604
605
606template <class Impl>
607Fault
608LSQUnit<Impl>::executeLoad(const DynInstPtr &inst)
609{
610 using namespace TheISA;
611 // Execute a specific load.
612 Fault load_fault = NoFault;
613
614 DPRINTF(LSQUnit, "Executing load PC %s, [sn:%lli]\n",
615 inst->pcState(), inst->seqNum);
616
617 assert(!inst->isSquashed());
618
619 load_fault = inst->initiateAcc();
620
621 if (inst->isTranslationDelayed() &&
622 load_fault == NoFault)
623 return load_fault;
624
625 // If the instruction faulted or predicated false, then we need to send it
626 // along to commit without the instruction completing.
627 if (load_fault != NoFault || !inst->readPredicate()) {
628 // Send this instruction to commit, also make sure iew stage
629 // realizes there is activity. Mark it as executed unless it
630 // is a strictly ordered load that needs to hit the head of
631 // commit.
632 if (!inst->readPredicate())
633 inst->forwardOldRegs();
634 DPRINTF(LSQUnit, "Load [sn:%lli] not executed from %s\n",
635 inst->seqNum,
636 (load_fault != NoFault ? "fault" : "predication"));
637 if (!(inst->hasRequest() && inst->strictlyOrdered()) ||
638 inst->isAtCommit()) {
639 inst->setExecuted();
640 }
641 iewStage->instToCommit(inst);
642 iewStage->activityThisCycle();
643 } else {
644 assert(inst->effAddrValid());
645 int load_idx = inst->lqIdx;
646 incrLdIdx(load_idx);
647
648 if (checkLoads)
649 return checkViolations(load_idx, inst);
650 }
651
652 return load_fault;
653}
654
655template <class Impl>
656Fault
657LSQUnit<Impl>::executeStore(const DynInstPtr &store_inst)
658{
659 using namespace TheISA;
660 // Make sure that a store exists.
661 assert(stores != 0);
662
663 int store_idx = store_inst->sqIdx;
664
665 DPRINTF(LSQUnit, "Executing store PC %s [sn:%lli]\n",
666 store_inst->pcState(), store_inst->seqNum);
667
668 assert(!store_inst->isSquashed());
669
670 // Check the recently completed loads to see if any match this store's
671 // address. If so, then we have a memory ordering violation.
672 int load_idx = store_inst->lqIdx;
673
674 Fault store_fault = store_inst->initiateAcc();
675
676 if (store_inst->isTranslationDelayed() &&
677 store_fault == NoFault)
678 return store_fault;
679
680 if (!store_inst->readPredicate()) {
681 DPRINTF(LSQUnit, "Store [sn:%lli] not executed from predication\n",
682 store_inst->seqNum);
683 store_inst->forwardOldRegs();
684 return store_fault;
685 }
686
687 if (storeQueue[store_idx].size == 0) {
688 DPRINTF(LSQUnit,"Fault on Store PC %s, [sn:%lli], Size = 0\n",
689 store_inst->pcState(), store_inst->seqNum);
690
691 return store_fault;
692 }
693
694 assert(store_fault == NoFault);
695
696 if (store_inst->isStoreConditional()) {
697 // Store conditionals need to set themselves as able to
698 // writeback if we haven't had a fault by here.
699 storeQueue[store_idx].canWB = true;
700
701 ++storesToWB;
702 }
703
704 return checkViolations(load_idx, store_inst);
705
706}
707
708template <class Impl>
709void
710LSQUnit<Impl>::commitLoad()
711{
712 assert(loadQueue[loadHead]);
713
714 DPRINTF(LSQUnit, "Committing head load instruction, PC %s\n",
715 loadQueue[loadHead]->pcState());
716
717 loadQueue[loadHead] = NULL;
718
719 incrLdIdx(loadHead);
720
721 --loads;
722}
723
724template <class Impl>
725void
726LSQUnit<Impl>::commitLoads(InstSeqNum &youngest_inst)
727{
728 assert(loads == 0 || loadQueue[loadHead]);
729
730 while (loads != 0 && loadQueue[loadHead]->seqNum <= youngest_inst) {
731 commitLoad();
732 }
733}
734
735template <class Impl>
736void
737LSQUnit<Impl>::commitStores(InstSeqNum &youngest_inst)
738{
739 assert(stores == 0 || storeQueue[storeHead].inst);
740
741 int store_idx = storeHead;
742
743 while (store_idx != storeTail) {
744 assert(storeQueue[store_idx].inst);
745 // Mark any stores that are now committed and have not yet
746 // been marked as able to write back.
747 if (!storeQueue[store_idx].canWB) {
748 if (storeQueue[store_idx].inst->seqNum > youngest_inst) {
749 break;
750 }
751 DPRINTF(LSQUnit, "Marking store as able to write back, PC "
752 "%s [sn:%lli]\n",
753 storeQueue[store_idx].inst->pcState(),
754 storeQueue[store_idx].inst->seqNum);
755
756 storeQueue[store_idx].canWB = true;
757
758 ++storesToWB;
759 }
760
761 incrStIdx(store_idx);
762 }
763}
764
765template <class Impl>
766void
767LSQUnit<Impl>::writebackPendingStore()
768{
769 if (hasPendingPkt) {
770 assert(pendingPkt != NULL);
771
772 // If the cache is blocked, this will store the packet for retry.
773 if (sendStore(pendingPkt)) {
774 storePostSend(pendingPkt);
775 }
776 pendingPkt = NULL;
777 hasPendingPkt = false;
778 }
779}
780
781template <class Impl>
782void
783LSQUnit<Impl>::writebackStores()
784{
785 // First writeback the second packet from any split store that didn't
786 // complete last cycle because there weren't enough cache ports available.
787 if (TheISA::HasUnalignedMemAcc) {
788 writebackPendingStore();
789 }
790
791 while (storesToWB > 0 &&
792 storeWBIdx != storeTail &&
793 storeQueue[storeWBIdx].inst &&
794 storeQueue[storeWBIdx].canWB &&
795 ((!needsTSO) || (!storeInFlight)) &&
796 usedStorePorts < cacheStorePorts) {
797
798 if (isStoreBlocked) {
799 DPRINTF(LSQUnit, "Unable to write back any more stores, cache"
800 " is blocked!\n");
801 break;
802 }
803
804 // Store didn't write any data so no need to write it back to
805 // memory.
806 if (storeQueue[storeWBIdx].size == 0) {
807 completeStore(storeWBIdx);
808
809 incrStIdx(storeWBIdx);
810
811 continue;
812 }
813
814 ++usedStorePorts;
815
816 if (storeQueue[storeWBIdx].inst->isDataPrefetch()) {
817 incrStIdx(storeWBIdx);
818
819 continue;
820 }
821
822 assert(storeQueue[storeWBIdx].req);
823 assert(!storeQueue[storeWBIdx].committed);
824
825 if (TheISA::HasUnalignedMemAcc && storeQueue[storeWBIdx].isSplit) {
826 assert(storeQueue[storeWBIdx].sreqLow);
827 assert(storeQueue[storeWBIdx].sreqHigh);
828 }
829
830 DynInstPtr inst = storeQueue[storeWBIdx].inst;
831
832 RequestPtr &req = storeQueue[storeWBIdx].req;
833 const RequestPtr &sreqLow = storeQueue[storeWBIdx].sreqLow;
834 const RequestPtr &sreqHigh = storeQueue[storeWBIdx].sreqHigh;
835
836 storeQueue[storeWBIdx].committed = true;
837
838 assert(!inst->memData);
839 inst->memData = new uint8_t[req->getSize()];
840
841 if (storeQueue[storeWBIdx].isAllZeros)
842 memset(inst->memData, 0, req->getSize());
843 else
844 memcpy(inst->memData, storeQueue[storeWBIdx].data, req->getSize());
845
846 PacketPtr data_pkt;
847 PacketPtr snd_data_pkt = NULL;
848
849 LSQSenderState *state = new LSQSenderState;
850 state->isLoad = false;
851 state->idx = storeWBIdx;
852 state->inst = inst;
853
854 if (!TheISA::HasUnalignedMemAcc || !storeQueue[storeWBIdx].isSplit) {
855
856 // Build a single data packet if the store isn't split.
857 data_pkt = Packet::createWrite(req);
858 data_pkt->dataStatic(inst->memData);
859 data_pkt->senderState = state;
860 } else {
861 // Create two packets if the store is split in two.
862 data_pkt = Packet::createWrite(sreqLow);
863 snd_data_pkt = Packet::createWrite(sreqHigh);
864
865 data_pkt->dataStatic(inst->memData);
866 snd_data_pkt->dataStatic(inst->memData + sreqLow->getSize());
867
868 data_pkt->senderState = state;
869 snd_data_pkt->senderState = state;
870
871 state->isSplit = true;
872 state->outstanding = 2;
873
874 // Can delete the main request now.
875 req = sreqLow;
876 }
877
878 DPRINTF(LSQUnit, "D-Cache: Writing back store idx:%i PC:%s "
879 "to Addr:%#x, data:%#x [sn:%lli]\n",
880 storeWBIdx, inst->pcState(),
881 req->getPaddr(), (int)*(inst->memData),
882 inst->seqNum);
883
884 // @todo: Remove this SC hack once the memory system handles it.
885 if (inst->isStoreConditional()) {
886 assert(!storeQueue[storeWBIdx].isSplit);
887 // Disable recording the result temporarily. Writing to
888 // misc regs normally updates the result, but this is not
889 // the desired behavior when handling store conditionals.
890 inst->recordResult(false);
891 bool success = TheISA::handleLockedWrite(inst.get(), req, cacheBlockMask);
892 inst->recordResult(true);
893
894 if (!success) {
895 // Instantly complete this store.
896 DPRINTF(LSQUnit, "Store conditional [sn:%lli] failed. "
897 "Instantly completing it.\n",
898 inst->seqNum);
899 WritebackEvent *wb = new WritebackEvent(inst, data_pkt, this);
900 cpu->schedule(wb, curTick() + 1);
901 completeStore(storeWBIdx);
902 incrStIdx(storeWBIdx);
903 continue;
904 }
905 } else {
906 // Non-store conditionals do not need a writeback.
907 state->noWB = true;
908 }
909
910 bool split =
911 TheISA::HasUnalignedMemAcc && storeQueue[storeWBIdx].isSplit;
912
913 ThreadContext *thread = cpu->tcBase(lsqID);
914
915 if (req->isMmappedIpr()) {
916 assert(!inst->isStoreConditional());
917 TheISA::handleIprWrite(thread, data_pkt);
918 delete data_pkt;
919 if (split) {
920 assert(snd_data_pkt->req->isMmappedIpr());
921 TheISA::handleIprWrite(thread, snd_data_pkt);
922 delete snd_data_pkt;
923 }
924 delete state;
925 completeStore(storeWBIdx);
926 incrStIdx(storeWBIdx);
927 } else if (!sendStore(data_pkt)) {
928 DPRINTF(IEW, "D-Cache became blocked when writing [sn:%lli], will"
929 "retry later\n",
930 inst->seqNum);
931
932 // Need to store the second packet, if split.
933 if (split) {
934 state->pktToSend = true;
935 state->pendingPacket = snd_data_pkt;
936 }
937 } else {
938
939 // If split, try to send the second packet too
940 if (split) {
941 assert(snd_data_pkt);
942
943 // Ensure there are enough ports to use.
944 if (usedStorePorts < cacheStorePorts) {
945 ++usedStorePorts;
946 if (sendStore(snd_data_pkt)) {
947 storePostSend(snd_data_pkt);
948 } else {
949 DPRINTF(IEW, "D-Cache became blocked when writing"
950 " [sn:%lli] second packet, will retry later\n",
951 inst->seqNum);
952 }
953 } else {
954
955 // Store the packet for when there's free ports.
956 assert(pendingPkt == NULL);
957 pendingPkt = snd_data_pkt;
958 hasPendingPkt = true;
959 }
960 } else {
961
962 // Not a split store.
963 storePostSend(data_pkt);
964 }
965 }
966 }
967
968 // Not sure this should set it to 0.
969 usedStorePorts = 0;
970
971 assert(stores >= 0 && storesToWB >= 0);
972}
973
974/*template <class Impl>
975void
976LSQUnit<Impl>::removeMSHR(InstSeqNum seqNum)
977{
978 list<InstSeqNum>::iterator mshr_it = find(mshrSeqNums.begin(),
979 mshrSeqNums.end(),
980 seqNum);
981
982 if (mshr_it != mshrSeqNums.end()) {
983 mshrSeqNums.erase(mshr_it);
984 DPRINTF(LSQUnit, "Removing MSHR. count = %i\n",mshrSeqNums.size());
985 }
986}*/
987
988template <class Impl>
989void
990LSQUnit<Impl>::squash(const InstSeqNum &squashed_num)
991{
992 DPRINTF(LSQUnit, "Squashing until [sn:%lli]!"
993 "(Loads:%i Stores:%i)\n", squashed_num, loads, stores);
994
995 int load_idx = loadTail;
996 decrLdIdx(load_idx);
997
998 while (loads != 0 && loadQueue[load_idx]->seqNum > squashed_num) {
999 DPRINTF(LSQUnit,"Load Instruction PC %s squashed, "
1000 "[sn:%lli]\n",
1001 loadQueue[load_idx]->pcState(),
1002 loadQueue[load_idx]->seqNum);
1003
1004 if (isStalled() && load_idx == stallingLoadIdx) {
1005 stalled = false;
1006 stallingStoreIsn = 0;
1007 stallingLoadIdx = 0;
1008 }
1009
1010 // Clear the smart pointer to make sure it is decremented.
1011 loadQueue[load_idx]->setSquashed();
1012 loadQueue[load_idx] = NULL;
1013 --loads;
1014
1015 // Inefficient!
1016 loadTail = load_idx;
1017
1018 decrLdIdx(load_idx);
1019 ++lsqSquashedLoads;
1020 }
1021
1022 if (memDepViolator && squashed_num < memDepViolator->seqNum) {
1023 memDepViolator = NULL;
1024 }
1025
1026 int store_idx = storeTail;
1027 decrStIdx(store_idx);
1028
1029 while (stores != 0 &&
1030 storeQueue[store_idx].inst->seqNum > squashed_num) {
1031 // Instructions marked as can WB are already committed.
1032 if (storeQueue[store_idx].canWB) {
1033 break;
1034 }
1035
1036 DPRINTF(LSQUnit,"Store Instruction PC %s squashed, "
1037 "idx:%i [sn:%lli]\n",
1038 storeQueue[store_idx].inst->pcState(),
1039 store_idx, storeQueue[store_idx].inst->seqNum);
1040
1041 // I don't think this can happen. It should have been cleared
1042 // by the stalling load.
1043 if (isStalled() &&
1044 storeQueue[store_idx].inst->seqNum == stallingStoreIsn) {
1045 panic("Is stalled should have been cleared by stalling load!\n");
1046 stalled = false;
1047 stallingStoreIsn = 0;
1048 }
1049
1050 // Clear the smart pointer to make sure it is decremented.
1051 storeQueue[store_idx].inst->setSquashed();
1052 storeQueue[store_idx].inst = NULL;
1053 storeQueue[store_idx].canWB = 0;
1054
1055 // Must delete request now that it wasn't handed off to
1056 // memory. This is quite ugly. @todo: Figure out the proper
1057 // place to really handle request deletes.
1058 storeQueue[store_idx].req.reset();
1059 if (TheISA::HasUnalignedMemAcc && storeQueue[store_idx].isSplit) {
1060 storeQueue[store_idx].sreqLow.reset();
1061 storeQueue[store_idx].sreqHigh.reset();
1062 }
1063
1064 --stores;
1065
1066 // Inefficient!
1067 storeTail = store_idx;
1068
1069 decrStIdx(store_idx);
1070 ++lsqSquashedStores;
1071 }
1072}
1073
1074template <class Impl>
1075void
1076LSQUnit<Impl>::storePostSend(PacketPtr pkt)
1077{
1078 if (isStalled() &&
1079 storeQueue[storeWBIdx].inst->seqNum == stallingStoreIsn) {
1080 DPRINTF(LSQUnit, "Unstalling, stalling store [sn:%lli] "
1081 "load idx:%i\n",
1082 stallingStoreIsn, stallingLoadIdx);
1083 stalled = false;
1084 stallingStoreIsn = 0;
1085 iewStage->replayMemInst(loadQueue[stallingLoadIdx]);
1086 }
1087
1088 if (!storeQueue[storeWBIdx].inst->isStoreConditional()) {
1089 // The store is basically completed at this time. This
1090 // only works so long as the checker doesn't try to
1091 // verify the value in memory for stores.
1092 storeQueue[storeWBIdx].inst->setCompleted();
1093
1094 if (cpu->checker) {
1095 cpu->checker->verify(storeQueue[storeWBIdx].inst);
1096 }
1097 }
1098
1099 if (needsTSO) {
1100 storeInFlight = true;
1101 }
1102
1103 incrStIdx(storeWBIdx);
1104}
1105
1106template <class Impl>
1107void
1108LSQUnit<Impl>::writeback(const DynInstPtr &inst, PacketPtr pkt)
1109{
1110 iewStage->wakeCPU();
1111
1112 // Squashed instructions do not need to complete their access.
1113 if (inst->isSquashed()) {
1114 assert(!inst->isStore());
1115 ++lsqIgnoredResponses;
1116 return;
1117 }
1118
1119 if (!inst->isExecuted()) {
1120 inst->setExecuted();
1121
1122 if (inst->fault == NoFault) {
1123 // Complete access to copy data to proper place.
1124 inst->completeAcc(pkt);
1125 } else {
1126 // If the instruction has an outstanding fault, we cannot complete
1127 // the access as this discards the current fault.
1128
1129 // If we have an outstanding fault, the fault should only be of
1130 // type ReExec.
1131 assert(dynamic_cast<ReExec*>(inst->fault.get()) != nullptr);
1132
1133 DPRINTF(LSQUnit, "Not completing instruction [sn:%lli] access "
1134 "due to pending fault.\n", inst->seqNum);
1135 }
1136 }
1137
1138 // Need to insert instruction into queue to commit
1139 iewStage->instToCommit(inst);
1140
1141 iewStage->activityThisCycle();
1142
1143 // see if this load changed the PC
1144 iewStage->checkMisprediction(inst);
1145}
1146
1147template <class Impl>
1148void
1149LSQUnit<Impl>::completeStore(int store_idx)
1150{
1151 assert(storeQueue[store_idx].inst);
1152 storeQueue[store_idx].completed = true;
1153 --storesToWB;
1154 // A bit conservative because a store completion may not free up entries,
1155 // but hopefully avoids two store completions in one cycle from making
1156 // the CPU tick twice.
1157 cpu->wakeCPU();
1158 cpu->activityThisCycle();
1159
1160 if (store_idx == storeHead) {
1161 do {
1162 incrStIdx(storeHead);
1163
1164 --stores;
1165 } while (storeQueue[storeHead].completed &&
1166 storeHead != storeTail);
1167
1168 iewStage->updateLSQNextCycle = true;
1169 }
1170
1171 DPRINTF(LSQUnit, "Completing store [sn:%lli], idx:%i, store head "
1172 "idx:%i\n",
1173 storeQueue[store_idx].inst->seqNum, store_idx, storeHead);
1174
1175#if TRACING_ON
1176 if (DTRACE(O3PipeView)) {
1177 storeQueue[store_idx].inst->storeTick =
1178 curTick() - storeQueue[store_idx].inst->fetchTick;
1179 }
1180#endif
1181
1182 if (isStalled() &&
1183 storeQueue[store_idx].inst->seqNum == stallingStoreIsn) {
1184 DPRINTF(LSQUnit, "Unstalling, stalling store [sn:%lli] "
1185 "load idx:%i\n",
1186 stallingStoreIsn, stallingLoadIdx);
1187 stalled = false;
1188 stallingStoreIsn = 0;
1189 iewStage->replayMemInst(loadQueue[stallingLoadIdx]);
1190 }
1191
1192 storeQueue[store_idx].inst->setCompleted();
1193
1194 if (needsTSO) {
1195 storeInFlight = false;
1196 }
1197
1198 // Tell the checker we've completed this instruction. Some stores
1199 // may get reported twice to the checker, but the checker can
1200 // handle that case.
1201
1202 // Store conditionals cannot be sent to the checker yet, they have
1203 // to update the misc registers first which should take place
1204 // when they commit
1205 if (cpu->checker && !storeQueue[store_idx].inst->isStoreConditional()) {
1206 cpu->checker->verify(storeQueue[store_idx].inst);
1207 }
1208}
1209
1210template <class Impl>
1211bool
1212LSQUnit<Impl>::sendStore(PacketPtr data_pkt)
1213{
1214 if (!dcachePort->sendTimingReq(data_pkt)) {
1215 // Need to handle becoming blocked on a store.
1216 isStoreBlocked = true;
1217 ++lsqCacheBlocked;
1218 assert(retryPkt == NULL);
1219 retryPkt = data_pkt;
1220 return false;
1221 }
1222 return true;
1223}
1224
1225template <class Impl>
1226void
1227LSQUnit<Impl>::recvRetry()
1228{
1229 if (isStoreBlocked) {
1230 DPRINTF(LSQUnit, "Receiving retry: store blocked\n");
1231 assert(retryPkt != NULL);
1232
1233 LSQSenderState *state =
1234 dynamic_cast<LSQSenderState *>(retryPkt->senderState);
1235
1236 if (dcachePort->sendTimingReq(retryPkt)) {
1237 // Don't finish the store unless this is the last packet.
1238 if (!TheISA::HasUnalignedMemAcc || !state->pktToSend ||
1239 state->pendingPacket == retryPkt) {
1240 state->pktToSend = false;
1241 storePostSend(retryPkt);
1242 }
1243 retryPkt = NULL;
1244 isStoreBlocked = false;
1245
1246 // Send any outstanding packet.
1247 if (TheISA::HasUnalignedMemAcc && state->pktToSend) {
1248 assert(state->pendingPacket);
1249 if (sendStore(state->pendingPacket)) {
1250 storePostSend(state->pendingPacket);
1251 }
1252 }
1253 } else {
1254 // Still blocked!
1255 ++lsqCacheBlocked;
1256 }
1257 }
1258}
1259
1260template <class Impl>
1261inline void
1262LSQUnit<Impl>::incrStIdx(int &store_idx) const
1263{
1264 if (++store_idx >= SQEntries)
1265 store_idx = 0;
1266}
1267
1268template <class Impl>
1269inline void
1270LSQUnit<Impl>::decrStIdx(int &store_idx) const
1271{
1272 if (--store_idx < 0)
1273 store_idx += SQEntries;
1274}
1275
1276template <class Impl>
1277inline void
1278LSQUnit<Impl>::incrLdIdx(int &load_idx) const
1279{
1280 if (++load_idx >= LQEntries)
1281 load_idx = 0;
1282}
1283
1284template <class Impl>
1285inline void
1286LSQUnit<Impl>::decrLdIdx(int &load_idx) const
1287{
1288 if (--load_idx < 0)
1289 load_idx += LQEntries;
1290}
1291
1292template <class Impl>
1293void
1294LSQUnit<Impl>::dumpInsts() const
1295{
1296 cprintf("Load store queue: Dumping instructions.\n");
1297 cprintf("Load queue size: %i\n", loads);
1298 cprintf("Load queue: ");
1299
1300 int load_idx = loadHead;
1301
1302 while (load_idx != loadTail && loadQueue[load_idx]) {
1303 const DynInstPtr &inst(loadQueue[load_idx]);
1304 cprintf("%s.[sn:%i] ", inst->pcState(), inst->seqNum);
1305
1306 incrLdIdx(load_idx);
1307 }
1308 cprintf("\n");
1309
1310 cprintf("Store queue size: %i\n", stores);
1311 cprintf("Store queue: ");
1312
1313 int store_idx = storeHead;
1314
1315 while (store_idx != storeTail && storeQueue[store_idx].inst) {
1316 const DynInstPtr &inst(storeQueue[store_idx].inst);
1317 cprintf("%s.[sn:%i] ", inst->pcState(), inst->seqNum);
1318
1319 incrStIdx(store_idx);
1320 }
1321
1322 cprintf("\n");
1323}
1324
1325#endif//__CPU_O3_LSQ_UNIT_IMPL_HH__
| 168 depCheckShift = params->LSQDepCheckShift;
169 checkLoads = params->LSQCheckLoads;
170 cacheStorePorts = params->cacheStorePorts;
171 needsTSO = params->needsTSO;
172
173 resetState();
174}
175
176
177template<class Impl>
178void
179LSQUnit<Impl>::resetState()
180{
181 loads = stores = storesToWB = 0;
182
183 loadHead = loadTail = 0;
184
185 storeHead = storeWBIdx = storeTail = 0;
186
187 usedStorePorts = 0;
188
189 retryPkt = NULL;
190 memDepViolator = NULL;
191
192 stalled = false;
193
194 cacheBlockMask = ~(cpu->cacheLineSize() - 1);
195}
196
197template<class Impl>
198std::string
199LSQUnit<Impl>::name() const
200{
201 if (Impl::MaxThreads == 1) {
202 return iewStage->name() + ".lsq";
203 } else {
204 return iewStage->name() + ".lsq.thread" + std::to_string(lsqID);
205 }
206}
207
208template<class Impl>
209void
210LSQUnit<Impl>::regStats()
211{
212 lsqForwLoads
213 .name(name() + ".forwLoads")
214 .desc("Number of loads that had data forwarded from stores");
215
216 invAddrLoads
217 .name(name() + ".invAddrLoads")
218 .desc("Number of loads ignored due to an invalid address");
219
220 lsqSquashedLoads
221 .name(name() + ".squashedLoads")
222 .desc("Number of loads squashed");
223
224 lsqIgnoredResponses
225 .name(name() + ".ignoredResponses")
226 .desc("Number of memory responses ignored because the instruction is squashed");
227
228 lsqMemOrderViolation
229 .name(name() + ".memOrderViolation")
230 .desc("Number of memory ordering violations");
231
232 lsqSquashedStores
233 .name(name() + ".squashedStores")
234 .desc("Number of stores squashed");
235
236 invAddrSwpfs
237 .name(name() + ".invAddrSwpfs")
238 .desc("Number of software prefetches ignored due to an invalid address");
239
240 lsqBlockedLoads
241 .name(name() + ".blockedLoads")
242 .desc("Number of blocked loads due to partial load-store forwarding");
243
244 lsqRescheduledLoads
245 .name(name() + ".rescheduledLoads")
246 .desc("Number of loads that were rescheduled");
247
248 lsqCacheBlocked
249 .name(name() + ".cacheBlocked")
250 .desc("Number of times an access to memory failed due to the cache being blocked");
251}
252
253template<class Impl>
254void
255LSQUnit<Impl>::setDcachePort(MasterPort *dcache_port)
256{
257 dcachePort = dcache_port;
258}
259
260template<class Impl>
261void
262LSQUnit<Impl>::clearLQ()
263{
264 loadQueue.clear();
265}
266
267template<class Impl>
268void
269LSQUnit<Impl>::clearSQ()
270{
271 storeQueue.clear();
272}
273
274template<class Impl>
275void
276LSQUnit<Impl>::drainSanityCheck() const
277{
278 for (int i = 0; i < loadQueue.size(); ++i)
279 assert(!loadQueue[i]);
280
281 assert(storesToWB == 0);
282 assert(!retryPkt);
283}
284
285template<class Impl>
286void
287LSQUnit<Impl>::takeOverFrom()
288{
289 resetState();
290}
291
292template<class Impl>
293void
294LSQUnit<Impl>::resizeLQ(unsigned size)
295{
296 unsigned size_plus_sentinel = size + 1;
297 assert(size_plus_sentinel >= LQEntries);
298
299 if (size_plus_sentinel > LQEntries) {
300 while (size_plus_sentinel > loadQueue.size()) {
301 DynInstPtr dummy;
302 loadQueue.push_back(dummy);
303 LQEntries++;
304 }
305 } else {
306 LQEntries = size_plus_sentinel;
307 }
308
309 assert(LQEntries <= 256);
310}
311
312template<class Impl>
313void
314LSQUnit<Impl>::resizeSQ(unsigned size)
315{
316 unsigned size_plus_sentinel = size + 1;
317 if (size_plus_sentinel > SQEntries) {
318 while (size_plus_sentinel > storeQueue.size()) {
319 SQEntry dummy;
320 storeQueue.push_back(dummy);
321 SQEntries++;
322 }
323 } else {
324 SQEntries = size_plus_sentinel;
325 }
326
327 assert(SQEntries <= 256);
328}
329
330template <class Impl>
331void
332LSQUnit<Impl>::insert(const DynInstPtr &inst)
333{
334 assert(inst->isMemRef());
335
336 assert(inst->isLoad() || inst->isStore());
337
338 if (inst->isLoad()) {
339 insertLoad(inst);
340 } else {
341 insertStore(inst);
342 }
343
344 inst->setInLSQ();
345}
346
347template <class Impl>
348void
349LSQUnit<Impl>::insertLoad(const DynInstPtr &load_inst)
350{
351 assert((loadTail + 1) % LQEntries != loadHead);
352 assert(loads < LQEntries);
353
354 DPRINTF(LSQUnit, "Inserting load PC %s, idx:%i [sn:%lli]\n",
355 load_inst->pcState(), loadTail, load_inst->seqNum);
356
357 load_inst->lqIdx = loadTail;
358
359 if (stores == 0) {
360 load_inst->sqIdx = -1;
361 } else {
362 load_inst->sqIdx = storeTail;
363 }
364
365 loadQueue[loadTail] = load_inst;
366
367 incrLdIdx(loadTail);
368
369 ++loads;
370}
371
372template <class Impl>
373void
374LSQUnit<Impl>::insertStore(const DynInstPtr &store_inst)
375{
376 // Make sure it is not full before inserting an instruction.
377 assert((storeTail + 1) % SQEntries != storeHead);
378 assert(stores < SQEntries);
379
380 DPRINTF(LSQUnit, "Inserting store PC %s, idx:%i [sn:%lli]\n",
381 store_inst->pcState(), storeTail, store_inst->seqNum);
382
383 store_inst->sqIdx = storeTail;
384 store_inst->lqIdx = loadTail;
385
386 storeQueue[storeTail] = SQEntry(store_inst);
387
388 incrStIdx(storeTail);
389
390 ++stores;
391}
392
393template <class Impl>
394typename Impl::DynInstPtr
395LSQUnit<Impl>::getMemDepViolator()
396{
397 DynInstPtr temp = memDepViolator;
398
399 memDepViolator = NULL;
400
401 return temp;
402}
403
404template <class Impl>
405unsigned
406LSQUnit<Impl>::numFreeLoadEntries()
407{
408 //LQ has an extra dummy entry to differentiate
409 //empty/full conditions. Subtract 1 from the free entries.
410 DPRINTF(LSQUnit, "LQ size: %d, #loads occupied: %d\n", LQEntries, loads);
411 return LQEntries - loads - 1;
412}
413
414template <class Impl>
415unsigned
416LSQUnit<Impl>::numFreeStoreEntries()
417{
418 //SQ has an extra dummy entry to differentiate
419 //empty/full conditions. Subtract 1 from the free entries.
420 DPRINTF(LSQUnit, "SQ size: %d, #stores occupied: %d\n", SQEntries, stores);
421 return SQEntries - stores - 1;
422
423 }
424
425template <class Impl>
426void
427LSQUnit<Impl>::checkSnoop(PacketPtr pkt)
428{
429 // Should only ever get invalidations in here
430 assert(pkt->isInvalidate());
431
432 int load_idx = loadHead;
433 DPRINTF(LSQUnit, "Got snoop for address %#x\n", pkt->getAddr());
434
435 // Only Invalidate packet calls checkSnoop
436 assert(pkt->isInvalidate());
437 for (int x = 0; x < cpu->numContexts(); x++) {
438 ThreadContext *tc = cpu->getContext(x);
439 bool no_squash = cpu->thread[x]->noSquashFromTC;
440 cpu->thread[x]->noSquashFromTC = true;
441 TheISA::handleLockedSnoop(tc, pkt, cacheBlockMask);
442 cpu->thread[x]->noSquashFromTC = no_squash;
443 }
444
445 Addr invalidate_addr = pkt->getAddr() & cacheBlockMask;
446
447 DynInstPtr ld_inst = loadQueue[load_idx];
448 if (ld_inst) {
449 Addr load_addr_low = ld_inst->physEffAddrLow & cacheBlockMask;
450 Addr load_addr_high = ld_inst->physEffAddrHigh & cacheBlockMask;
451
452 // Check that this snoop didn't just invalidate our lock flag
453 if (ld_inst->effAddrValid() && (load_addr_low == invalidate_addr
454 || load_addr_high == invalidate_addr)
455 && ld_inst->memReqFlags & Request::LLSC)
456 TheISA::handleLockedSnoopHit(ld_inst.get());
457 }
458
459 // If this is the only load in the LSQ we don't care
460 if (load_idx == loadTail)
461 return;
462
463 incrLdIdx(load_idx);
464
465 bool force_squash = false;
466
467 while (load_idx != loadTail) {
468 DynInstPtr ld_inst = loadQueue[load_idx];
469
470 if (!ld_inst->effAddrValid() || ld_inst->strictlyOrdered()) {
471 incrLdIdx(load_idx);
472 continue;
473 }
474
475 Addr load_addr_low = ld_inst->physEffAddrLow & cacheBlockMask;
476 Addr load_addr_high = ld_inst->physEffAddrHigh & cacheBlockMask;
477
478 DPRINTF(LSQUnit, "-- inst [sn:%lli] load_addr: %#x to pktAddr:%#x\n",
479 ld_inst->seqNum, load_addr_low, invalidate_addr);
480
481 if ((load_addr_low == invalidate_addr
482 || load_addr_high == invalidate_addr) || force_squash) {
483 if (needsTSO) {
484 // If we have a TSO system, as all loads must be ordered with
485 // all other loads, this load as well as *all* subsequent loads
486 // need to be squashed to prevent possible load reordering.
487 force_squash = true;
488 }
489 if (ld_inst->possibleLoadViolation() || force_squash) {
490 DPRINTF(LSQUnit, "Conflicting load at addr %#x [sn:%lli]\n",
491 pkt->getAddr(), ld_inst->seqNum);
492
493 // Mark the load for re-execution
494 ld_inst->fault = std::make_shared<ReExec>();
495 } else {
496 DPRINTF(LSQUnit, "HitExternal Snoop for addr %#x [sn:%lli]\n",
497 pkt->getAddr(), ld_inst->seqNum);
498
499 // Make sure that we don't lose a snoop hitting a LOCKED
500 // address since the LOCK* flags don't get updated until
501 // commit.
502 if (ld_inst->memReqFlags & Request::LLSC)
503 TheISA::handleLockedSnoopHit(ld_inst.get());
504
505 // If a older load checks this and it's true
506 // then we might have missed the snoop
507 // in which case we need to invalidate to be sure
508 ld_inst->hitExternalSnoop(true);
509 }
510 }
511 incrLdIdx(load_idx);
512 }
513 return;
514}
515
516template <class Impl>
517Fault
518LSQUnit<Impl>::checkViolations(int load_idx, const DynInstPtr &inst)
519{
520 Addr inst_eff_addr1 = inst->effAddr >> depCheckShift;
521 Addr inst_eff_addr2 = (inst->effAddr + inst->effSize - 1) >> depCheckShift;
522
523 /** @todo in theory you only need to check an instruction that has executed
524 * however, there isn't a good way in the pipeline at the moment to check
525 * all instructions that will execute before the store writes back. Thus,
526 * like the implementation that came before it, we're overly conservative.
527 */
528 while (load_idx != loadTail) {
529 DynInstPtr ld_inst = loadQueue[load_idx];
530 if (!ld_inst->effAddrValid() || ld_inst->strictlyOrdered()) {
531 incrLdIdx(load_idx);
532 continue;
533 }
534
535 Addr ld_eff_addr1 = ld_inst->effAddr >> depCheckShift;
536 Addr ld_eff_addr2 =
537 (ld_inst->effAddr + ld_inst->effSize - 1) >> depCheckShift;
538
539 if (inst_eff_addr2 >= ld_eff_addr1 && inst_eff_addr1 <= ld_eff_addr2) {
540 if (inst->isLoad()) {
541 // If this load is to the same block as an external snoop
542 // invalidate that we've observed then the load needs to be
543 // squashed as it could have newer data
544 if (ld_inst->hitExternalSnoop()) {
545 if (!memDepViolator ||
546 ld_inst->seqNum < memDepViolator->seqNum) {
547 DPRINTF(LSQUnit, "Detected fault with inst [sn:%lli] "
548 "and [sn:%lli] at address %#x\n",
549 inst->seqNum, ld_inst->seqNum, ld_eff_addr1);
550 memDepViolator = ld_inst;
551
552 ++lsqMemOrderViolation;
553
554 return std::make_shared<GenericISA::M5PanicFault>(
555 "Detected fault with inst [sn:%lli] and "
556 "[sn:%lli] at address %#x\n",
557 inst->seqNum, ld_inst->seqNum, ld_eff_addr1);
558 }
559 }
560
561 // Otherwise, mark the load has a possible load violation
562 // and if we see a snoop before it's commited, we need to squash
563 ld_inst->possibleLoadViolation(true);
564 DPRINTF(LSQUnit, "Found possible load violation at addr: %#x"
565 " between instructions [sn:%lli] and [sn:%lli]\n",
566 inst_eff_addr1, inst->seqNum, ld_inst->seqNum);
567 } else {
568 // A load/store incorrectly passed this store.
569 // Check if we already have a violator, or if it's newer
570 // squash and refetch.
571 if (memDepViolator && ld_inst->seqNum > memDepViolator->seqNum)
572 break;
573
574 DPRINTF(LSQUnit, "Detected fault with inst [sn:%lli] and "
575 "[sn:%lli] at address %#x\n",
576 inst->seqNum, ld_inst->seqNum, ld_eff_addr1);
577 memDepViolator = ld_inst;
578
579 ++lsqMemOrderViolation;
580
581 return std::make_shared<GenericISA::M5PanicFault>(
582 "Detected fault with "
583 "inst [sn:%lli] and [sn:%lli] at address %#x\n",
584 inst->seqNum, ld_inst->seqNum, ld_eff_addr1);
585 }
586 }
587
588 incrLdIdx(load_idx);
589 }
590 return NoFault;
591}
592
593
594
595
596template <class Impl>
597Fault
598LSQUnit<Impl>::executeLoad(const DynInstPtr &inst)
599{
600 using namespace TheISA;
601 // Execute a specific load.
602 Fault load_fault = NoFault;
603
604 DPRINTF(LSQUnit, "Executing load PC %s, [sn:%lli]\n",
605 inst->pcState(), inst->seqNum);
606
607 assert(!inst->isSquashed());
608
609 load_fault = inst->initiateAcc();
610
611 if (inst->isTranslationDelayed() &&
612 load_fault == NoFault)
613 return load_fault;
614
615 // If the instruction faulted or predicated false, then we need to send it
616 // along to commit without the instruction completing.
617 if (load_fault != NoFault || !inst->readPredicate()) {
618 // Send this instruction to commit, also make sure iew stage
619 // realizes there is activity. Mark it as executed unless it
620 // is a strictly ordered load that needs to hit the head of
621 // commit.
622 if (!inst->readPredicate())
623 inst->forwardOldRegs();
624 DPRINTF(LSQUnit, "Load [sn:%lli] not executed from %s\n",
625 inst->seqNum,
626 (load_fault != NoFault ? "fault" : "predication"));
627 if (!(inst->hasRequest() && inst->strictlyOrdered()) ||
628 inst->isAtCommit()) {
629 inst->setExecuted();
630 }
631 iewStage->instToCommit(inst);
632 iewStage->activityThisCycle();
633 } else {
634 assert(inst->effAddrValid());
635 int load_idx = inst->lqIdx;
636 incrLdIdx(load_idx);
637
638 if (checkLoads)
639 return checkViolations(load_idx, inst);
640 }
641
642 return load_fault;
643}
644
645template <class Impl>
646Fault
647LSQUnit<Impl>::executeStore(const DynInstPtr &store_inst)
648{
649 using namespace TheISA;
650 // Make sure that a store exists.
651 assert(stores != 0);
652
653 int store_idx = store_inst->sqIdx;
654
655 DPRINTF(LSQUnit, "Executing store PC %s [sn:%lli]\n",
656 store_inst->pcState(), store_inst->seqNum);
657
658 assert(!store_inst->isSquashed());
659
660 // Check the recently completed loads to see if any match this store's
661 // address. If so, then we have a memory ordering violation.
662 int load_idx = store_inst->lqIdx;
663
664 Fault store_fault = store_inst->initiateAcc();
665
666 if (store_inst->isTranslationDelayed() &&
667 store_fault == NoFault)
668 return store_fault;
669
670 if (!store_inst->readPredicate()) {
671 DPRINTF(LSQUnit, "Store [sn:%lli] not executed from predication\n",
672 store_inst->seqNum);
673 store_inst->forwardOldRegs();
674 return store_fault;
675 }
676
677 if (storeQueue[store_idx].size == 0) {
678 DPRINTF(LSQUnit,"Fault on Store PC %s, [sn:%lli], Size = 0\n",
679 store_inst->pcState(), store_inst->seqNum);
680
681 return store_fault;
682 }
683
684 assert(store_fault == NoFault);
685
686 if (store_inst->isStoreConditional()) {
687 // Store conditionals need to set themselves as able to
688 // writeback if we haven't had a fault by here.
689 storeQueue[store_idx].canWB = true;
690
691 ++storesToWB;
692 }
693
694 return checkViolations(load_idx, store_inst);
695
696}
697
698template <class Impl>
699void
700LSQUnit<Impl>::commitLoad()
701{
702 assert(loadQueue[loadHead]);
703
704 DPRINTF(LSQUnit, "Committing head load instruction, PC %s\n",
705 loadQueue[loadHead]->pcState());
706
707 loadQueue[loadHead] = NULL;
708
709 incrLdIdx(loadHead);
710
711 --loads;
712}
713
714template <class Impl>
715void
716LSQUnit<Impl>::commitLoads(InstSeqNum &youngest_inst)
717{
718 assert(loads == 0 || loadQueue[loadHead]);
719
720 while (loads != 0 && loadQueue[loadHead]->seqNum <= youngest_inst) {
721 commitLoad();
722 }
723}
724
725template <class Impl>
726void
727LSQUnit<Impl>::commitStores(InstSeqNum &youngest_inst)
728{
729 assert(stores == 0 || storeQueue[storeHead].inst);
730
731 int store_idx = storeHead;
732
733 while (store_idx != storeTail) {
734 assert(storeQueue[store_idx].inst);
735 // Mark any stores that are now committed and have not yet
736 // been marked as able to write back.
737 if (!storeQueue[store_idx].canWB) {
738 if (storeQueue[store_idx].inst->seqNum > youngest_inst) {
739 break;
740 }
741 DPRINTF(LSQUnit, "Marking store as able to write back, PC "
742 "%s [sn:%lli]\n",
743 storeQueue[store_idx].inst->pcState(),
744 storeQueue[store_idx].inst->seqNum);
745
746 storeQueue[store_idx].canWB = true;
747
748 ++storesToWB;
749 }
750
751 incrStIdx(store_idx);
752 }
753}
754
755template <class Impl>
756void
757LSQUnit<Impl>::writebackPendingStore()
758{
759 if (hasPendingPkt) {
760 assert(pendingPkt != NULL);
761
762 // If the cache is blocked, this will store the packet for retry.
763 if (sendStore(pendingPkt)) {
764 storePostSend(pendingPkt);
765 }
766 pendingPkt = NULL;
767 hasPendingPkt = false;
768 }
769}
770
771template <class Impl>
772void
773LSQUnit<Impl>::writebackStores()
774{
775 // First writeback the second packet from any split store that didn't
776 // complete last cycle because there weren't enough cache ports available.
777 if (TheISA::HasUnalignedMemAcc) {
778 writebackPendingStore();
779 }
780
781 while (storesToWB > 0 &&
782 storeWBIdx != storeTail &&
783 storeQueue[storeWBIdx].inst &&
784 storeQueue[storeWBIdx].canWB &&
785 ((!needsTSO) || (!storeInFlight)) &&
786 usedStorePorts < cacheStorePorts) {
787
788 if (isStoreBlocked) {
789 DPRINTF(LSQUnit, "Unable to write back any more stores, cache"
790 " is blocked!\n");
791 break;
792 }
793
794 // Store didn't write any data so no need to write it back to
795 // memory.
796 if (storeQueue[storeWBIdx].size == 0) {
797 completeStore(storeWBIdx);
798
799 incrStIdx(storeWBIdx);
800
801 continue;
802 }
803
804 ++usedStorePorts;
805
806 if (storeQueue[storeWBIdx].inst->isDataPrefetch()) {
807 incrStIdx(storeWBIdx);
808
809 continue;
810 }
811
812 assert(storeQueue[storeWBIdx].req);
813 assert(!storeQueue[storeWBIdx].committed);
814
815 if (TheISA::HasUnalignedMemAcc && storeQueue[storeWBIdx].isSplit) {
816 assert(storeQueue[storeWBIdx].sreqLow);
817 assert(storeQueue[storeWBIdx].sreqHigh);
818 }
819
820 DynInstPtr inst = storeQueue[storeWBIdx].inst;
821
822 RequestPtr &req = storeQueue[storeWBIdx].req;
823 const RequestPtr &sreqLow = storeQueue[storeWBIdx].sreqLow;
824 const RequestPtr &sreqHigh = storeQueue[storeWBIdx].sreqHigh;
825
826 storeQueue[storeWBIdx].committed = true;
827
828 assert(!inst->memData);
829 inst->memData = new uint8_t[req->getSize()];
830
831 if (storeQueue[storeWBIdx].isAllZeros)
832 memset(inst->memData, 0, req->getSize());
833 else
834 memcpy(inst->memData, storeQueue[storeWBIdx].data, req->getSize());
835
836 PacketPtr data_pkt;
837 PacketPtr snd_data_pkt = NULL;
838
839 LSQSenderState *state = new LSQSenderState;
840 state->isLoad = false;
841 state->idx = storeWBIdx;
842 state->inst = inst;
843
844 if (!TheISA::HasUnalignedMemAcc || !storeQueue[storeWBIdx].isSplit) {
845
846 // Build a single data packet if the store isn't split.
847 data_pkt = Packet::createWrite(req);
848 data_pkt->dataStatic(inst->memData);
849 data_pkt->senderState = state;
850 } else {
851 // Create two packets if the store is split in two.
852 data_pkt = Packet::createWrite(sreqLow);
853 snd_data_pkt = Packet::createWrite(sreqHigh);
854
855 data_pkt->dataStatic(inst->memData);
856 snd_data_pkt->dataStatic(inst->memData + sreqLow->getSize());
857
858 data_pkt->senderState = state;
859 snd_data_pkt->senderState = state;
860
861 state->isSplit = true;
862 state->outstanding = 2;
863
864 // Can delete the main request now.
865 req = sreqLow;
866 }
867
868 DPRINTF(LSQUnit, "D-Cache: Writing back store idx:%i PC:%s "
869 "to Addr:%#x, data:%#x [sn:%lli]\n",
870 storeWBIdx, inst->pcState(),
871 req->getPaddr(), (int)*(inst->memData),
872 inst->seqNum);
873
874 // @todo: Remove this SC hack once the memory system handles it.
875 if (inst->isStoreConditional()) {
876 assert(!storeQueue[storeWBIdx].isSplit);
877 // Disable recording the result temporarily. Writing to
878 // misc regs normally updates the result, but this is not
879 // the desired behavior when handling store conditionals.
880 inst->recordResult(false);
881 bool success = TheISA::handleLockedWrite(inst.get(), req, cacheBlockMask);
882 inst->recordResult(true);
883
884 if (!success) {
885 // Instantly complete this store.
886 DPRINTF(LSQUnit, "Store conditional [sn:%lli] failed. "
887 "Instantly completing it.\n",
888 inst->seqNum);
889 WritebackEvent *wb = new WritebackEvent(inst, data_pkt, this);
890 cpu->schedule(wb, curTick() + 1);
891 completeStore(storeWBIdx);
892 incrStIdx(storeWBIdx);
893 continue;
894 }
895 } else {
896 // Non-store conditionals do not need a writeback.
897 state->noWB = true;
898 }
899
900 bool split =
901 TheISA::HasUnalignedMemAcc && storeQueue[storeWBIdx].isSplit;
902
903 ThreadContext *thread = cpu->tcBase(lsqID);
904
905 if (req->isMmappedIpr()) {
906 assert(!inst->isStoreConditional());
907 TheISA::handleIprWrite(thread, data_pkt);
908 delete data_pkt;
909 if (split) {
910 assert(snd_data_pkt->req->isMmappedIpr());
911 TheISA::handleIprWrite(thread, snd_data_pkt);
912 delete snd_data_pkt;
913 }
914 delete state;
915 completeStore(storeWBIdx);
916 incrStIdx(storeWBIdx);
917 } else if (!sendStore(data_pkt)) {
918 DPRINTF(IEW, "D-Cache became blocked when writing [sn:%lli], will"
919 "retry later\n",
920 inst->seqNum);
921
922 // Need to store the second packet, if split.
923 if (split) {
924 state->pktToSend = true;
925 state->pendingPacket = snd_data_pkt;
926 }
927 } else {
928
929 // If split, try to send the second packet too
930 if (split) {
931 assert(snd_data_pkt);
932
933 // Ensure there are enough ports to use.
934 if (usedStorePorts < cacheStorePorts) {
935 ++usedStorePorts;
936 if (sendStore(snd_data_pkt)) {
937 storePostSend(snd_data_pkt);
938 } else {
939 DPRINTF(IEW, "D-Cache became blocked when writing"
940 " [sn:%lli] second packet, will retry later\n",
941 inst->seqNum);
942 }
943 } else {
944
945 // Store the packet for when there's free ports.
946 assert(pendingPkt == NULL);
947 pendingPkt = snd_data_pkt;
948 hasPendingPkt = true;
949 }
950 } else {
951
952 // Not a split store.
953 storePostSend(data_pkt);
954 }
955 }
956 }
957
958 // Not sure this should set it to 0.
959 usedStorePorts = 0;
960
961 assert(stores >= 0 && storesToWB >= 0);
962}
963
964/*template <class Impl>
965void
966LSQUnit<Impl>::removeMSHR(InstSeqNum seqNum)
967{
968 list<InstSeqNum>::iterator mshr_it = find(mshrSeqNums.begin(),
969 mshrSeqNums.end(),
970 seqNum);
971
972 if (mshr_it != mshrSeqNums.end()) {
973 mshrSeqNums.erase(mshr_it);
974 DPRINTF(LSQUnit, "Removing MSHR. count = %i\n",mshrSeqNums.size());
975 }
976}*/
977
978template <class Impl>
979void
980LSQUnit<Impl>::squash(const InstSeqNum &squashed_num)
981{
982 DPRINTF(LSQUnit, "Squashing until [sn:%lli]!"
983 "(Loads:%i Stores:%i)\n", squashed_num, loads, stores);
984
985 int load_idx = loadTail;
986 decrLdIdx(load_idx);
987
988 while (loads != 0 && loadQueue[load_idx]->seqNum > squashed_num) {
989 DPRINTF(LSQUnit,"Load Instruction PC %s squashed, "
990 "[sn:%lli]\n",
991 loadQueue[load_idx]->pcState(),
992 loadQueue[load_idx]->seqNum);
993
994 if (isStalled() && load_idx == stallingLoadIdx) {
995 stalled = false;
996 stallingStoreIsn = 0;
997 stallingLoadIdx = 0;
998 }
999
1000 // Clear the smart pointer to make sure it is decremented.
1001 loadQueue[load_idx]->setSquashed();
1002 loadQueue[load_idx] = NULL;
1003 --loads;
1004
1005 // Inefficient!
1006 loadTail = load_idx;
1007
1008 decrLdIdx(load_idx);
1009 ++lsqSquashedLoads;
1010 }
1011
1012 if (memDepViolator && squashed_num < memDepViolator->seqNum) {
1013 memDepViolator = NULL;
1014 }
1015
1016 int store_idx = storeTail;
1017 decrStIdx(store_idx);
1018
1019 while (stores != 0 &&
1020 storeQueue[store_idx].inst->seqNum > squashed_num) {
1021 // Instructions marked as can WB are already committed.
1022 if (storeQueue[store_idx].canWB) {
1023 break;
1024 }
1025
1026 DPRINTF(LSQUnit,"Store Instruction PC %s squashed, "
1027 "idx:%i [sn:%lli]\n",
1028 storeQueue[store_idx].inst->pcState(),
1029 store_idx, storeQueue[store_idx].inst->seqNum);
1030
1031 // I don't think this can happen. It should have been cleared
1032 // by the stalling load.
1033 if (isStalled() &&
1034 storeQueue[store_idx].inst->seqNum == stallingStoreIsn) {
1035 panic("Is stalled should have been cleared by stalling load!\n");
1036 stalled = false;
1037 stallingStoreIsn = 0;
1038 }
1039
1040 // Clear the smart pointer to make sure it is decremented.
1041 storeQueue[store_idx].inst->setSquashed();
1042 storeQueue[store_idx].inst = NULL;
1043 storeQueue[store_idx].canWB = 0;
1044
1045 // Must delete request now that it wasn't handed off to
1046 // memory. This is quite ugly. @todo: Figure out the proper
1047 // place to really handle request deletes.
1048 storeQueue[store_idx].req.reset();
1049 if (TheISA::HasUnalignedMemAcc && storeQueue[store_idx].isSplit) {
1050 storeQueue[store_idx].sreqLow.reset();
1051 storeQueue[store_idx].sreqHigh.reset();
1052 }
1053
1054 --stores;
1055
1056 // Inefficient!
1057 storeTail = store_idx;
1058
1059 decrStIdx(store_idx);
1060 ++lsqSquashedStores;
1061 }
1062}
1063
1064template <class Impl>
1065void
1066LSQUnit<Impl>::storePostSend(PacketPtr pkt)
1067{
1068 if (isStalled() &&
1069 storeQueue[storeWBIdx].inst->seqNum == stallingStoreIsn) {
1070 DPRINTF(LSQUnit, "Unstalling, stalling store [sn:%lli] "
1071 "load idx:%i\n",
1072 stallingStoreIsn, stallingLoadIdx);
1073 stalled = false;
1074 stallingStoreIsn = 0;
1075 iewStage->replayMemInst(loadQueue[stallingLoadIdx]);
1076 }
1077
1078 if (!storeQueue[storeWBIdx].inst->isStoreConditional()) {
1079 // The store is basically completed at this time. This
1080 // only works so long as the checker doesn't try to
1081 // verify the value in memory for stores.
1082 storeQueue[storeWBIdx].inst->setCompleted();
1083
1084 if (cpu->checker) {
1085 cpu->checker->verify(storeQueue[storeWBIdx].inst);
1086 }
1087 }
1088
1089 if (needsTSO) {
1090 storeInFlight = true;
1091 }
1092
1093 incrStIdx(storeWBIdx);
1094}
1095
1096template <class Impl>
1097void
1098LSQUnit<Impl>::writeback(const DynInstPtr &inst, PacketPtr pkt)
1099{
1100 iewStage->wakeCPU();
1101
1102 // Squashed instructions do not need to complete their access.
1103 if (inst->isSquashed()) {
1104 assert(!inst->isStore());
1105 ++lsqIgnoredResponses;
1106 return;
1107 }
1108
1109 if (!inst->isExecuted()) {
1110 inst->setExecuted();
1111
1112 if (inst->fault == NoFault) {
1113 // Complete access to copy data to proper place.
1114 inst->completeAcc(pkt);
1115 } else {
1116 // If the instruction has an outstanding fault, we cannot complete
1117 // the access as this discards the current fault.
1118
1119 // If we have an outstanding fault, the fault should only be of
1120 // type ReExec.
1121 assert(dynamic_cast<ReExec*>(inst->fault.get()) != nullptr);
1122
1123 DPRINTF(LSQUnit, "Not completing instruction [sn:%lli] access "
1124 "due to pending fault.\n", inst->seqNum);
1125 }
1126 }
1127
1128 // Need to insert instruction into queue to commit
1129 iewStage->instToCommit(inst);
1130
1131 iewStage->activityThisCycle();
1132
1133 // see if this load changed the PC
1134 iewStage->checkMisprediction(inst);
1135}
1136
1137template <class Impl>
1138void
1139LSQUnit<Impl>::completeStore(int store_idx)
1140{
1141 assert(storeQueue[store_idx].inst);
1142 storeQueue[store_idx].completed = true;
1143 --storesToWB;
1144 // A bit conservative because a store completion may not free up entries,
1145 // but hopefully avoids two store completions in one cycle from making
1146 // the CPU tick twice.
1147 cpu->wakeCPU();
1148 cpu->activityThisCycle();
1149
1150 if (store_idx == storeHead) {
1151 do {
1152 incrStIdx(storeHead);
1153
1154 --stores;
1155 } while (storeQueue[storeHead].completed &&
1156 storeHead != storeTail);
1157
1158 iewStage->updateLSQNextCycle = true;
1159 }
1160
1161 DPRINTF(LSQUnit, "Completing store [sn:%lli], idx:%i, store head "
1162 "idx:%i\n",
1163 storeQueue[store_idx].inst->seqNum, store_idx, storeHead);
1164
1165#if TRACING_ON
1166 if (DTRACE(O3PipeView)) {
1167 storeQueue[store_idx].inst->storeTick =
1168 curTick() - storeQueue[store_idx].inst->fetchTick;
1169 }
1170#endif
1171
1172 if (isStalled() &&
1173 storeQueue[store_idx].inst->seqNum == stallingStoreIsn) {
1174 DPRINTF(LSQUnit, "Unstalling, stalling store [sn:%lli] "
1175 "load idx:%i\n",
1176 stallingStoreIsn, stallingLoadIdx);
1177 stalled = false;
1178 stallingStoreIsn = 0;
1179 iewStage->replayMemInst(loadQueue[stallingLoadIdx]);
1180 }
1181
1182 storeQueue[store_idx].inst->setCompleted();
1183
1184 if (needsTSO) {
1185 storeInFlight = false;
1186 }
1187
1188 // Tell the checker we've completed this instruction. Some stores
1189 // may get reported twice to the checker, but the checker can
1190 // handle that case.
1191
1192 // Store conditionals cannot be sent to the checker yet, they have
1193 // to update the misc registers first which should take place
1194 // when they commit
1195 if (cpu->checker && !storeQueue[store_idx].inst->isStoreConditional()) {
1196 cpu->checker->verify(storeQueue[store_idx].inst);
1197 }
1198}
1199
1200template <class Impl>
1201bool
1202LSQUnit<Impl>::sendStore(PacketPtr data_pkt)
1203{
1204 if (!dcachePort->sendTimingReq(data_pkt)) {
1205 // Need to handle becoming blocked on a store.
1206 isStoreBlocked = true;
1207 ++lsqCacheBlocked;
1208 assert(retryPkt == NULL);
1209 retryPkt = data_pkt;
1210 return false;
1211 }
1212 return true;
1213}
1214
1215template <class Impl>
1216void
1217LSQUnit<Impl>::recvRetry()
1218{
1219 if (isStoreBlocked) {
1220 DPRINTF(LSQUnit, "Receiving retry: store blocked\n");
1221 assert(retryPkt != NULL);
1222
1223 LSQSenderState *state =
1224 dynamic_cast<LSQSenderState *>(retryPkt->senderState);
1225
1226 if (dcachePort->sendTimingReq(retryPkt)) {
1227 // Don't finish the store unless this is the last packet.
1228 if (!TheISA::HasUnalignedMemAcc || !state->pktToSend ||
1229 state->pendingPacket == retryPkt) {
1230 state->pktToSend = false;
1231 storePostSend(retryPkt);
1232 }
1233 retryPkt = NULL;
1234 isStoreBlocked = false;
1235
1236 // Send any outstanding packet.
1237 if (TheISA::HasUnalignedMemAcc && state->pktToSend) {
1238 assert(state->pendingPacket);
1239 if (sendStore(state->pendingPacket)) {
1240 storePostSend(state->pendingPacket);
1241 }
1242 }
1243 } else {
1244 // Still blocked!
1245 ++lsqCacheBlocked;
1246 }
1247 }
1248}
1249
1250template <class Impl>
1251inline void
1252LSQUnit<Impl>::incrStIdx(int &store_idx) const
1253{
1254 if (++store_idx >= SQEntries)
1255 store_idx = 0;
1256}
1257
1258template <class Impl>
1259inline void
1260LSQUnit<Impl>::decrStIdx(int &store_idx) const
1261{
1262 if (--store_idx < 0)
1263 store_idx += SQEntries;
1264}
1265
1266template <class Impl>
1267inline void
1268LSQUnit<Impl>::incrLdIdx(int &load_idx) const
1269{
1270 if (++load_idx >= LQEntries)
1271 load_idx = 0;
1272}
1273
1274template <class Impl>
1275inline void
1276LSQUnit<Impl>::decrLdIdx(int &load_idx) const
1277{
1278 if (--load_idx < 0)
1279 load_idx += LQEntries;
1280}
1281
1282template <class Impl>
1283void
1284LSQUnit<Impl>::dumpInsts() const
1285{
1286 cprintf("Load store queue: Dumping instructions.\n");
1287 cprintf("Load queue size: %i\n", loads);
1288 cprintf("Load queue: ");
1289
1290 int load_idx = loadHead;
1291
1292 while (load_idx != loadTail && loadQueue[load_idx]) {
1293 const DynInstPtr &inst(loadQueue[load_idx]);
1294 cprintf("%s.[sn:%i] ", inst->pcState(), inst->seqNum);
1295
1296 incrLdIdx(load_idx);
1297 }
1298 cprintf("\n");
1299
1300 cprintf("Store queue size: %i\n", stores);
1301 cprintf("Store queue: ");
1302
1303 int store_idx = storeHead;
1304
1305 while (store_idx != storeTail && storeQueue[store_idx].inst) {
1306 const DynInstPtr &inst(storeQueue[store_idx].inst);
1307 cprintf("%s.[sn:%i] ", inst->pcState(), inst->seqNum);
1308
1309 incrStIdx(store_idx);
1310 }
1311
1312 cprintf("\n");
1313}
1314
1315#endif//__CPU_O3_LSQ_UNIT_IMPL_HH__
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