1
2/*
| 1
2/*
|
3 * Copyright (c) 2010-2013 ARM Limited
| 3 * Copyright (c) 2010-2014 ARM Limited
|
4 * Copyright (c) 2013 Advanced Micro Devices, Inc.
5 * All rights reserved
6 *
7 * The license below extends only to copyright in the software and shall
8 * not be construed as granting a license to any other intellectual
9 * property including but not limited to intellectual property relating
10 * to a hardware implementation of the functionality of the software
11 * licensed hereunder. You may use the software subject to the license
12 * terms below provided that you ensure that this notice is replicated
13 * unmodified and in its entirety in all distributions of the software,
14 * modified or unmodified, in source code or in binary form.
15 *
16 * Copyright (c) 2004-2005 The Regents of The University of Michigan
17 * All rights reserved.
18 *
19 * Redistribution and use in source and binary forms, with or without
20 * modification, are permitted provided that the following conditions are
21 * met: redistributions of source code must retain the above copyright
22 * notice, this list of conditions and the following disclaimer;
23 * redistributions in binary form must reproduce the above copyright
24 * notice, this list of conditions and the following disclaimer in the
25 * documentation and/or other materials provided with the distribution;
26 * neither the name of the copyright holders nor the names of its
27 * contributors may be used to endorse or promote products derived from
28 * this software without specific prior written permission.
29 *
30 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
31 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
32 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
33 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
34 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
35 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
36 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
37 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
38 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
39 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
40 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
41 *
42 * Authors: Kevin Lim
43 * Korey Sewell
44 */
45
46#ifndef __CPU_O3_LSQ_UNIT_IMPL_HH__
47#define __CPU_O3_LSQ_UNIT_IMPL_HH__
48
49#include "arch/generic/debugfaults.hh"
50#include "arch/locked_mem.hh"
51#include "base/str.hh"
52#include "config/the_isa.hh"
53#include "cpu/checker/cpu.hh"
54#include "cpu/o3/lsq.hh"
55#include "cpu/o3/lsq_unit.hh"
56#include "debug/Activity.hh"
57#include "debug/IEW.hh"
58#include "debug/LSQUnit.hh"
59#include "debug/O3PipeView.hh"
60#include "mem/packet.hh"
61#include "mem/request.hh"
62
63template<class Impl>
64LSQUnit<Impl>::WritebackEvent::WritebackEvent(DynInstPtr &_inst, PacketPtr _pkt,
65 LSQUnit *lsq_ptr)
66 : Event(Default_Pri, AutoDelete),
67 inst(_inst), pkt(_pkt), lsqPtr(lsq_ptr)
68{
69}
70
71template<class Impl>
72void
73LSQUnit<Impl>::WritebackEvent::process()
74{
75 assert(!lsqPtr->cpu->switchedOut());
76
77 lsqPtr->writeback(inst, pkt);
78
79 if (pkt->senderState)
80 delete pkt->senderState;
81
82 delete pkt->req;
83 delete pkt;
84}
85
86template<class Impl>
87const char *
88LSQUnit<Impl>::WritebackEvent::description() const
89{
90 return "Store writeback";
91}
92
93template<class Impl>
94void
95LSQUnit<Impl>::completeDataAccess(PacketPtr pkt)
96{
97 LSQSenderState *state = dynamic_cast<LSQSenderState *>(pkt->senderState);
98 DynInstPtr inst = state->inst;
99 DPRINTF(IEW, "Writeback event [sn:%lli].\n", inst->seqNum);
100 DPRINTF(Activity, "Activity: Writeback event [sn:%lli].\n", inst->seqNum);
101
| 4 * Copyright (c) 2013 Advanced Micro Devices, Inc.
5 * All rights reserved
6 *
7 * The license below extends only to copyright in the software and shall
8 * not be construed as granting a license to any other intellectual
9 * property including but not limited to intellectual property relating
10 * to a hardware implementation of the functionality of the software
11 * licensed hereunder. You may use the software subject to the license
12 * terms below provided that you ensure that this notice is replicated
13 * unmodified and in its entirety in all distributions of the software,
14 * modified or unmodified, in source code or in binary form.
15 *
16 * Copyright (c) 2004-2005 The Regents of The University of Michigan
17 * All rights reserved.
18 *
19 * Redistribution and use in source and binary forms, with or without
20 * modification, are permitted provided that the following conditions are
21 * met: redistributions of source code must retain the above copyright
22 * notice, this list of conditions and the following disclaimer;
23 * redistributions in binary form must reproduce the above copyright
24 * notice, this list of conditions and the following disclaimer in the
25 * documentation and/or other materials provided with the distribution;
26 * neither the name of the copyright holders nor the names of its
27 * contributors may be used to endorse or promote products derived from
28 * this software without specific prior written permission.
29 *
30 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
31 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
32 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
33 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
34 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
35 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
36 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
37 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
38 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
39 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
40 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
41 *
42 * Authors: Kevin Lim
43 * Korey Sewell
44 */
45
46#ifndef __CPU_O3_LSQ_UNIT_IMPL_HH__
47#define __CPU_O3_LSQ_UNIT_IMPL_HH__
48
49#include "arch/generic/debugfaults.hh"
50#include "arch/locked_mem.hh"
51#include "base/str.hh"
52#include "config/the_isa.hh"
53#include "cpu/checker/cpu.hh"
54#include "cpu/o3/lsq.hh"
55#include "cpu/o3/lsq_unit.hh"
56#include "debug/Activity.hh"
57#include "debug/IEW.hh"
58#include "debug/LSQUnit.hh"
59#include "debug/O3PipeView.hh"
60#include "mem/packet.hh"
61#include "mem/request.hh"
62
63template<class Impl>
64LSQUnit<Impl>::WritebackEvent::WritebackEvent(DynInstPtr &_inst, PacketPtr _pkt,
65 LSQUnit *lsq_ptr)
66 : Event(Default_Pri, AutoDelete),
67 inst(_inst), pkt(_pkt), lsqPtr(lsq_ptr)
68{
69}
70
71template<class Impl>
72void
73LSQUnit<Impl>::WritebackEvent::process()
74{
75 assert(!lsqPtr->cpu->switchedOut());
76
77 lsqPtr->writeback(inst, pkt);
78
79 if (pkt->senderState)
80 delete pkt->senderState;
81
82 delete pkt->req;
83 delete pkt;
84}
85
86template<class Impl>
87const char *
88LSQUnit<Impl>::WritebackEvent::description() const
89{
90 return "Store writeback";
91}
92
93template<class Impl>
94void
95LSQUnit<Impl>::completeDataAccess(PacketPtr pkt)
96{
97 LSQSenderState *state = dynamic_cast<LSQSenderState *>(pkt->senderState);
98 DynInstPtr inst = state->inst;
99 DPRINTF(IEW, "Writeback event [sn:%lli].\n", inst->seqNum);
100 DPRINTF(Activity, "Activity: Writeback event [sn:%lli].\n", inst->seqNum);
101
|
102 //iewStage->ldstQueue.removeMSHR(inst->threadNumber,inst->seqNum);
| 102 if (state->cacheBlocked) {
103 // This is the first half of a previous split load,
104 // where the 2nd half blocked, ignore this response
105 DPRINTF(IEW, "[sn:%lli]: Response from first half of earlier "
106 "blocked split load recieved. Ignoring.\n", inst->seqNum);
107 delete state;
108 delete pkt->req;
109 delete pkt;
110 return;
111 }
|
103
104 // If this is a split access, wait until all packets are received.
105 if (TheISA::HasUnalignedMemAcc && !state->complete()) {
106 delete pkt->req;
107 delete pkt;
108 return;
109 }
110
111 assert(!cpu->switchedOut());
112 if (!inst->isSquashed()) {
113 if (!state->noWB) {
114 if (!TheISA::HasUnalignedMemAcc || !state->isSplit ||
115 !state->isLoad) {
116 writeback(inst, pkt);
117 } else {
118 writeback(inst, state->mainPkt);
119 }
120 }
121
122 if (inst->isStore()) {
123 completeStore(state->idx);
124 }
125 }
126
127 if (TheISA::HasUnalignedMemAcc && state->isSplit && state->isLoad) {
128 delete state->mainPkt->req;
129 delete state->mainPkt;
130 }
131
132 pkt->req->setAccessLatency();
133 cpu->ppDataAccessComplete->notify(std::make_pair(inst, pkt));
134
135 delete state;
136 delete pkt->req;
137 delete pkt;
138}
139
140template <class Impl>
141LSQUnit<Impl>::LSQUnit()
142 : loads(0), stores(0), storesToWB(0), cacheBlockMask(0), stalled(false),
| 112
113 // If this is a split access, wait until all packets are received.
114 if (TheISA::HasUnalignedMemAcc && !state->complete()) {
115 delete pkt->req;
116 delete pkt;
117 return;
118 }
119
120 assert(!cpu->switchedOut());
121 if (!inst->isSquashed()) {
122 if (!state->noWB) {
123 if (!TheISA::HasUnalignedMemAcc || !state->isSplit ||
124 !state->isLoad) {
125 writeback(inst, pkt);
126 } else {
127 writeback(inst, state->mainPkt);
128 }
129 }
130
131 if (inst->isStore()) {
132 completeStore(state->idx);
133 }
134 }
135
136 if (TheISA::HasUnalignedMemAcc && state->isSplit && state->isLoad) {
137 delete state->mainPkt->req;
138 delete state->mainPkt;
139 }
140
141 pkt->req->setAccessLatency();
142 cpu->ppDataAccessComplete->notify(std::make_pair(inst, pkt));
143
144 delete state;
145 delete pkt->req;
146 delete pkt;
147}
148
149template <class Impl>
150LSQUnit<Impl>::LSQUnit()
151 : loads(0), stores(0), storesToWB(0), cacheBlockMask(0), stalled(false),
|
143 isStoreBlocked(false), isLoadBlocked(false),
144 loadBlockedHandled(false), storeInFlight(false), hasPendingPkt(false)
| 152 isStoreBlocked(false), storeInFlight(false), hasPendingPkt(false)
|
145{
146}
147
148template<class Impl>
149void
150LSQUnit<Impl>::init(O3CPU *cpu_ptr, IEW *iew_ptr, DerivO3CPUParams *params,
151 LSQ *lsq_ptr, unsigned maxLQEntries, unsigned maxSQEntries,
152 unsigned id)
153{
154 cpu = cpu_ptr;
155 iewStage = iew_ptr;
156
157 lsq = lsq_ptr;
158
159 lsqID = id;
160
161 DPRINTF(LSQUnit, "Creating LSQUnit%i object.\n",id);
162
163 // Add 1 for the sentinel entry (they are circular queues).
164 LQEntries = maxLQEntries + 1;
165 SQEntries = maxSQEntries + 1;
166
167 //Due to uint8_t index in LSQSenderState
168 assert(LQEntries <= 256);
169 assert(SQEntries <= 256);
170
171 loadQueue.resize(LQEntries);
172 storeQueue.resize(SQEntries);
173
174 depCheckShift = params->LSQDepCheckShift;
175 checkLoads = params->LSQCheckLoads;
176 cachePorts = params->cachePorts;
177 needsTSO = params->needsTSO;
178
179 resetState();
180}
181
182
183template<class Impl>
184void
185LSQUnit<Impl>::resetState()
186{
187 loads = stores = storesToWB = 0;
188
189 loadHead = loadTail = 0;
190
191 storeHead = storeWBIdx = storeTail = 0;
192
193 usedPorts = 0;
194
195 retryPkt = NULL;
196 memDepViolator = NULL;
197
| 153{
154}
155
156template<class Impl>
157void
158LSQUnit<Impl>::init(O3CPU *cpu_ptr, IEW *iew_ptr, DerivO3CPUParams *params,
159 LSQ *lsq_ptr, unsigned maxLQEntries, unsigned maxSQEntries,
160 unsigned id)
161{
162 cpu = cpu_ptr;
163 iewStage = iew_ptr;
164
165 lsq = lsq_ptr;
166
167 lsqID = id;
168
169 DPRINTF(LSQUnit, "Creating LSQUnit%i object.\n",id);
170
171 // Add 1 for the sentinel entry (they are circular queues).
172 LQEntries = maxLQEntries + 1;
173 SQEntries = maxSQEntries + 1;
174
175 //Due to uint8_t index in LSQSenderState
176 assert(LQEntries <= 256);
177 assert(SQEntries <= 256);
178
179 loadQueue.resize(LQEntries);
180 storeQueue.resize(SQEntries);
181
182 depCheckShift = params->LSQDepCheckShift;
183 checkLoads = params->LSQCheckLoads;
184 cachePorts = params->cachePorts;
185 needsTSO = params->needsTSO;
186
187 resetState();
188}
189
190
191template<class Impl>
192void
193LSQUnit<Impl>::resetState()
194{
195 loads = stores = storesToWB = 0;
196
197 loadHead = loadTail = 0;
198
199 storeHead = storeWBIdx = storeTail = 0;
200
201 usedPorts = 0;
202
203 retryPkt = NULL;
204 memDepViolator = NULL;
205
|
198 blockedLoadSeqNum = 0;
199
| |
200 stalled = false;
| 206 stalled = false;
|
201 isLoadBlocked = false;
202 loadBlockedHandled = false;
| |
203
204 cacheBlockMask = ~(cpu->cacheLineSize() - 1);
205}
206
207template<class Impl>
208std::string
209LSQUnit<Impl>::name() const
210{
211 if (Impl::MaxThreads == 1) {
212 return iewStage->name() + ".lsq";
213 } else {
214 return iewStage->name() + ".lsq.thread" + to_string(lsqID);
215 }
216}
217
218template<class Impl>
219void
220LSQUnit<Impl>::regStats()
221{
222 lsqForwLoads
223 .name(name() + ".forwLoads")
224 .desc("Number of loads that had data forwarded from stores");
225
226 invAddrLoads
227 .name(name() + ".invAddrLoads")
228 .desc("Number of loads ignored due to an invalid address");
229
230 lsqSquashedLoads
231 .name(name() + ".squashedLoads")
232 .desc("Number of loads squashed");
233
234 lsqIgnoredResponses
235 .name(name() + ".ignoredResponses")
236 .desc("Number of memory responses ignored because the instruction is squashed");
237
238 lsqMemOrderViolation
239 .name(name() + ".memOrderViolation")
240 .desc("Number of memory ordering violations");
241
242 lsqSquashedStores
243 .name(name() + ".squashedStores")
244 .desc("Number of stores squashed");
245
246 invAddrSwpfs
247 .name(name() + ".invAddrSwpfs")
248 .desc("Number of software prefetches ignored due to an invalid address");
249
250 lsqBlockedLoads
251 .name(name() + ".blockedLoads")
252 .desc("Number of blocked loads due to partial load-store forwarding");
253
254 lsqRescheduledLoads
255 .name(name() + ".rescheduledLoads")
256 .desc("Number of loads that were rescheduled");
257
258 lsqCacheBlocked
259 .name(name() + ".cacheBlocked")
260 .desc("Number of times an access to memory failed due to the cache being blocked");
261}
262
263template<class Impl>
264void
265LSQUnit<Impl>::setDcachePort(MasterPort *dcache_port)
266{
267 dcachePort = dcache_port;
268}
269
270template<class Impl>
271void
272LSQUnit<Impl>::clearLQ()
273{
274 loadQueue.clear();
275}
276
277template<class Impl>
278void
279LSQUnit<Impl>::clearSQ()
280{
281 storeQueue.clear();
282}
283
284template<class Impl>
285void
286LSQUnit<Impl>::drainSanityCheck() const
287{
288 for (int i = 0; i < loadQueue.size(); ++i)
289 assert(!loadQueue[i]);
290
291 assert(storesToWB == 0);
292 assert(!retryPkt);
293}
294
295template<class Impl>
296void
297LSQUnit<Impl>::takeOverFrom()
298{
299 resetState();
300}
301
302template<class Impl>
303void
304LSQUnit<Impl>::resizeLQ(unsigned size)
305{
306 unsigned size_plus_sentinel = size + 1;
307 assert(size_plus_sentinel >= LQEntries);
308
309 if (size_plus_sentinel > LQEntries) {
310 while (size_plus_sentinel > loadQueue.size()) {
311 DynInstPtr dummy;
312 loadQueue.push_back(dummy);
313 LQEntries++;
314 }
315 } else {
316 LQEntries = size_plus_sentinel;
317 }
318
319 assert(LQEntries <= 256);
320}
321
322template<class Impl>
323void
324LSQUnit<Impl>::resizeSQ(unsigned size)
325{
326 unsigned size_plus_sentinel = size + 1;
327 if (size_plus_sentinel > SQEntries) {
328 while (size_plus_sentinel > storeQueue.size()) {
329 SQEntry dummy;
330 storeQueue.push_back(dummy);
331 SQEntries++;
332 }
333 } else {
334 SQEntries = size_plus_sentinel;
335 }
336
337 assert(SQEntries <= 256);
338}
339
340template <class Impl>
341void
342LSQUnit<Impl>::insert(DynInstPtr &inst)
343{
344 assert(inst->isMemRef());
345
346 assert(inst->isLoad() || inst->isStore());
347
348 if (inst->isLoad()) {
349 insertLoad(inst);
350 } else {
351 insertStore(inst);
352 }
353
354 inst->setInLSQ();
355}
356
357template <class Impl>
358void
359LSQUnit<Impl>::insertLoad(DynInstPtr &load_inst)
360{
361 assert((loadTail + 1) % LQEntries != loadHead);
362 assert(loads < LQEntries);
363
364 DPRINTF(LSQUnit, "Inserting load PC %s, idx:%i [sn:%lli]\n",
365 load_inst->pcState(), loadTail, load_inst->seqNum);
366
367 load_inst->lqIdx = loadTail;
368
369 if (stores == 0) {
370 load_inst->sqIdx = -1;
371 } else {
372 load_inst->sqIdx = storeTail;
373 }
374
375 loadQueue[loadTail] = load_inst;
376
377 incrLdIdx(loadTail);
378
379 ++loads;
380}
381
382template <class Impl>
383void
384LSQUnit<Impl>::insertStore(DynInstPtr &store_inst)
385{
386 // Make sure it is not full before inserting an instruction.
387 assert((storeTail + 1) % SQEntries != storeHead);
388 assert(stores < SQEntries);
389
390 DPRINTF(LSQUnit, "Inserting store PC %s, idx:%i [sn:%lli]\n",
391 store_inst->pcState(), storeTail, store_inst->seqNum);
392
393 store_inst->sqIdx = storeTail;
394 store_inst->lqIdx = loadTail;
395
396 storeQueue[storeTail] = SQEntry(store_inst);
397
398 incrStIdx(storeTail);
399
400 ++stores;
401}
402
403template <class Impl>
404typename Impl::DynInstPtr
405LSQUnit<Impl>::getMemDepViolator()
406{
407 DynInstPtr temp = memDepViolator;
408
409 memDepViolator = NULL;
410
411 return temp;
412}
413
414template <class Impl>
415unsigned
416LSQUnit<Impl>::numFreeLoadEntries()
417{
418 //LQ has an extra dummy entry to differentiate
419 //empty/full conditions. Subtract 1 from the free entries.
420 DPRINTF(LSQUnit, "LQ size: %d, #loads occupied: %d\n", LQEntries, loads);
421 return LQEntries - loads - 1;
422}
423
424template <class Impl>
425unsigned
426LSQUnit<Impl>::numFreeStoreEntries()
427{
428 //SQ has an extra dummy entry to differentiate
429 //empty/full conditions. Subtract 1 from the free entries.
430 DPRINTF(LSQUnit, "SQ size: %d, #stores occupied: %d\n", SQEntries, stores);
431 return SQEntries - stores - 1;
432
433 }
434
435template <class Impl>
436void
437LSQUnit<Impl>::checkSnoop(PacketPtr pkt)
438{
439 int load_idx = loadHead;
440 DPRINTF(LSQUnit, "Got snoop for address %#x\n", pkt->getAddr());
441
442 // Unlock the cpu-local monitor when the CPU sees a snoop to a locked
443 // address. The CPU can speculatively execute a LL operation after a pending
444 // SC operation in the pipeline and that can make the cache monitor the CPU
445 // is connected to valid while it really shouldn't be.
446 for (int x = 0; x < cpu->numContexts(); x++) {
447 ThreadContext *tc = cpu->getContext(x);
448 bool no_squash = cpu->thread[x]->noSquashFromTC;
449 cpu->thread[x]->noSquashFromTC = true;
450 TheISA::handleLockedSnoop(tc, pkt, cacheBlockMask);
451 cpu->thread[x]->noSquashFromTC = no_squash;
452 }
453
454 Addr invalidate_addr = pkt->getAddr() & cacheBlockMask;
455
456 DynInstPtr ld_inst = loadQueue[load_idx];
457 if (ld_inst) {
458 Addr load_addr = ld_inst->physEffAddr & cacheBlockMask;
459 // Check that this snoop didn't just invalidate our lock flag
460 if (ld_inst->effAddrValid() && load_addr == invalidate_addr &&
461 ld_inst->memReqFlags & Request::LLSC)
462 TheISA::handleLockedSnoopHit(ld_inst.get());
463 }
464
465 // If this is the only load in the LSQ we don't care
466 if (load_idx == loadTail)
467 return;
468
469 incrLdIdx(load_idx);
470
471 bool force_squash = false;
472
473 while (load_idx != loadTail) {
474 DynInstPtr ld_inst = loadQueue[load_idx];
475
476 if (!ld_inst->effAddrValid() || ld_inst->uncacheable()) {
477 incrLdIdx(load_idx);
478 continue;
479 }
480
481 Addr load_addr = ld_inst->physEffAddr & cacheBlockMask;
482 DPRINTF(LSQUnit, "-- inst [sn:%lli] load_addr: %#x to pktAddr:%#x\n",
483 ld_inst->seqNum, load_addr, invalidate_addr);
484
485 if (load_addr == invalidate_addr || force_squash) {
486 if (needsTSO) {
487 // If we have a TSO system, as all loads must be ordered with
488 // all other loads, this load as well as *all* subsequent loads
489 // need to be squashed to prevent possible load reordering.
490 force_squash = true;
491 }
492 if (ld_inst->possibleLoadViolation() || force_squash) {
493 DPRINTF(LSQUnit, "Conflicting load at addr %#x [sn:%lli]\n",
494 pkt->getAddr(), ld_inst->seqNum);
495
496 // Mark the load for re-execution
497 ld_inst->fault = new ReExec;
498 } else {
499 DPRINTF(LSQUnit, "HitExternal Snoop for addr %#x [sn:%lli]\n",
500 pkt->getAddr(), ld_inst->seqNum);
501
502 // Make sure that we don't lose a snoop hitting a LOCKED
503 // address since the LOCK* flags don't get updated until
504 // commit.
505 if (ld_inst->memReqFlags & Request::LLSC)
506 TheISA::handleLockedSnoopHit(ld_inst.get());
507
508 // If a older load checks this and it's true
509 // then we might have missed the snoop
510 // in which case we need to invalidate to be sure
511 ld_inst->hitExternalSnoop(true);
512 }
513 }
514 incrLdIdx(load_idx);
515 }
516 return;
517}
518
519template <class Impl>
520Fault
521LSQUnit<Impl>::checkViolations(int load_idx, DynInstPtr &inst)
522{
523 Addr inst_eff_addr1 = inst->effAddr >> depCheckShift;
524 Addr inst_eff_addr2 = (inst->effAddr + inst->effSize - 1) >> depCheckShift;
525
526 /** @todo in theory you only need to check an instruction that has executed
527 * however, there isn't a good way in the pipeline at the moment to check
528 * all instructions that will execute before the store writes back. Thus,
529 * like the implementation that came before it, we're overly conservative.
530 */
531 while (load_idx != loadTail) {
532 DynInstPtr ld_inst = loadQueue[load_idx];
533 if (!ld_inst->effAddrValid() || ld_inst->uncacheable()) {
534 incrLdIdx(load_idx);
535 continue;
536 }
537
538 Addr ld_eff_addr1 = ld_inst->effAddr >> depCheckShift;
539 Addr ld_eff_addr2 =
540 (ld_inst->effAddr + ld_inst->effSize - 1) >> depCheckShift;
541
542 if (inst_eff_addr2 >= ld_eff_addr1 && inst_eff_addr1 <= ld_eff_addr2) {
543 if (inst->isLoad()) {
544 // If this load is to the same block as an external snoop
545 // invalidate that we've observed then the load needs to be
546 // squashed as it could have newer data
547 if (ld_inst->hitExternalSnoop()) {
548 if (!memDepViolator ||
549 ld_inst->seqNum < memDepViolator->seqNum) {
550 DPRINTF(LSQUnit, "Detected fault with inst [sn:%lli] "
551 "and [sn:%lli] at address %#x\n",
552 inst->seqNum, ld_inst->seqNum, ld_eff_addr1);
553 memDepViolator = ld_inst;
554
555 ++lsqMemOrderViolation;
556
557 return new GenericISA::M5PanicFault(
558 "Detected fault with inst [sn:%lli] and "
559 "[sn:%lli] at address %#x\n",
560 inst->seqNum, ld_inst->seqNum, ld_eff_addr1);
561 }
562 }
563
564 // Otherwise, mark the load has a possible load violation
565 // and if we see a snoop before it's commited, we need to squash
566 ld_inst->possibleLoadViolation(true);
567 DPRINTF(LSQUnit, "Found possible load violaiton at addr: %#x"
568 " between instructions [sn:%lli] and [sn:%lli]\n",
569 inst_eff_addr1, inst->seqNum, ld_inst->seqNum);
570 } else {
571 // A load/store incorrectly passed this store.
572 // Check if we already have a violator, or if it's newer
573 // squash and refetch.
574 if (memDepViolator && ld_inst->seqNum > memDepViolator->seqNum)
575 break;
576
577 DPRINTF(LSQUnit, "Detected fault with inst [sn:%lli] and "
578 "[sn:%lli] at address %#x\n",
579 inst->seqNum, ld_inst->seqNum, ld_eff_addr1);
580 memDepViolator = ld_inst;
581
582 ++lsqMemOrderViolation;
583
584 return new GenericISA::M5PanicFault("Detected fault with "
585 "inst [sn:%lli] and [sn:%lli] at address %#x\n",
586 inst->seqNum, ld_inst->seqNum, ld_eff_addr1);
587 }
588 }
589
590 incrLdIdx(load_idx);
591 }
592 return NoFault;
593}
594
595
596
597
598template <class Impl>
599Fault
600LSQUnit<Impl>::executeLoad(DynInstPtr &inst)
601{
602 using namespace TheISA;
603 // Execute a specific load.
604 Fault load_fault = NoFault;
605
606 DPRINTF(LSQUnit, "Executing load PC %s, [sn:%lli]\n",
607 inst->pcState(), inst->seqNum);
608
609 assert(!inst->isSquashed());
610
611 load_fault = inst->initiateAcc();
612
613 if (inst->isTranslationDelayed() &&
614 load_fault == NoFault)
615 return load_fault;
616
617 // If the instruction faulted or predicated false, then we need to send it
618 // along to commit without the instruction completing.
619 if (load_fault != NoFault || !inst->readPredicate()) {
620 // Send this instruction to commit, also make sure iew stage
621 // realizes there is activity.
622 // Mark it as executed unless it is an uncached load that
623 // needs to hit the head of commit.
624 if (!inst->readPredicate())
625 inst->forwardOldRegs();
626 DPRINTF(LSQUnit, "Load [sn:%lli] not executed from %s\n",
627 inst->seqNum,
628 (load_fault != NoFault ? "fault" : "predication"));
629 if (!(inst->hasRequest() && inst->uncacheable()) ||
630 inst->isAtCommit()) {
631 inst->setExecuted();
632 }
633 iewStage->instToCommit(inst);
634 iewStage->activityThisCycle();
| 207
208 cacheBlockMask = ~(cpu->cacheLineSize() - 1);
209}
210
211template<class Impl>
212std::string
213LSQUnit<Impl>::name() const
214{
215 if (Impl::MaxThreads == 1) {
216 return iewStage->name() + ".lsq";
217 } else {
218 return iewStage->name() + ".lsq.thread" + to_string(lsqID);
219 }
220}
221
222template<class Impl>
223void
224LSQUnit<Impl>::regStats()
225{
226 lsqForwLoads
227 .name(name() + ".forwLoads")
228 .desc("Number of loads that had data forwarded from stores");
229
230 invAddrLoads
231 .name(name() + ".invAddrLoads")
232 .desc("Number of loads ignored due to an invalid address");
233
234 lsqSquashedLoads
235 .name(name() + ".squashedLoads")
236 .desc("Number of loads squashed");
237
238 lsqIgnoredResponses
239 .name(name() + ".ignoredResponses")
240 .desc("Number of memory responses ignored because the instruction is squashed");
241
242 lsqMemOrderViolation
243 .name(name() + ".memOrderViolation")
244 .desc("Number of memory ordering violations");
245
246 lsqSquashedStores
247 .name(name() + ".squashedStores")
248 .desc("Number of stores squashed");
249
250 invAddrSwpfs
251 .name(name() + ".invAddrSwpfs")
252 .desc("Number of software prefetches ignored due to an invalid address");
253
254 lsqBlockedLoads
255 .name(name() + ".blockedLoads")
256 .desc("Number of blocked loads due to partial load-store forwarding");
257
258 lsqRescheduledLoads
259 .name(name() + ".rescheduledLoads")
260 .desc("Number of loads that were rescheduled");
261
262 lsqCacheBlocked
263 .name(name() + ".cacheBlocked")
264 .desc("Number of times an access to memory failed due to the cache being blocked");
265}
266
267template<class Impl>
268void
269LSQUnit<Impl>::setDcachePort(MasterPort *dcache_port)
270{
271 dcachePort = dcache_port;
272}
273
274template<class Impl>
275void
276LSQUnit<Impl>::clearLQ()
277{
278 loadQueue.clear();
279}
280
281template<class Impl>
282void
283LSQUnit<Impl>::clearSQ()
284{
285 storeQueue.clear();
286}
287
288template<class Impl>
289void
290LSQUnit<Impl>::drainSanityCheck() const
291{
292 for (int i = 0; i < loadQueue.size(); ++i)
293 assert(!loadQueue[i]);
294
295 assert(storesToWB == 0);
296 assert(!retryPkt);
297}
298
299template<class Impl>
300void
301LSQUnit<Impl>::takeOverFrom()
302{
303 resetState();
304}
305
306template<class Impl>
307void
308LSQUnit<Impl>::resizeLQ(unsigned size)
309{
310 unsigned size_plus_sentinel = size + 1;
311 assert(size_plus_sentinel >= LQEntries);
312
313 if (size_plus_sentinel > LQEntries) {
314 while (size_plus_sentinel > loadQueue.size()) {
315 DynInstPtr dummy;
316 loadQueue.push_back(dummy);
317 LQEntries++;
318 }
319 } else {
320 LQEntries = size_plus_sentinel;
321 }
322
323 assert(LQEntries <= 256);
324}
325
326template<class Impl>
327void
328LSQUnit<Impl>::resizeSQ(unsigned size)
329{
330 unsigned size_plus_sentinel = size + 1;
331 if (size_plus_sentinel > SQEntries) {
332 while (size_plus_sentinel > storeQueue.size()) {
333 SQEntry dummy;
334 storeQueue.push_back(dummy);
335 SQEntries++;
336 }
337 } else {
338 SQEntries = size_plus_sentinel;
339 }
340
341 assert(SQEntries <= 256);
342}
343
344template <class Impl>
345void
346LSQUnit<Impl>::insert(DynInstPtr &inst)
347{
348 assert(inst->isMemRef());
349
350 assert(inst->isLoad() || inst->isStore());
351
352 if (inst->isLoad()) {
353 insertLoad(inst);
354 } else {
355 insertStore(inst);
356 }
357
358 inst->setInLSQ();
359}
360
361template <class Impl>
362void
363LSQUnit<Impl>::insertLoad(DynInstPtr &load_inst)
364{
365 assert((loadTail + 1) % LQEntries != loadHead);
366 assert(loads < LQEntries);
367
368 DPRINTF(LSQUnit, "Inserting load PC %s, idx:%i [sn:%lli]\n",
369 load_inst->pcState(), loadTail, load_inst->seqNum);
370
371 load_inst->lqIdx = loadTail;
372
373 if (stores == 0) {
374 load_inst->sqIdx = -1;
375 } else {
376 load_inst->sqIdx = storeTail;
377 }
378
379 loadQueue[loadTail] = load_inst;
380
381 incrLdIdx(loadTail);
382
383 ++loads;
384}
385
386template <class Impl>
387void
388LSQUnit<Impl>::insertStore(DynInstPtr &store_inst)
389{
390 // Make sure it is not full before inserting an instruction.
391 assert((storeTail + 1) % SQEntries != storeHead);
392 assert(stores < SQEntries);
393
394 DPRINTF(LSQUnit, "Inserting store PC %s, idx:%i [sn:%lli]\n",
395 store_inst->pcState(), storeTail, store_inst->seqNum);
396
397 store_inst->sqIdx = storeTail;
398 store_inst->lqIdx = loadTail;
399
400 storeQueue[storeTail] = SQEntry(store_inst);
401
402 incrStIdx(storeTail);
403
404 ++stores;
405}
406
407template <class Impl>
408typename Impl::DynInstPtr
409LSQUnit<Impl>::getMemDepViolator()
410{
411 DynInstPtr temp = memDepViolator;
412
413 memDepViolator = NULL;
414
415 return temp;
416}
417
418template <class Impl>
419unsigned
420LSQUnit<Impl>::numFreeLoadEntries()
421{
422 //LQ has an extra dummy entry to differentiate
423 //empty/full conditions. Subtract 1 from the free entries.
424 DPRINTF(LSQUnit, "LQ size: %d, #loads occupied: %d\n", LQEntries, loads);
425 return LQEntries - loads - 1;
426}
427
428template <class Impl>
429unsigned
430LSQUnit<Impl>::numFreeStoreEntries()
431{
432 //SQ has an extra dummy entry to differentiate
433 //empty/full conditions. Subtract 1 from the free entries.
434 DPRINTF(LSQUnit, "SQ size: %d, #stores occupied: %d\n", SQEntries, stores);
435 return SQEntries - stores - 1;
436
437 }
438
439template <class Impl>
440void
441LSQUnit<Impl>::checkSnoop(PacketPtr pkt)
442{
443 int load_idx = loadHead;
444 DPRINTF(LSQUnit, "Got snoop for address %#x\n", pkt->getAddr());
445
446 // Unlock the cpu-local monitor when the CPU sees a snoop to a locked
447 // address. The CPU can speculatively execute a LL operation after a pending
448 // SC operation in the pipeline and that can make the cache monitor the CPU
449 // is connected to valid while it really shouldn't be.
450 for (int x = 0; x < cpu->numContexts(); x++) {
451 ThreadContext *tc = cpu->getContext(x);
452 bool no_squash = cpu->thread[x]->noSquashFromTC;
453 cpu->thread[x]->noSquashFromTC = true;
454 TheISA::handleLockedSnoop(tc, pkt, cacheBlockMask);
455 cpu->thread[x]->noSquashFromTC = no_squash;
456 }
457
458 Addr invalidate_addr = pkt->getAddr() & cacheBlockMask;
459
460 DynInstPtr ld_inst = loadQueue[load_idx];
461 if (ld_inst) {
462 Addr load_addr = ld_inst->physEffAddr & cacheBlockMask;
463 // Check that this snoop didn't just invalidate our lock flag
464 if (ld_inst->effAddrValid() && load_addr == invalidate_addr &&
465 ld_inst->memReqFlags & Request::LLSC)
466 TheISA::handleLockedSnoopHit(ld_inst.get());
467 }
468
469 // If this is the only load in the LSQ we don't care
470 if (load_idx == loadTail)
471 return;
472
473 incrLdIdx(load_idx);
474
475 bool force_squash = false;
476
477 while (load_idx != loadTail) {
478 DynInstPtr ld_inst = loadQueue[load_idx];
479
480 if (!ld_inst->effAddrValid() || ld_inst->uncacheable()) {
481 incrLdIdx(load_idx);
482 continue;
483 }
484
485 Addr load_addr = ld_inst->physEffAddr & cacheBlockMask;
486 DPRINTF(LSQUnit, "-- inst [sn:%lli] load_addr: %#x to pktAddr:%#x\n",
487 ld_inst->seqNum, load_addr, invalidate_addr);
488
489 if (load_addr == invalidate_addr || force_squash) {
490 if (needsTSO) {
491 // If we have a TSO system, as all loads must be ordered with
492 // all other loads, this load as well as *all* subsequent loads
493 // need to be squashed to prevent possible load reordering.
494 force_squash = true;
495 }
496 if (ld_inst->possibleLoadViolation() || force_squash) {
497 DPRINTF(LSQUnit, "Conflicting load at addr %#x [sn:%lli]\n",
498 pkt->getAddr(), ld_inst->seqNum);
499
500 // Mark the load for re-execution
501 ld_inst->fault = new ReExec;
502 } else {
503 DPRINTF(LSQUnit, "HitExternal Snoop for addr %#x [sn:%lli]\n",
504 pkt->getAddr(), ld_inst->seqNum);
505
506 // Make sure that we don't lose a snoop hitting a LOCKED
507 // address since the LOCK* flags don't get updated until
508 // commit.
509 if (ld_inst->memReqFlags & Request::LLSC)
510 TheISA::handleLockedSnoopHit(ld_inst.get());
511
512 // If a older load checks this and it's true
513 // then we might have missed the snoop
514 // in which case we need to invalidate to be sure
515 ld_inst->hitExternalSnoop(true);
516 }
517 }
518 incrLdIdx(load_idx);
519 }
520 return;
521}
522
523template <class Impl>
524Fault
525LSQUnit<Impl>::checkViolations(int load_idx, DynInstPtr &inst)
526{
527 Addr inst_eff_addr1 = inst->effAddr >> depCheckShift;
528 Addr inst_eff_addr2 = (inst->effAddr + inst->effSize - 1) >> depCheckShift;
529
530 /** @todo in theory you only need to check an instruction that has executed
531 * however, there isn't a good way in the pipeline at the moment to check
532 * all instructions that will execute before the store writes back. Thus,
533 * like the implementation that came before it, we're overly conservative.
534 */
535 while (load_idx != loadTail) {
536 DynInstPtr ld_inst = loadQueue[load_idx];
537 if (!ld_inst->effAddrValid() || ld_inst->uncacheable()) {
538 incrLdIdx(load_idx);
539 continue;
540 }
541
542 Addr ld_eff_addr1 = ld_inst->effAddr >> depCheckShift;
543 Addr ld_eff_addr2 =
544 (ld_inst->effAddr + ld_inst->effSize - 1) >> depCheckShift;
545
546 if (inst_eff_addr2 >= ld_eff_addr1 && inst_eff_addr1 <= ld_eff_addr2) {
547 if (inst->isLoad()) {
548 // If this load is to the same block as an external snoop
549 // invalidate that we've observed then the load needs to be
550 // squashed as it could have newer data
551 if (ld_inst->hitExternalSnoop()) {
552 if (!memDepViolator ||
553 ld_inst->seqNum < memDepViolator->seqNum) {
554 DPRINTF(LSQUnit, "Detected fault with inst [sn:%lli] "
555 "and [sn:%lli] at address %#x\n",
556 inst->seqNum, ld_inst->seqNum, ld_eff_addr1);
557 memDepViolator = ld_inst;
558
559 ++lsqMemOrderViolation;
560
561 return new GenericISA::M5PanicFault(
562 "Detected fault with inst [sn:%lli] and "
563 "[sn:%lli] at address %#x\n",
564 inst->seqNum, ld_inst->seqNum, ld_eff_addr1);
565 }
566 }
567
568 // Otherwise, mark the load has a possible load violation
569 // and if we see a snoop before it's commited, we need to squash
570 ld_inst->possibleLoadViolation(true);
571 DPRINTF(LSQUnit, "Found possible load violaiton at addr: %#x"
572 " between instructions [sn:%lli] and [sn:%lli]\n",
573 inst_eff_addr1, inst->seqNum, ld_inst->seqNum);
574 } else {
575 // A load/store incorrectly passed this store.
576 // Check if we already have a violator, or if it's newer
577 // squash and refetch.
578 if (memDepViolator && ld_inst->seqNum > memDepViolator->seqNum)
579 break;
580
581 DPRINTF(LSQUnit, "Detected fault with inst [sn:%lli] and "
582 "[sn:%lli] at address %#x\n",
583 inst->seqNum, ld_inst->seqNum, ld_eff_addr1);
584 memDepViolator = ld_inst;
585
586 ++lsqMemOrderViolation;
587
588 return new GenericISA::M5PanicFault("Detected fault with "
589 "inst [sn:%lli] and [sn:%lli] at address %#x\n",
590 inst->seqNum, ld_inst->seqNum, ld_eff_addr1);
591 }
592 }
593
594 incrLdIdx(load_idx);
595 }
596 return NoFault;
597}
598
599
600
601
602template <class Impl>
603Fault
604LSQUnit<Impl>::executeLoad(DynInstPtr &inst)
605{
606 using namespace TheISA;
607 // Execute a specific load.
608 Fault load_fault = NoFault;
609
610 DPRINTF(LSQUnit, "Executing load PC %s, [sn:%lli]\n",
611 inst->pcState(), inst->seqNum);
612
613 assert(!inst->isSquashed());
614
615 load_fault = inst->initiateAcc();
616
617 if (inst->isTranslationDelayed() &&
618 load_fault == NoFault)
619 return load_fault;
620
621 // If the instruction faulted or predicated false, then we need to send it
622 // along to commit without the instruction completing.
623 if (load_fault != NoFault || !inst->readPredicate()) {
624 // Send this instruction to commit, also make sure iew stage
625 // realizes there is activity.
626 // Mark it as executed unless it is an uncached load that
627 // needs to hit the head of commit.
628 if (!inst->readPredicate())
629 inst->forwardOldRegs();
630 DPRINTF(LSQUnit, "Load [sn:%lli] not executed from %s\n",
631 inst->seqNum,
632 (load_fault != NoFault ? "fault" : "predication"));
633 if (!(inst->hasRequest() && inst->uncacheable()) ||
634 inst->isAtCommit()) {
635 inst->setExecuted();
636 }
637 iewStage->instToCommit(inst);
638 iewStage->activityThisCycle();
|
635 } else if (!loadBlocked()) {
| 639 } else {
|
636 assert(inst->effAddrValid());
637 int load_idx = inst->lqIdx;
638 incrLdIdx(load_idx);
639
640 if (checkLoads)
641 return checkViolations(load_idx, inst);
642 }
643
644 return load_fault;
645}
646
647template <class Impl>
648Fault
649LSQUnit<Impl>::executeStore(DynInstPtr &store_inst)
650{
651 using namespace TheISA;
652 // Make sure that a store exists.
653 assert(stores != 0);
654
655 int store_idx = store_inst->sqIdx;
656
657 DPRINTF(LSQUnit, "Executing store PC %s [sn:%lli]\n",
658 store_inst->pcState(), store_inst->seqNum);
659
660 assert(!store_inst->isSquashed());
661
662 // Check the recently completed loads to see if any match this store's
663 // address. If so, then we have a memory ordering violation.
664 int load_idx = store_inst->lqIdx;
665
666 Fault store_fault = store_inst->initiateAcc();
667
668 if (store_inst->isTranslationDelayed() &&
669 store_fault == NoFault)
670 return store_fault;
671
672 if (!store_inst->readPredicate())
673 store_inst->forwardOldRegs();
674
675 if (storeQueue[store_idx].size == 0) {
676 DPRINTF(LSQUnit,"Fault on Store PC %s, [sn:%lli], Size = 0\n",
677 store_inst->pcState(), store_inst->seqNum);
678
679 return store_fault;
680 } else if (!store_inst->readPredicate()) {
681 DPRINTF(LSQUnit, "Store [sn:%lli] not executed from predication\n",
682 store_inst->seqNum);
683 return store_fault;
684 }
685
686 assert(store_fault == NoFault);
687
688 if (store_inst->isStoreConditional()) {
689 // Store conditionals need to set themselves as able to
690 // writeback if we haven't had a fault by here.
691 storeQueue[store_idx].canWB = true;
692
693 ++storesToWB;
694 }
695
696 return checkViolations(load_idx, store_inst);
697
698}
699
700template <class Impl>
701void
702LSQUnit<Impl>::commitLoad()
703{
704 assert(loadQueue[loadHead]);
705
706 DPRINTF(LSQUnit, "Committing head load instruction, PC %s\n",
707 loadQueue[loadHead]->pcState());
708
709 loadQueue[loadHead] = NULL;
710
711 incrLdIdx(loadHead);
712
713 --loads;
714}
715
716template <class Impl>
717void
718LSQUnit<Impl>::commitLoads(InstSeqNum &youngest_inst)
719{
720 assert(loads == 0 || loadQueue[loadHead]);
721
722 while (loads != 0 && loadQueue[loadHead]->seqNum <= youngest_inst) {
723 commitLoad();
724 }
725}
726
727template <class Impl>
728void
729LSQUnit<Impl>::commitStores(InstSeqNum &youngest_inst)
730{
731 assert(stores == 0 || storeQueue[storeHead].inst);
732
733 int store_idx = storeHead;
734
735 while (store_idx != storeTail) {
736 assert(storeQueue[store_idx].inst);
737 // Mark any stores that are now committed and have not yet
738 // been marked as able to write back.
739 if (!storeQueue[store_idx].canWB) {
740 if (storeQueue[store_idx].inst->seqNum > youngest_inst) {
741 break;
742 }
743 DPRINTF(LSQUnit, "Marking store as able to write back, PC "
744 "%s [sn:%lli]\n",
745 storeQueue[store_idx].inst->pcState(),
746 storeQueue[store_idx].inst->seqNum);
747
748 storeQueue[store_idx].canWB = true;
749
750 ++storesToWB;
751 }
752
753 incrStIdx(store_idx);
754 }
755}
756
757template <class Impl>
758void
759LSQUnit<Impl>::writebackPendingStore()
760{
761 if (hasPendingPkt) {
762 assert(pendingPkt != NULL);
763
764 // If the cache is blocked, this will store the packet for retry.
765 if (sendStore(pendingPkt)) {
766 storePostSend(pendingPkt);
767 }
768 pendingPkt = NULL;
769 hasPendingPkt = false;
770 }
771}
772
773template <class Impl>
774void
775LSQUnit<Impl>::writebackStores()
776{
777 // First writeback the second packet from any split store that didn't
778 // complete last cycle because there weren't enough cache ports available.
779 if (TheISA::HasUnalignedMemAcc) {
780 writebackPendingStore();
781 }
782
783 while (storesToWB > 0 &&
784 storeWBIdx != storeTail &&
785 storeQueue[storeWBIdx].inst &&
786 storeQueue[storeWBIdx].canWB &&
787 ((!needsTSO) || (!storeInFlight)) &&
788 usedPorts < cachePorts) {
789
| 640 assert(inst->effAddrValid());
641 int load_idx = inst->lqIdx;
642 incrLdIdx(load_idx);
643
644 if (checkLoads)
645 return checkViolations(load_idx, inst);
646 }
647
648 return load_fault;
649}
650
651template <class Impl>
652Fault
653LSQUnit<Impl>::executeStore(DynInstPtr &store_inst)
654{
655 using namespace TheISA;
656 // Make sure that a store exists.
657 assert(stores != 0);
658
659 int store_idx = store_inst->sqIdx;
660
661 DPRINTF(LSQUnit, "Executing store PC %s [sn:%lli]\n",
662 store_inst->pcState(), store_inst->seqNum);
663
664 assert(!store_inst->isSquashed());
665
666 // Check the recently completed loads to see if any match this store's
667 // address. If so, then we have a memory ordering violation.
668 int load_idx = store_inst->lqIdx;
669
670 Fault store_fault = store_inst->initiateAcc();
671
672 if (store_inst->isTranslationDelayed() &&
673 store_fault == NoFault)
674 return store_fault;
675
676 if (!store_inst->readPredicate())
677 store_inst->forwardOldRegs();
678
679 if (storeQueue[store_idx].size == 0) {
680 DPRINTF(LSQUnit,"Fault on Store PC %s, [sn:%lli], Size = 0\n",
681 store_inst->pcState(), store_inst->seqNum);
682
683 return store_fault;
684 } else if (!store_inst->readPredicate()) {
685 DPRINTF(LSQUnit, "Store [sn:%lli] not executed from predication\n",
686 store_inst->seqNum);
687 return store_fault;
688 }
689
690 assert(store_fault == NoFault);
691
692 if (store_inst->isStoreConditional()) {
693 // Store conditionals need to set themselves as able to
694 // writeback if we haven't had a fault by here.
695 storeQueue[store_idx].canWB = true;
696
697 ++storesToWB;
698 }
699
700 return checkViolations(load_idx, store_inst);
701
702}
703
704template <class Impl>
705void
706LSQUnit<Impl>::commitLoad()
707{
708 assert(loadQueue[loadHead]);
709
710 DPRINTF(LSQUnit, "Committing head load instruction, PC %s\n",
711 loadQueue[loadHead]->pcState());
712
713 loadQueue[loadHead] = NULL;
714
715 incrLdIdx(loadHead);
716
717 --loads;
718}
719
720template <class Impl>
721void
722LSQUnit<Impl>::commitLoads(InstSeqNum &youngest_inst)
723{
724 assert(loads == 0 || loadQueue[loadHead]);
725
726 while (loads != 0 && loadQueue[loadHead]->seqNum <= youngest_inst) {
727 commitLoad();
728 }
729}
730
731template <class Impl>
732void
733LSQUnit<Impl>::commitStores(InstSeqNum &youngest_inst)
734{
735 assert(stores == 0 || storeQueue[storeHead].inst);
736
737 int store_idx = storeHead;
738
739 while (store_idx != storeTail) {
740 assert(storeQueue[store_idx].inst);
741 // Mark any stores that are now committed and have not yet
742 // been marked as able to write back.
743 if (!storeQueue[store_idx].canWB) {
744 if (storeQueue[store_idx].inst->seqNum > youngest_inst) {
745 break;
746 }
747 DPRINTF(LSQUnit, "Marking store as able to write back, PC "
748 "%s [sn:%lli]\n",
749 storeQueue[store_idx].inst->pcState(),
750 storeQueue[store_idx].inst->seqNum);
751
752 storeQueue[store_idx].canWB = true;
753
754 ++storesToWB;
755 }
756
757 incrStIdx(store_idx);
758 }
759}
760
761template <class Impl>
762void
763LSQUnit<Impl>::writebackPendingStore()
764{
765 if (hasPendingPkt) {
766 assert(pendingPkt != NULL);
767
768 // If the cache is blocked, this will store the packet for retry.
769 if (sendStore(pendingPkt)) {
770 storePostSend(pendingPkt);
771 }
772 pendingPkt = NULL;
773 hasPendingPkt = false;
774 }
775}
776
777template <class Impl>
778void
779LSQUnit<Impl>::writebackStores()
780{
781 // First writeback the second packet from any split store that didn't
782 // complete last cycle because there weren't enough cache ports available.
783 if (TheISA::HasUnalignedMemAcc) {
784 writebackPendingStore();
785 }
786
787 while (storesToWB > 0 &&
788 storeWBIdx != storeTail &&
789 storeQueue[storeWBIdx].inst &&
790 storeQueue[storeWBIdx].canWB &&
791 ((!needsTSO) || (!storeInFlight)) &&
792 usedPorts < cachePorts) {
793
|
790 if (isStoreBlocked || lsq->cacheBlocked()) {
| 794 if (isStoreBlocked) {
|
791 DPRINTF(LSQUnit, "Unable to write back any more stores, cache"
792 " is blocked!\n");
793 break;
794 }
795
796 // Store didn't write any data so no need to write it back to
797 // memory.
798 if (storeQueue[storeWBIdx].size == 0) {
799 completeStore(storeWBIdx);
800
801 incrStIdx(storeWBIdx);
802
803 continue;
804 }
805
806 ++usedPorts;
807
808 if (storeQueue[storeWBIdx].inst->isDataPrefetch()) {
809 incrStIdx(storeWBIdx);
810
811 continue;
812 }
813
814 assert(storeQueue[storeWBIdx].req);
815 assert(!storeQueue[storeWBIdx].committed);
816
817 if (TheISA::HasUnalignedMemAcc && storeQueue[storeWBIdx].isSplit) {
818 assert(storeQueue[storeWBIdx].sreqLow);
819 assert(storeQueue[storeWBIdx].sreqHigh);
820 }
821
822 DynInstPtr inst = storeQueue[storeWBIdx].inst;
823
824 Request *req = storeQueue[storeWBIdx].req;
825 RequestPtr sreqLow = storeQueue[storeWBIdx].sreqLow;
826 RequestPtr sreqHigh = storeQueue[storeWBIdx].sreqHigh;
827
828 storeQueue[storeWBIdx].committed = true;
829
830 assert(!inst->memData);
831 inst->memData = new uint8_t[req->getSize()];
832
833 if (storeQueue[storeWBIdx].isAllZeros)
834 memset(inst->memData, 0, req->getSize());
835 else
836 memcpy(inst->memData, storeQueue[storeWBIdx].data, req->getSize());
837
838 MemCmd command =
839 req->isSwap() ? MemCmd::SwapReq :
840 (req->isLLSC() ? MemCmd::StoreCondReq : MemCmd::WriteReq);
841 PacketPtr data_pkt;
842 PacketPtr snd_data_pkt = NULL;
843
844 LSQSenderState *state = new LSQSenderState;
845 state->isLoad = false;
846 state->idx = storeWBIdx;
847 state->inst = inst;
848
849 if (!TheISA::HasUnalignedMemAcc || !storeQueue[storeWBIdx].isSplit) {
850
851 // Build a single data packet if the store isn't split.
852 data_pkt = new Packet(req, command);
853 data_pkt->dataStatic(inst->memData);
854 data_pkt->senderState = state;
855 } else {
856 // Create two packets if the store is split in two.
857 data_pkt = new Packet(sreqLow, command);
858 snd_data_pkt = new Packet(sreqHigh, command);
859
860 data_pkt->dataStatic(inst->memData);
861 snd_data_pkt->dataStatic(inst->memData + sreqLow->getSize());
862
863 data_pkt->senderState = state;
864 snd_data_pkt->senderState = state;
865
866 state->isSplit = true;
867 state->outstanding = 2;
868
869 // Can delete the main request now.
870 delete req;
871 req = sreqLow;
872 }
873
874 DPRINTF(LSQUnit, "D-Cache: Writing back store idx:%i PC:%s "
875 "to Addr:%#x, data:%#x [sn:%lli]\n",
876 storeWBIdx, inst->pcState(),
877 req->getPaddr(), (int)*(inst->memData),
878 inst->seqNum);
879
880 // @todo: Remove this SC hack once the memory system handles it.
881 if (inst->isStoreConditional()) {
882 assert(!storeQueue[storeWBIdx].isSplit);
883 // Disable recording the result temporarily. Writing to
884 // misc regs normally updates the result, but this is not
885 // the desired behavior when handling store conditionals.
886 inst->recordResult(false);
887 bool success = TheISA::handleLockedWrite(inst.get(), req, cacheBlockMask);
888 inst->recordResult(true);
889
890 if (!success) {
891 // Instantly complete this store.
892 DPRINTF(LSQUnit, "Store conditional [sn:%lli] failed. "
893 "Instantly completing it.\n",
894 inst->seqNum);
895 WritebackEvent *wb = new WritebackEvent(inst, data_pkt, this);
896 cpu->schedule(wb, curTick() + 1);
897 if (cpu->checker) {
898 // Make sure to set the LLSC data for verification
899 // if checker is loaded
900 inst->reqToVerify->setExtraData(0);
901 inst->completeAcc(data_pkt);
902 }
903 completeStore(storeWBIdx);
904 incrStIdx(storeWBIdx);
905 continue;
906 }
907 } else {
908 // Non-store conditionals do not need a writeback.
909 state->noWB = true;
910 }
911
912 bool split =
913 TheISA::HasUnalignedMemAcc && storeQueue[storeWBIdx].isSplit;
914
915 ThreadContext *thread = cpu->tcBase(lsqID);
916
917 if (req->isMmappedIpr()) {
918 assert(!inst->isStoreConditional());
919 TheISA::handleIprWrite(thread, data_pkt);
920 delete data_pkt;
921 if (split) {
922 assert(snd_data_pkt->req->isMmappedIpr());
923 TheISA::handleIprWrite(thread, snd_data_pkt);
924 delete snd_data_pkt;
925 delete sreqLow;
926 delete sreqHigh;
927 }
928 delete state;
929 delete req;
930 completeStore(storeWBIdx);
931 incrStIdx(storeWBIdx);
932 } else if (!sendStore(data_pkt)) {
933 DPRINTF(IEW, "D-Cache became blocked when writing [sn:%lli], will"
934 "retry later\n",
935 inst->seqNum);
936
937 // Need to store the second packet, if split.
938 if (split) {
939 state->pktToSend = true;
940 state->pendingPacket = snd_data_pkt;
941 }
942 } else {
943
944 // If split, try to send the second packet too
945 if (split) {
946 assert(snd_data_pkt);
947
948 // Ensure there are enough ports to use.
949 if (usedPorts < cachePorts) {
950 ++usedPorts;
951 if (sendStore(snd_data_pkt)) {
952 storePostSend(snd_data_pkt);
953 } else {
954 DPRINTF(IEW, "D-Cache became blocked when writing"
955 " [sn:%lli] second packet, will retry later\n",
956 inst->seqNum);
957 }
958 } else {
959
960 // Store the packet for when there's free ports.
961 assert(pendingPkt == NULL);
962 pendingPkt = snd_data_pkt;
963 hasPendingPkt = true;
964 }
965 } else {
966
967 // Not a split store.
968 storePostSend(data_pkt);
969 }
970 }
971 }
972
973 // Not sure this should set it to 0.
974 usedPorts = 0;
975
976 assert(stores >= 0 && storesToWB >= 0);
977}
978
979/*template <class Impl>
980void
981LSQUnit<Impl>::removeMSHR(InstSeqNum seqNum)
982{
983 list<InstSeqNum>::iterator mshr_it = find(mshrSeqNums.begin(),
984 mshrSeqNums.end(),
985 seqNum);
986
987 if (mshr_it != mshrSeqNums.end()) {
988 mshrSeqNums.erase(mshr_it);
989 DPRINTF(LSQUnit, "Removing MSHR. count = %i\n",mshrSeqNums.size());
990 }
991}*/
992
993template <class Impl>
994void
995LSQUnit<Impl>::squash(const InstSeqNum &squashed_num)
996{
997 DPRINTF(LSQUnit, "Squashing until [sn:%lli]!"
998 "(Loads:%i Stores:%i)\n", squashed_num, loads, stores);
999
1000 int load_idx = loadTail;
1001 decrLdIdx(load_idx);
1002
1003 while (loads != 0 && loadQueue[load_idx]->seqNum > squashed_num) {
1004 DPRINTF(LSQUnit,"Load Instruction PC %s squashed, "
1005 "[sn:%lli]\n",
1006 loadQueue[load_idx]->pcState(),
1007 loadQueue[load_idx]->seqNum);
1008
1009 if (isStalled() && load_idx == stallingLoadIdx) {
1010 stalled = false;
1011 stallingStoreIsn = 0;
1012 stallingLoadIdx = 0;
1013 }
1014
1015 // Clear the smart pointer to make sure it is decremented.
1016 loadQueue[load_idx]->setSquashed();
1017 loadQueue[load_idx] = NULL;
1018 --loads;
1019
1020 // Inefficient!
1021 loadTail = load_idx;
1022
1023 decrLdIdx(load_idx);
1024 ++lsqSquashedLoads;
1025 }
1026
| 795 DPRINTF(LSQUnit, "Unable to write back any more stores, cache"
796 " is blocked!\n");
797 break;
798 }
799
800 // Store didn't write any data so no need to write it back to
801 // memory.
802 if (storeQueue[storeWBIdx].size == 0) {
803 completeStore(storeWBIdx);
804
805 incrStIdx(storeWBIdx);
806
807 continue;
808 }
809
810 ++usedPorts;
811
812 if (storeQueue[storeWBIdx].inst->isDataPrefetch()) {
813 incrStIdx(storeWBIdx);
814
815 continue;
816 }
817
818 assert(storeQueue[storeWBIdx].req);
819 assert(!storeQueue[storeWBIdx].committed);
820
821 if (TheISA::HasUnalignedMemAcc && storeQueue[storeWBIdx].isSplit) {
822 assert(storeQueue[storeWBIdx].sreqLow);
823 assert(storeQueue[storeWBIdx].sreqHigh);
824 }
825
826 DynInstPtr inst = storeQueue[storeWBIdx].inst;
827
828 Request *req = storeQueue[storeWBIdx].req;
829 RequestPtr sreqLow = storeQueue[storeWBIdx].sreqLow;
830 RequestPtr sreqHigh = storeQueue[storeWBIdx].sreqHigh;
831
832 storeQueue[storeWBIdx].committed = true;
833
834 assert(!inst->memData);
835 inst->memData = new uint8_t[req->getSize()];
836
837 if (storeQueue[storeWBIdx].isAllZeros)
838 memset(inst->memData, 0, req->getSize());
839 else
840 memcpy(inst->memData, storeQueue[storeWBIdx].data, req->getSize());
841
842 MemCmd command =
843 req->isSwap() ? MemCmd::SwapReq :
844 (req->isLLSC() ? MemCmd::StoreCondReq : MemCmd::WriteReq);
845 PacketPtr data_pkt;
846 PacketPtr snd_data_pkt = NULL;
847
848 LSQSenderState *state = new LSQSenderState;
849 state->isLoad = false;
850 state->idx = storeWBIdx;
851 state->inst = inst;
852
853 if (!TheISA::HasUnalignedMemAcc || !storeQueue[storeWBIdx].isSplit) {
854
855 // Build a single data packet if the store isn't split.
856 data_pkt = new Packet(req, command);
857 data_pkt->dataStatic(inst->memData);
858 data_pkt->senderState = state;
859 } else {
860 // Create two packets if the store is split in two.
861 data_pkt = new Packet(sreqLow, command);
862 snd_data_pkt = new Packet(sreqHigh, command);
863
864 data_pkt->dataStatic(inst->memData);
865 snd_data_pkt->dataStatic(inst->memData + sreqLow->getSize());
866
867 data_pkt->senderState = state;
868 snd_data_pkt->senderState = state;
869
870 state->isSplit = true;
871 state->outstanding = 2;
872
873 // Can delete the main request now.
874 delete req;
875 req = sreqLow;
876 }
877
878 DPRINTF(LSQUnit, "D-Cache: Writing back store idx:%i PC:%s "
879 "to Addr:%#x, data:%#x [sn:%lli]\n",
880 storeWBIdx, inst->pcState(),
881 req->getPaddr(), (int)*(inst->memData),
882 inst->seqNum);
883
884 // @todo: Remove this SC hack once the memory system handles it.
885 if (inst->isStoreConditional()) {
886 assert(!storeQueue[storeWBIdx].isSplit);
887 // Disable recording the result temporarily. Writing to
888 // misc regs normally updates the result, but this is not
889 // the desired behavior when handling store conditionals.
890 inst->recordResult(false);
891 bool success = TheISA::handleLockedWrite(inst.get(), req, cacheBlockMask);
892 inst->recordResult(true);
893
894 if (!success) {
895 // Instantly complete this store.
896 DPRINTF(LSQUnit, "Store conditional [sn:%lli] failed. "
897 "Instantly completing it.\n",
898 inst->seqNum);
899 WritebackEvent *wb = new WritebackEvent(inst, data_pkt, this);
900 cpu->schedule(wb, curTick() + 1);
901 if (cpu->checker) {
902 // Make sure to set the LLSC data for verification
903 // if checker is loaded
904 inst->reqToVerify->setExtraData(0);
905 inst->completeAcc(data_pkt);
906 }
907 completeStore(storeWBIdx);
908 incrStIdx(storeWBIdx);
909 continue;
910 }
911 } else {
912 // Non-store conditionals do not need a writeback.
913 state->noWB = true;
914 }
915
916 bool split =
917 TheISA::HasUnalignedMemAcc && storeQueue[storeWBIdx].isSplit;
918
919 ThreadContext *thread = cpu->tcBase(lsqID);
920
921 if (req->isMmappedIpr()) {
922 assert(!inst->isStoreConditional());
923 TheISA::handleIprWrite(thread, data_pkt);
924 delete data_pkt;
925 if (split) {
926 assert(snd_data_pkt->req->isMmappedIpr());
927 TheISA::handleIprWrite(thread, snd_data_pkt);
928 delete snd_data_pkt;
929 delete sreqLow;
930 delete sreqHigh;
931 }
932 delete state;
933 delete req;
934 completeStore(storeWBIdx);
935 incrStIdx(storeWBIdx);
936 } else if (!sendStore(data_pkt)) {
937 DPRINTF(IEW, "D-Cache became blocked when writing [sn:%lli], will"
938 "retry later\n",
939 inst->seqNum);
940
941 // Need to store the second packet, if split.
942 if (split) {
943 state->pktToSend = true;
944 state->pendingPacket = snd_data_pkt;
945 }
946 } else {
947
948 // If split, try to send the second packet too
949 if (split) {
950 assert(snd_data_pkt);
951
952 // Ensure there are enough ports to use.
953 if (usedPorts < cachePorts) {
954 ++usedPorts;
955 if (sendStore(snd_data_pkt)) {
956 storePostSend(snd_data_pkt);
957 } else {
958 DPRINTF(IEW, "D-Cache became blocked when writing"
959 " [sn:%lli] second packet, will retry later\n",
960 inst->seqNum);
961 }
962 } else {
963
964 // Store the packet for when there's free ports.
965 assert(pendingPkt == NULL);
966 pendingPkt = snd_data_pkt;
967 hasPendingPkt = true;
968 }
969 } else {
970
971 // Not a split store.
972 storePostSend(data_pkt);
973 }
974 }
975 }
976
977 // Not sure this should set it to 0.
978 usedPorts = 0;
979
980 assert(stores >= 0 && storesToWB >= 0);
981}
982
983/*template <class Impl>
984void
985LSQUnit<Impl>::removeMSHR(InstSeqNum seqNum)
986{
987 list<InstSeqNum>::iterator mshr_it = find(mshrSeqNums.begin(),
988 mshrSeqNums.end(),
989 seqNum);
990
991 if (mshr_it != mshrSeqNums.end()) {
992 mshrSeqNums.erase(mshr_it);
993 DPRINTF(LSQUnit, "Removing MSHR. count = %i\n",mshrSeqNums.size());
994 }
995}*/
996
997template <class Impl>
998void
999LSQUnit<Impl>::squash(const InstSeqNum &squashed_num)
1000{
1001 DPRINTF(LSQUnit, "Squashing until [sn:%lli]!"
1002 "(Loads:%i Stores:%i)\n", squashed_num, loads, stores);
1003
1004 int load_idx = loadTail;
1005 decrLdIdx(load_idx);
1006
1007 while (loads != 0 && loadQueue[load_idx]->seqNum > squashed_num) {
1008 DPRINTF(LSQUnit,"Load Instruction PC %s squashed, "
1009 "[sn:%lli]\n",
1010 loadQueue[load_idx]->pcState(),
1011 loadQueue[load_idx]->seqNum);
1012
1013 if (isStalled() && load_idx == stallingLoadIdx) {
1014 stalled = false;
1015 stallingStoreIsn = 0;
1016 stallingLoadIdx = 0;
1017 }
1018
1019 // Clear the smart pointer to make sure it is decremented.
1020 loadQueue[load_idx]->setSquashed();
1021 loadQueue[load_idx] = NULL;
1022 --loads;
1023
1024 // Inefficient!
1025 loadTail = load_idx;
1026
1027 decrLdIdx(load_idx);
1028 ++lsqSquashedLoads;
1029 }
1030
|
1027 if (isLoadBlocked) {
1028 if (squashed_num < blockedLoadSeqNum) {
1029 isLoadBlocked = false;
1030 loadBlockedHandled = false;
1031 blockedLoadSeqNum = 0;
1032 }
1033 }
1034
| |
1035 if (memDepViolator && squashed_num < memDepViolator->seqNum) {
1036 memDepViolator = NULL;
1037 }
1038
1039 int store_idx = storeTail;
1040 decrStIdx(store_idx);
1041
1042 while (stores != 0 &&
1043 storeQueue[store_idx].inst->seqNum > squashed_num) {
1044 // Instructions marked as can WB are already committed.
1045 if (storeQueue[store_idx].canWB) {
1046 break;
1047 }
1048
1049 DPRINTF(LSQUnit,"Store Instruction PC %s squashed, "
1050 "idx:%i [sn:%lli]\n",
1051 storeQueue[store_idx].inst->pcState(),
1052 store_idx, storeQueue[store_idx].inst->seqNum);
1053
1054 // I don't think this can happen. It should have been cleared
1055 // by the stalling load.
1056 if (isStalled() &&
1057 storeQueue[store_idx].inst->seqNum == stallingStoreIsn) {
1058 panic("Is stalled should have been cleared by stalling load!\n");
1059 stalled = false;
1060 stallingStoreIsn = 0;
1061 }
1062
1063 // Clear the smart pointer to make sure it is decremented.
1064 storeQueue[store_idx].inst->setSquashed();
1065 storeQueue[store_idx].inst = NULL;
1066 storeQueue[store_idx].canWB = 0;
1067
1068 // Must delete request now that it wasn't handed off to
1069 // memory. This is quite ugly. @todo: Figure out the proper
1070 // place to really handle request deletes.
1071 delete storeQueue[store_idx].req;
1072 if (TheISA::HasUnalignedMemAcc && storeQueue[store_idx].isSplit) {
1073 delete storeQueue[store_idx].sreqLow;
1074 delete storeQueue[store_idx].sreqHigh;
1075
1076 storeQueue[store_idx].sreqLow = NULL;
1077 storeQueue[store_idx].sreqHigh = NULL;
1078 }
1079
1080 storeQueue[store_idx].req = NULL;
1081 --stores;
1082
1083 // Inefficient!
1084 storeTail = store_idx;
1085
1086 decrStIdx(store_idx);
1087 ++lsqSquashedStores;
1088 }
1089}
1090
1091template <class Impl>
1092void
1093LSQUnit<Impl>::storePostSend(PacketPtr pkt)
1094{
1095 if (isStalled() &&
1096 storeQueue[storeWBIdx].inst->seqNum == stallingStoreIsn) {
1097 DPRINTF(LSQUnit, "Unstalling, stalling store [sn:%lli] "
1098 "load idx:%i\n",
1099 stallingStoreIsn, stallingLoadIdx);
1100 stalled = false;
1101 stallingStoreIsn = 0;
1102 iewStage->replayMemInst(loadQueue[stallingLoadIdx]);
1103 }
1104
1105 if (!storeQueue[storeWBIdx].inst->isStoreConditional()) {
1106 // The store is basically completed at this time. This
1107 // only works so long as the checker doesn't try to
1108 // verify the value in memory for stores.
1109 storeQueue[storeWBIdx].inst->setCompleted();
1110
1111 if (cpu->checker) {
1112 cpu->checker->verify(storeQueue[storeWBIdx].inst);
1113 }
1114 }
1115
1116 if (needsTSO) {
1117 storeInFlight = true;
1118 }
1119
1120 incrStIdx(storeWBIdx);
1121}
1122
1123template <class Impl>
1124void
1125LSQUnit<Impl>::writeback(DynInstPtr &inst, PacketPtr pkt)
1126{
1127 iewStage->wakeCPU();
1128
1129 // Squashed instructions do not need to complete their access.
1130 if (inst->isSquashed()) {
1131 assert(!inst->isStore());
1132 ++lsqIgnoredResponses;
1133 return;
1134 }
1135
1136 if (!inst->isExecuted()) {
1137 inst->setExecuted();
1138
1139 // Complete access to copy data to proper place.
1140 inst->completeAcc(pkt);
1141 }
1142
1143 // Need to insert instruction into queue to commit
1144 iewStage->instToCommit(inst);
1145
1146 iewStage->activityThisCycle();
1147
1148 // see if this load changed the PC
1149 iewStage->checkMisprediction(inst);
1150}
1151
1152template <class Impl>
1153void
1154LSQUnit<Impl>::completeStore(int store_idx)
1155{
1156 assert(storeQueue[store_idx].inst);
1157 storeQueue[store_idx].completed = true;
1158 --storesToWB;
1159 // A bit conservative because a store completion may not free up entries,
1160 // but hopefully avoids two store completions in one cycle from making
1161 // the CPU tick twice.
1162 cpu->wakeCPU();
1163 cpu->activityThisCycle();
1164
1165 if (store_idx == storeHead) {
1166 do {
1167 incrStIdx(storeHead);
1168
1169 --stores;
1170 } while (storeQueue[storeHead].completed &&
1171 storeHead != storeTail);
1172
1173 iewStage->updateLSQNextCycle = true;
1174 }
1175
1176 DPRINTF(LSQUnit, "Completing store [sn:%lli], idx:%i, store head "
1177 "idx:%i\n",
1178 storeQueue[store_idx].inst->seqNum, store_idx, storeHead);
1179
1180#if TRACING_ON
1181 if (DTRACE(O3PipeView)) {
1182 storeQueue[store_idx].inst->storeTick =
1183 curTick() - storeQueue[store_idx].inst->fetchTick;
1184 }
1185#endif
1186
1187 if (isStalled() &&
1188 storeQueue[store_idx].inst->seqNum == stallingStoreIsn) {
1189 DPRINTF(LSQUnit, "Unstalling, stalling store [sn:%lli] "
1190 "load idx:%i\n",
1191 stallingStoreIsn, stallingLoadIdx);
1192 stalled = false;
1193 stallingStoreIsn = 0;
1194 iewStage->replayMemInst(loadQueue[stallingLoadIdx]);
1195 }
1196
1197 storeQueue[store_idx].inst->setCompleted();
1198
1199 if (needsTSO) {
1200 storeInFlight = false;
1201 }
1202
1203 // Tell the checker we've completed this instruction. Some stores
1204 // may get reported twice to the checker, but the checker can
1205 // handle that case.
1206 if (cpu->checker) {
1207 cpu->checker->verify(storeQueue[store_idx].inst);
1208 }
1209}
1210
1211template <class Impl>
1212bool
1213LSQUnit<Impl>::sendStore(PacketPtr data_pkt)
1214{
1215 if (!dcachePort->sendTimingReq(data_pkt)) {
1216 // Need to handle becoming blocked on a store.
1217 isStoreBlocked = true;
1218 ++lsqCacheBlocked;
1219 assert(retryPkt == NULL);
1220 retryPkt = data_pkt;
| 1031 if (memDepViolator && squashed_num < memDepViolator->seqNum) {
1032 memDepViolator = NULL;
1033 }
1034
1035 int store_idx = storeTail;
1036 decrStIdx(store_idx);
1037
1038 while (stores != 0 &&
1039 storeQueue[store_idx].inst->seqNum > squashed_num) {
1040 // Instructions marked as can WB are already committed.
1041 if (storeQueue[store_idx].canWB) {
1042 break;
1043 }
1044
1045 DPRINTF(LSQUnit,"Store Instruction PC %s squashed, "
1046 "idx:%i [sn:%lli]\n",
1047 storeQueue[store_idx].inst->pcState(),
1048 store_idx, storeQueue[store_idx].inst->seqNum);
1049
1050 // I don't think this can happen. It should have been cleared
1051 // by the stalling load.
1052 if (isStalled() &&
1053 storeQueue[store_idx].inst->seqNum == stallingStoreIsn) {
1054 panic("Is stalled should have been cleared by stalling load!\n");
1055 stalled = false;
1056 stallingStoreIsn = 0;
1057 }
1058
1059 // Clear the smart pointer to make sure it is decremented.
1060 storeQueue[store_idx].inst->setSquashed();
1061 storeQueue[store_idx].inst = NULL;
1062 storeQueue[store_idx].canWB = 0;
1063
1064 // Must delete request now that it wasn't handed off to
1065 // memory. This is quite ugly. @todo: Figure out the proper
1066 // place to really handle request deletes.
1067 delete storeQueue[store_idx].req;
1068 if (TheISA::HasUnalignedMemAcc && storeQueue[store_idx].isSplit) {
1069 delete storeQueue[store_idx].sreqLow;
1070 delete storeQueue[store_idx].sreqHigh;
1071
1072 storeQueue[store_idx].sreqLow = NULL;
1073 storeQueue[store_idx].sreqHigh = NULL;
1074 }
1075
1076 storeQueue[store_idx].req = NULL;
1077 --stores;
1078
1079 // Inefficient!
1080 storeTail = store_idx;
1081
1082 decrStIdx(store_idx);
1083 ++lsqSquashedStores;
1084 }
1085}
1086
1087template <class Impl>
1088void
1089LSQUnit<Impl>::storePostSend(PacketPtr pkt)
1090{
1091 if (isStalled() &&
1092 storeQueue[storeWBIdx].inst->seqNum == stallingStoreIsn) {
1093 DPRINTF(LSQUnit, "Unstalling, stalling store [sn:%lli] "
1094 "load idx:%i\n",
1095 stallingStoreIsn, stallingLoadIdx);
1096 stalled = false;
1097 stallingStoreIsn = 0;
1098 iewStage->replayMemInst(loadQueue[stallingLoadIdx]);
1099 }
1100
1101 if (!storeQueue[storeWBIdx].inst->isStoreConditional()) {
1102 // The store is basically completed at this time. This
1103 // only works so long as the checker doesn't try to
1104 // verify the value in memory for stores.
1105 storeQueue[storeWBIdx].inst->setCompleted();
1106
1107 if (cpu->checker) {
1108 cpu->checker->verify(storeQueue[storeWBIdx].inst);
1109 }
1110 }
1111
1112 if (needsTSO) {
1113 storeInFlight = true;
1114 }
1115
1116 incrStIdx(storeWBIdx);
1117}
1118
1119template <class Impl>
1120void
1121LSQUnit<Impl>::writeback(DynInstPtr &inst, PacketPtr pkt)
1122{
1123 iewStage->wakeCPU();
1124
1125 // Squashed instructions do not need to complete their access.
1126 if (inst->isSquashed()) {
1127 assert(!inst->isStore());
1128 ++lsqIgnoredResponses;
1129 return;
1130 }
1131
1132 if (!inst->isExecuted()) {
1133 inst->setExecuted();
1134
1135 // Complete access to copy data to proper place.
1136 inst->completeAcc(pkt);
1137 }
1138
1139 // Need to insert instruction into queue to commit
1140 iewStage->instToCommit(inst);
1141
1142 iewStage->activityThisCycle();
1143
1144 // see if this load changed the PC
1145 iewStage->checkMisprediction(inst);
1146}
1147
1148template <class Impl>
1149void
1150LSQUnit<Impl>::completeStore(int store_idx)
1151{
1152 assert(storeQueue[store_idx].inst);
1153 storeQueue[store_idx].completed = true;
1154 --storesToWB;
1155 // A bit conservative because a store completion may not free up entries,
1156 // but hopefully avoids two store completions in one cycle from making
1157 // the CPU tick twice.
1158 cpu->wakeCPU();
1159 cpu->activityThisCycle();
1160
1161 if (store_idx == storeHead) {
1162 do {
1163 incrStIdx(storeHead);
1164
1165 --stores;
1166 } while (storeQueue[storeHead].completed &&
1167 storeHead != storeTail);
1168
1169 iewStage->updateLSQNextCycle = true;
1170 }
1171
1172 DPRINTF(LSQUnit, "Completing store [sn:%lli], idx:%i, store head "
1173 "idx:%i\n",
1174 storeQueue[store_idx].inst->seqNum, store_idx, storeHead);
1175
1176#if TRACING_ON
1177 if (DTRACE(O3PipeView)) {
1178 storeQueue[store_idx].inst->storeTick =
1179 curTick() - storeQueue[store_idx].inst->fetchTick;
1180 }
1181#endif
1182
1183 if (isStalled() &&
1184 storeQueue[store_idx].inst->seqNum == stallingStoreIsn) {
1185 DPRINTF(LSQUnit, "Unstalling, stalling store [sn:%lli] "
1186 "load idx:%i\n",
1187 stallingStoreIsn, stallingLoadIdx);
1188 stalled = false;
1189 stallingStoreIsn = 0;
1190 iewStage->replayMemInst(loadQueue[stallingLoadIdx]);
1191 }
1192
1193 storeQueue[store_idx].inst->setCompleted();
1194
1195 if (needsTSO) {
1196 storeInFlight = false;
1197 }
1198
1199 // Tell the checker we've completed this instruction. Some stores
1200 // may get reported twice to the checker, but the checker can
1201 // handle that case.
1202 if (cpu->checker) {
1203 cpu->checker->verify(storeQueue[store_idx].inst);
1204 }
1205}
1206
1207template <class Impl>
1208bool
1209LSQUnit<Impl>::sendStore(PacketPtr data_pkt)
1210{
1211 if (!dcachePort->sendTimingReq(data_pkt)) {
1212 // Need to handle becoming blocked on a store.
1213 isStoreBlocked = true;
1214 ++lsqCacheBlocked;
1215 assert(retryPkt == NULL);
1216 retryPkt = data_pkt;
|
1221 lsq->setRetryTid(lsqID);
| |
1222 return false;
1223 }
1224 return true;
1225}
1226
1227template <class Impl>
1228void
1229LSQUnit<Impl>::recvRetry()
1230{
1231 if (isStoreBlocked) {
1232 DPRINTF(LSQUnit, "Receiving retry: store blocked\n");
1233 assert(retryPkt != NULL);
1234
1235 LSQSenderState *state =
1236 dynamic_cast<LSQSenderState *>(retryPkt->senderState);
1237
1238 if (dcachePort->sendTimingReq(retryPkt)) {
1239 // Don't finish the store unless this is the last packet.
1240 if (!TheISA::HasUnalignedMemAcc || !state->pktToSend ||
1241 state->pendingPacket == retryPkt) {
1242 state->pktToSend = false;
1243 storePostSend(retryPkt);
1244 }
1245 retryPkt = NULL;
1246 isStoreBlocked = false;
| 1217 return false;
1218 }
1219 return true;
1220}
1221
1222template <class Impl>
1223void
1224LSQUnit<Impl>::recvRetry()
1225{
1226 if (isStoreBlocked) {
1227 DPRINTF(LSQUnit, "Receiving retry: store blocked\n");
1228 assert(retryPkt != NULL);
1229
1230 LSQSenderState *state =
1231 dynamic_cast<LSQSenderState *>(retryPkt->senderState);
1232
1233 if (dcachePort->sendTimingReq(retryPkt)) {
1234 // Don't finish the store unless this is the last packet.
1235 if (!TheISA::HasUnalignedMemAcc || !state->pktToSend ||
1236 state->pendingPacket == retryPkt) {
1237 state->pktToSend = false;
1238 storePostSend(retryPkt);
1239 }
1240 retryPkt = NULL;
1241 isStoreBlocked = false;
|
1247 lsq->setRetryTid(InvalidThreadID);
| |
1248
1249 // Send any outstanding packet.
1250 if (TheISA::HasUnalignedMemAcc && state->pktToSend) {
1251 assert(state->pendingPacket);
1252 if (sendStore(state->pendingPacket)) {
1253 storePostSend(state->pendingPacket);
1254 }
1255 }
1256 } else {
1257 // Still blocked!
1258 ++lsqCacheBlocked;
| 1242
1243 // Send any outstanding packet.
1244 if (TheISA::HasUnalignedMemAcc && state->pktToSend) {
1245 assert(state->pendingPacket);
1246 if (sendStore(state->pendingPacket)) {
1247 storePostSend(state->pendingPacket);
1248 }
1249 }
1250 } else {
1251 // Still blocked!
1252 ++lsqCacheBlocked;
|
1259 lsq->setRetryTid(lsqID);
| |
1260 }
| 1253 }
|
1261 } else if (isLoadBlocked) {
1262 DPRINTF(LSQUnit, "Loads squash themselves and all younger insts, "
1263 "no need to resend packet.\n");
1264 } else {
1265 DPRINTF(LSQUnit, "Retry received but LSQ is no longer blocked.\n");
| |
1266 }
1267}
1268
1269template <class Impl>
1270inline void
1271LSQUnit<Impl>::incrStIdx(int &store_idx) const
1272{
1273 if (++store_idx >= SQEntries)
1274 store_idx = 0;
1275}
1276
1277template <class Impl>
1278inline void
1279LSQUnit<Impl>::decrStIdx(int &store_idx) const
1280{
1281 if (--store_idx < 0)
1282 store_idx += SQEntries;
1283}
1284
1285template <class Impl>
1286inline void
1287LSQUnit<Impl>::incrLdIdx(int &load_idx) const
1288{
1289 if (++load_idx >= LQEntries)
1290 load_idx = 0;
1291}
1292
1293template <class Impl>
1294inline void
1295LSQUnit<Impl>::decrLdIdx(int &load_idx) const
1296{
1297 if (--load_idx < 0)
1298 load_idx += LQEntries;
1299}
1300
1301template <class Impl>
1302void
1303LSQUnit<Impl>::dumpInsts() const
1304{
1305 cprintf("Load store queue: Dumping instructions.\n");
1306 cprintf("Load queue size: %i\n", loads);
1307 cprintf("Load queue: ");
1308
1309 int load_idx = loadHead;
1310
1311 while (load_idx != loadTail && loadQueue[load_idx]) {
1312 const DynInstPtr &inst(loadQueue[load_idx]);
1313 cprintf("%s.[sn:%i] ", inst->pcState(), inst->seqNum);
1314
1315 incrLdIdx(load_idx);
1316 }
1317 cprintf("\n");
1318
1319 cprintf("Store queue size: %i\n", stores);
1320 cprintf("Store queue: ");
1321
1322 int store_idx = storeHead;
1323
1324 while (store_idx != storeTail && storeQueue[store_idx].inst) {
1325 const DynInstPtr &inst(storeQueue[store_idx].inst);
1326 cprintf("%s.[sn:%i] ", inst->pcState(), inst->seqNum);
1327
1328 incrStIdx(store_idx);
1329 }
1330
1331 cprintf("\n");
1332}
1333
1334#endif//__CPU_O3_LSQ_UNIT_IMPL_HH__
| 1254 }
1255}
1256
1257template <class Impl>
1258inline void
1259LSQUnit<Impl>::incrStIdx(int &store_idx) const
1260{
1261 if (++store_idx >= SQEntries)
1262 store_idx = 0;
1263}
1264
1265template <class Impl>
1266inline void
1267LSQUnit<Impl>::decrStIdx(int &store_idx) const
1268{
1269 if (--store_idx < 0)
1270 store_idx += SQEntries;
1271}
1272
1273template <class Impl>
1274inline void
1275LSQUnit<Impl>::incrLdIdx(int &load_idx) const
1276{
1277 if (++load_idx >= LQEntries)
1278 load_idx = 0;
1279}
1280
1281template <class Impl>
1282inline void
1283LSQUnit<Impl>::decrLdIdx(int &load_idx) const
1284{
1285 if (--load_idx < 0)
1286 load_idx += LQEntries;
1287}
1288
1289template <class Impl>
1290void
1291LSQUnit<Impl>::dumpInsts() const
1292{
1293 cprintf("Load store queue: Dumping instructions.\n");
1294 cprintf("Load queue size: %i\n", loads);
1295 cprintf("Load queue: ");
1296
1297 int load_idx = loadHead;
1298
1299 while (load_idx != loadTail && loadQueue[load_idx]) {
1300 const DynInstPtr &inst(loadQueue[load_idx]);
1301 cprintf("%s.[sn:%i] ", inst->pcState(), inst->seqNum);
1302
1303 incrLdIdx(load_idx);
1304 }
1305 cprintf("\n");
1306
1307 cprintf("Store queue size: %i\n", stores);
1308 cprintf("Store queue: ");
1309
1310 int store_idx = storeHead;
1311
1312 while (store_idx != storeTail && storeQueue[store_idx].inst) {
1313 const DynInstPtr &inst(storeQueue[store_idx].inst);
1314 cprintf("%s.[sn:%i] ", inst->pcState(), inst->seqNum);
1315
1316 incrStIdx(store_idx);
1317 }
1318
1319 cprintf("\n");
1320}
1321
1322#endif//__CPU_O3_LSQ_UNIT_IMPL_HH__
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