lsq_unit_impl.hh (8592:30a97c4198df) | lsq_unit_impl.hh (8727:b3995530319f) |
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1/* 2 * Copyright (c) 2010 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 124 unchanged lines hidden (view full) --- 133 delete pkt->req; 134 delete pkt; 135} 136 137template <class Impl> 138LSQUnit<Impl>::LSQUnit() 139 : loads(0), stores(0), storesToWB(0), cacheBlockMask(0), stalled(false), 140 isStoreBlocked(false), isLoadBlocked(false), | 1/* 2 * Copyright (c) 2010 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 124 unchanged lines hidden (view full) --- 133 delete pkt->req; 134 delete pkt; 135} 136 137template <class Impl> 138LSQUnit<Impl>::LSQUnit() 139 : loads(0), stores(0), storesToWB(0), cacheBlockMask(0), stalled(false), 140 isStoreBlocked(false), isLoadBlocked(false), |
141 loadBlockedHandled(false), hasPendingPkt(false) | 141 loadBlockedHandled(false), storeInFlight(false), hasPendingPkt(false) |
142{ 143} 144 145template<class Impl> 146void 147LSQUnit<Impl>::init(O3CPU *cpu_ptr, IEW *iew_ptr, DerivO3CPUParams *params, 148 LSQ *lsq_ptr, unsigned maxLQEntries, unsigned maxSQEntries, 149 unsigned id) --- 27 unchanged lines hidden (view full) --- 177 178 usedPorts = 0; 179 cachePorts = params->cachePorts; 180 181 retryPkt = NULL; 182 memDepViolator = NULL; 183 184 blockedLoadSeqNum = 0; | 142{ 143} 144 145template<class Impl> 146void 147LSQUnit<Impl>::init(O3CPU *cpu_ptr, IEW *iew_ptr, DerivO3CPUParams *params, 148 LSQ *lsq_ptr, unsigned maxLQEntries, unsigned maxSQEntries, 149 unsigned id) --- 27 unchanged lines hidden (view full) --- 177 178 usedPorts = 0; 179 cachePorts = params->cachePorts; 180 181 retryPkt = NULL; 182 memDepViolator = NULL; 183 184 blockedLoadSeqNum = 0; |
185 needsTSO = params->needsTSO; |
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185} 186 187template<class Impl> 188std::string 189LSQUnit<Impl>::name() const 190{ 191 if (Impl::MaxThreads == 1) { 192 return iewStage->name() + ".lsq"; --- 572 unchanged lines hidden (view full) --- 765 if (TheISA::HasUnalignedMemAcc) { 766 writebackPendingStore(); 767 } 768 769 while (storesToWB > 0 && 770 storeWBIdx != storeTail && 771 storeQueue[storeWBIdx].inst && 772 storeQueue[storeWBIdx].canWB && | 186} 187 188template<class Impl> 189std::string 190LSQUnit<Impl>::name() const 191{ 192 if (Impl::MaxThreads == 1) { 193 return iewStage->name() + ".lsq"; --- 572 unchanged lines hidden (view full) --- 766 if (TheISA::HasUnalignedMemAcc) { 767 writebackPendingStore(); 768 } 769 770 while (storesToWB > 0 && 771 storeWBIdx != storeTail && 772 storeQueue[storeWBIdx].inst && 773 storeQueue[storeWBIdx].canWB && |
774 ((!needsTSO) || (!storeInFlight)) && |
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773 usedPorts < cachePorts) { 774 775 if (isStoreBlocked || lsq->cacheBlocked()) { 776 DPRINTF(LSQUnit, "Unable to write back any more stores, cache" 777 " is blocked!\n"); 778 break; 779 } 780 --- 304 unchanged lines hidden (view full) --- 1085 storeQueue[storeWBIdx].inst->setCompleted(); 1086#if USE_CHECKER 1087 if (cpu->checker) { 1088 cpu->checker->verify(storeQueue[storeWBIdx].inst); 1089 } 1090#endif 1091 } 1092 | 775 usedPorts < cachePorts) { 776 777 if (isStoreBlocked || lsq->cacheBlocked()) { 778 DPRINTF(LSQUnit, "Unable to write back any more stores, cache" 779 " is blocked!\n"); 780 break; 781 } 782 --- 304 unchanged lines hidden (view full) --- 1087 storeQueue[storeWBIdx].inst->setCompleted(); 1088#if USE_CHECKER 1089 if (cpu->checker) { 1090 cpu->checker->verify(storeQueue[storeWBIdx].inst); 1091 } 1092#endif 1093 } 1094 |
1095 if (needsTSO) { 1096 storeInFlight = true; 1097 } 1098 |
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1093 incrStIdx(storeWBIdx); 1094} 1095 1096template <class Impl> 1097void 1098LSQUnit<Impl>::writeback(DynInstPtr &inst, PacketPtr pkt) 1099{ 1100 iewStage->wakeCPU(); --- 57 unchanged lines hidden (view full) --- 1158 stallingStoreIsn, stallingLoadIdx); 1159 stalled = false; 1160 stallingStoreIsn = 0; 1161 iewStage->replayMemInst(loadQueue[stallingLoadIdx]); 1162 } 1163 1164 storeQueue[store_idx].inst->setCompleted(); 1165 | 1099 incrStIdx(storeWBIdx); 1100} 1101 1102template <class Impl> 1103void 1104LSQUnit<Impl>::writeback(DynInstPtr &inst, PacketPtr pkt) 1105{ 1106 iewStage->wakeCPU(); --- 57 unchanged lines hidden (view full) --- 1164 stallingStoreIsn, stallingLoadIdx); 1165 stalled = false; 1166 stallingStoreIsn = 0; 1167 iewStage->replayMemInst(loadQueue[stallingLoadIdx]); 1168 } 1169 1170 storeQueue[store_idx].inst->setCompleted(); 1171 |
1172 if (needsTSO) { 1173 storeInFlight = false; 1174 } 1175 |
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1166 // Tell the checker we've completed this instruction. Some stores 1167 // may get reported twice to the checker, but the checker can 1168 // handle that case. 1169#if USE_CHECKER 1170 if (cpu->checker) { 1171 cpu->checker->verify(storeQueue[store_idx].inst); 1172 } 1173#endif --- 121 unchanged lines hidden --- | 1176 // Tell the checker we've completed this instruction. Some stores 1177 // may get reported twice to the checker, but the checker can 1178 // handle that case. 1179#if USE_CHECKER 1180 if (cpu->checker) { 1181 cpu->checker->verify(storeQueue[store_idx].inst); 1182 } 1183#endif --- 121 unchanged lines hidden --- |