lsq_unit_impl.hh (3731:4cd483eb6f16) | lsq_unit_impl.hh (3772:71cccab4eff8) |
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1/* 2 * Copyright (c) 2004-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 404 unchanged lines hidden (view full) --- 413 414 // If the instruction faulted, then we need to send it along to commit 415 // without the instruction completing. 416 if (load_fault != NoFault) { 417 // Send this instruction to commit, also make sure iew stage 418 // realizes there is activity. 419 // Mark it as executed unless it is an uncached load that 420 // needs to hit the head of commit. | 1/* 2 * Copyright (c) 2004-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 404 unchanged lines hidden (view full) --- 413 414 // If the instruction faulted, then we need to send it along to commit 415 // without the instruction completing. 416 if (load_fault != NoFault) { 417 // Send this instruction to commit, also make sure iew stage 418 // realizes there is activity. 419 // Mark it as executed unless it is an uncached load that 420 // needs to hit the head of commit. |
421 if (!(inst->req && inst->req->isUncacheable()) || 422 inst->isAtCommit()) { | 421 if (!(inst->req->isUncacheable()) || inst->isAtCommit()) { |
423 inst->setExecuted(); 424 } 425 iewStage->instToCommit(inst); 426 iewStage->activityThisCycle(); 427 } 428 429 return load_fault; 430} --- 161 unchanged lines hidden (view full) --- 592 593 DynInstPtr inst = storeQueue[storeWBIdx].inst; 594 595 Request *req = storeQueue[storeWBIdx].req; 596 storeQueue[storeWBIdx].committed = true; 597 598 assert(!inst->memData); 599 inst->memData = new uint8_t[64]; | 422 inst->setExecuted(); 423 } 424 iewStage->instToCommit(inst); 425 iewStage->activityThisCycle(); 426 } 427 428 return load_fault; 429} --- 161 unchanged lines hidden (view full) --- 591 592 DynInstPtr inst = storeQueue[storeWBIdx].inst; 593 594 Request *req = storeQueue[storeWBIdx].req; 595 storeQueue[storeWBIdx].committed = true; 596 597 assert(!inst->memData); 598 inst->memData = new uint8_t[64]; |
600 memcpy(inst->memData, (uint8_t *)&storeQueue[storeWBIdx].data, | 599 600 TheISA::IntReg convertedData = 601 TheISA::htog(storeQueue[storeWBIdx].data); 602 603 memcpy(inst->memData, (uint8_t *)&convertedData, |
601 req->getSize()); 602 603 PacketPtr data_pkt = new Packet(req, Packet::WriteReq, Packet::Broadcast); 604 data_pkt->dataStatic(inst->memData); 605 606 LSQSenderState *state = new LSQSenderState; 607 state->isLoad = false; 608 state->idx = storeWBIdx; --- 370 unchanged lines hidden --- | 604 req->getSize()); 605 606 PacketPtr data_pkt = new Packet(req, Packet::WriteReq, Packet::Broadcast); 607 data_pkt->dataStatic(inst->memData); 608 609 LSQSenderState *state = new LSQSenderState; 610 state->isLoad = false; 611 state->idx = storeWBIdx; --- 370 unchanged lines hidden --- |