lsq_unit_impl.hh (2871:7ed5c9ef3eb6) | lsq_unit_impl.hh (2907:7b0ababb4166) |
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1/* 2 * Copyright (c) 2004-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 17 unchanged lines hidden (view full) --- 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Kevin Lim 29 * Korey Sewell 30 */ 31 32#include "config/use_checker.hh" 33 | 1/* 2 * Copyright (c) 2004-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 17 unchanged lines hidden (view full) --- 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Kevin Lim 29 * Korey Sewell 30 */ 31 32#include "config/use_checker.hh" 33 |
34#include "cpu/o3/lsq.hh" |
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34#include "cpu/o3/lsq_unit.hh" 35#include "base/str.hh" 36#include "mem/packet.hh" 37#include "mem/request.hh" 38 39#if USE_CHECKER 40#include "cpu/checker/cpu.hh" 41#endif --- 49 unchanged lines hidden (view full) --- 91 } 92 } 93 94 delete state; 95 delete pkt; 96} 97 98template <class Impl> | 35#include "cpu/o3/lsq_unit.hh" 36#include "base/str.hh" 37#include "mem/packet.hh" 38#include "mem/request.hh" 39 40#if USE_CHECKER 41#include "cpu/checker/cpu.hh" 42#endif --- 49 unchanged lines hidden (view full) --- 92 } 93 } 94 95 delete state; 96 delete pkt; 97} 98 99template <class Impl> |
99Tick 100LSQUnit<Impl>::DcachePort::recvAtomic(PacketPtr pkt) 101{ 102 panic("O3CPU model does not work with atomic mode!"); 103 return curTick; 104} 105 106template <class Impl> 107void 108LSQUnit<Impl>::DcachePort::recvFunctional(PacketPtr pkt) 109{ 110 panic("O3CPU doesn't expect recvFunctional callback!"); 111} 112 113template <class Impl> 114void 115LSQUnit<Impl>::DcachePort::recvStatusChange(Status status) 116{ 117 if (status == RangeChange) 118 return; 119 120 panic("O3CPU doesn't expect recvStatusChange callback!"); 121} 122 123template <class Impl> 124bool 125LSQUnit<Impl>::DcachePort::recvTiming(PacketPtr pkt) 126{ 127 lsq->completeDataAccess(pkt); 128 return true; 129} 130 131template <class Impl> 132void 133LSQUnit<Impl>::DcachePort::recvRetry() 134{ 135 lsq->recvRetry(); 136} 137 138template <class Impl> | |
139LSQUnit<Impl>::LSQUnit() 140 : loads(0), stores(0), storesToWB(0), stalled(false), 141 isStoreBlocked(false), isLoadBlocked(false), 142 loadBlockedHandled(false) 143{ 144} 145 146template<class Impl> 147void | 100LSQUnit<Impl>::LSQUnit() 101 : loads(0), stores(0), storesToWB(0), stalled(false), 102 isStoreBlocked(false), isLoadBlocked(false), 103 loadBlockedHandled(false) 104{ 105} 106 107template<class Impl> 108void |
148LSQUnit | 109LSQUnit<Impl>::init(Params *params, LSQ *lsq_ptr, unsigned maxLQEntries, |
149 unsigned maxSQEntries, unsigned id) 150{ 151 DPRINTF(LSQUnit, "Creating LSQUnit%i object.\n",id); 152 153 switchedOut = false; 154 | 110 unsigned maxSQEntries, unsigned id) 111{ 112 DPRINTF(LSQUnit, "Creating LSQUnit%i object.\n",id); 113 114 switchedOut = false; 115 |
116 lsq = lsq_ptr; 117 |
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155 lsqID = id; 156 157 // Add 1 for the sentinel entry (they are circular queues). 158 LQEntries = maxLQEntries + 1; 159 SQEntries = maxSQEntries + 1; 160 161 loadQueue.resize(LQEntries); 162 storeQueue.resize(SQEntries); 163 164 loadHead = loadTail = 0; 165 166 storeHead = storeWBIdx = storeTail = 0; 167 168 usedPorts = 0; 169 cachePorts = params->cachePorts; 170 | 118 lsqID = id; 119 120 // Add 1 for the sentinel entry (they are circular queues). 121 LQEntries = maxLQEntries + 1; 122 SQEntries = maxSQEntries + 1; 123 124 loadQueue.resize(LQEntries); 125 storeQueue.resize(SQEntries); 126 127 loadHead = loadTail = 0; 128 129 storeHead = storeWBIdx = storeTail = 0; 130 131 usedPorts = 0; 132 cachePorts = params->cachePorts; 133 |
171 mem = params->mem; 172 | |
173 memDepViolator = NULL; 174 175 blockedLoadSeqNum = 0; 176} 177 178template<class Impl> 179void 180LSQUnit<Impl>::setCPU(O3CPU *cpu_ptr) 181{ 182 cpu = cpu_ptr; | 134 memDepViolator = NULL; 135 136 blockedLoadSeqNum = 0; 137} 138 139template<class Impl> 140void 141LSQUnit<Impl>::setCPU(O3CPU *cpu_ptr) 142{ 143 cpu = cpu_ptr; |
183 dcachePort = new DcachePort(cpu, this); | |
184 185#if USE_CHECKER 186 if (cpu->checker) { 187 cpu->checker->setDcachePort(dcachePort); 188 } 189#endif 190} 191 --- 391 unchanged lines hidden (view full) --- 583LSQUnit<Impl>::writebackStores() 584{ 585 while (storesToWB > 0 && 586 storeWBIdx != storeTail && 587 storeQueue[storeWBIdx].inst && 588 storeQueue[storeWBIdx].canWB && 589 usedPorts < cachePorts) { 590 | 144 145#if USE_CHECKER 146 if (cpu->checker) { 147 cpu->checker->setDcachePort(dcachePort); 148 } 149#endif 150} 151 --- 391 unchanged lines hidden (view full) --- 543LSQUnit<Impl>::writebackStores() 544{ 545 while (storesToWB > 0 && 546 storeWBIdx != storeTail && 547 storeQueue[storeWBIdx].inst && 548 storeQueue[storeWBIdx].canWB && 549 usedPorts < cachePorts) { 550 |
591 if (isStoreBlocked) { | 551 if (isStoreBlocked || lsq->cacheBlocked()) { |
592 DPRINTF(LSQUnit, "Unable to write back any more stores, cache" 593 " is blocked!\n"); 594 break; 595 } 596 597 // Store didn't write any data so no need to write it back to 598 // memory. 599 if (storeQueue[storeWBIdx].size == 0) { --- 306 unchanged lines hidden (view full) --- 906 907 if (dcachePort->sendTiming(retryPkt)) { 908 storePostSend(retryPkt); 909 retryPkt = NULL; 910 isStoreBlocked = false; 911 } else { 912 // Still blocked! 913 ++lsqCacheBlocked; | 552 DPRINTF(LSQUnit, "Unable to write back any more stores, cache" 553 " is blocked!\n"); 554 break; 555 } 556 557 // Store didn't write any data so no need to write it back to 558 // memory. 559 if (storeQueue[storeWBIdx].size == 0) { --- 306 unchanged lines hidden (view full) --- 866 867 if (dcachePort->sendTiming(retryPkt)) { 868 storePostSend(retryPkt); 869 retryPkt = NULL; 870 isStoreBlocked = false; 871 } else { 872 // Still blocked! 873 ++lsqCacheBlocked; |
874 lsq->setRetryTid(lsqID); |
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914 } 915 } else if (isLoadBlocked) { 916 DPRINTF(LSQUnit, "Loads squash themselves and all younger insts, " 917 "no need to resend packet.\n"); 918 } else { 919 DPRINTF(LSQUnit, "Retry received but LSQ is no longer blocked.\n"); 920 } 921} --- 62 unchanged lines hidden --- | 875 } 876 } else if (isLoadBlocked) { 877 DPRINTF(LSQUnit, "Loads squash themselves and all younger insts, " 878 "no need to resend packet.\n"); 879 } else { 880 DPRINTF(LSQUnit, "Retry received but LSQ is no longer blocked.\n"); 881 } 882} --- 62 unchanged lines hidden --- |