lsq_unit_impl.hh (2692:e5b7553eff69) | lsq_unit_impl.hh (2693:18c6be231eb1) |
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1/* 2 * Copyright (c) 2004-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 111 unchanged lines hidden (view full) --- 120 lsq->completeDataAccess(pkt); 121 return true; 122} 123 124template <class Impl> 125void 126LSQUnit<Impl>::DcachePort::recvRetry() 127{ | 1/* 2 * Copyright (c) 2004-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 111 unchanged lines hidden (view full) --- 120 lsq->completeDataAccess(pkt); 121 return true; 122} 123 124template <class Impl> 125void 126LSQUnit<Impl>::DcachePort::recvRetry() 127{ |
128 panic("Retry unsupported for now!"); 129 // we shouldn't get a retry unless we have a packet that we're 130 // waiting to transmit 131/* 132 assert(cpu->dcache_pkt != NULL); 133 assert(cpu->_status == DcacheRetry); 134 PacketPtr tmp = cpu->dcache_pkt; 135 if (sendTiming(tmp)) { 136 cpu->_status = DcacheWaitResponse; 137 cpu->dcache_pkt = NULL; 138 } 139*/ | 128 lsq->recvRetry(); |
140} 141 142template <class Impl> 143LSQUnit<Impl>::LSQUnit() 144 : loads(0), stores(0), storesToWB(0), stalled(false), 145 isStoreBlocked(false), isLoadBlocked(false), 146 loadBlockedHandled(false) 147{ --- 462 unchanged lines hidden (view full) --- 610 data_pkt->senderState = state; 611 612 DPRINTF(LSQUnit, "D-Cache: Writing back store idx:%i PC:%#x " 613 "to Addr:%#x, data:%#x [sn:%lli]\n", 614 storeWBIdx, storeQueue[storeWBIdx].inst->readPC(), 615 req->getPaddr(), *(inst->memData), 616 storeQueue[storeWBIdx].inst->seqNum); 617 | 129} 130 131template <class Impl> 132LSQUnit<Impl>::LSQUnit() 133 : loads(0), stores(0), storesToWB(0), stalled(false), 134 isStoreBlocked(false), isLoadBlocked(false), 135 loadBlockedHandled(false) 136{ --- 462 unchanged lines hidden (view full) --- 599 data_pkt->senderState = state; 600 601 DPRINTF(LSQUnit, "D-Cache: Writing back store idx:%i PC:%#x " 602 "to Addr:%#x, data:%#x [sn:%lli]\n", 603 storeWBIdx, storeQueue[storeWBIdx].inst->readPC(), 604 req->getPaddr(), *(inst->memData), 605 storeQueue[storeWBIdx].inst->seqNum); 606 |
607 // @todo: Remove this SC hack once the memory system handles it. 608 if (req->getFlags() & LOCKED) { 609 if (req->getFlags() & UNCACHEABLE) { 610 req->setScResult(2); 611 } else { 612 if (cpu->lockFlag) { 613 req->setScResult(1); 614 } else { 615 req->setScResult(0); 616 // Hack: Instantly complete this store. 617 completeDataAccess(data_pkt); 618 incrStIdx(storeWBIdx); 619 continue; 620 } 621 } 622 } else { 623 // Non-store conditionals do not need a writeback. 624 state->noWB = true; 625 } 626 |
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618 if (!dcachePort->sendTiming(data_pkt)) { 619 // Need to handle becoming blocked on a store. 620 isStoreBlocked = true; | 627 if (!dcachePort->sendTiming(data_pkt)) { 628 // Need to handle becoming blocked on a store. 629 isStoreBlocked = true; |
621 } else { 622 if (isStalled() && 623 storeQueue[storeWBIdx].inst->seqNum == stallingStoreIsn) { 624 DPRINTF(LSQUnit, "Unstalling, stalling store [sn:%lli] " 625 "load idx:%i\n", 626 stallingStoreIsn, stallingLoadIdx); 627 stalled = false; 628 stallingStoreIsn = 0; 629 iewStage->replayMemInst(loadQueue[stallingLoadIdx]); 630 } | |
631 | 630 |
632 if (!(req->getFlags() & LOCKED)) { 633 assert(!storeQueue[storeWBIdx].inst->isStoreConditional()); 634 // Non-store conditionals do not need a writeback. 635 state->noWB = true; 636 637 // The store is basically completed at this time. This 638 // only works so long as the checker doesn't try to 639 // verify the value in memory for stores. 640 storeQueue[storeWBIdx].inst->setCompleted(); 641 if (cpu->checker) { 642 cpu->checker->tick(storeQueue[storeWBIdx].inst); 643 } 644 } 645 646 if (data_pkt->result != Packet::Success) { 647 DPRINTF(LSQUnit,"D-Cache Write Miss on idx:%i!\n", 648 storeWBIdx); 649 650 DPRINTF(Activity, "Active st accessing mem miss [sn:%lli]\n", 651 storeQueue[storeWBIdx].inst->seqNum); 652 653 //mshrSeqNums.push_back(storeQueue[storeWBIdx].inst->seqNum); 654 655 //DPRINTF(LSQUnit, "Added MSHR. count = %i\n",mshrSeqNums.size()); 656 657 // @todo: Increment stat here. 658 } else { 659 DPRINTF(LSQUnit,"D-Cache: Write Hit on idx:%i !\n", 660 storeWBIdx); 661 662 DPRINTF(Activity, "Active st accessing mem hit [sn:%lli]\n", 663 storeQueue[storeWBIdx].inst->seqNum); 664 } 665 666 incrStIdx(storeWBIdx); | 631 assert(sendingPkt == NULL); 632 sendingPkt = data_pkt; 633 } else { 634 storePostSend(data_pkt); |
667 } 668 } 669 670 // Not sure this should set it to 0. 671 usedPorts = 0; 672 673 assert(stores >= 0 && storesToWB >= 0); 674} --- 89 unchanged lines hidden (view full) --- 764 storeTail = store_idx; 765 766 decrStIdx(store_idx); 767 } 768} 769 770template <class Impl> 771void | 635 } 636 } 637 638 // Not sure this should set it to 0. 639 usedPorts = 0; 640 641 assert(stores >= 0 && storesToWB >= 0); 642} --- 89 unchanged lines hidden (view full) --- 732 storeTail = store_idx; 733 734 decrStIdx(store_idx); 735 } 736} 737 738template <class Impl> 739void |
740LSQUnit<Impl>::storePostSend(Packet *pkt) 741{ 742 if (isStalled() && 743 storeQueue[storeWBIdx].inst->seqNum == stallingStoreIsn) { 744 DPRINTF(LSQUnit, "Unstalling, stalling store [sn:%lli] " 745 "load idx:%i\n", 746 stallingStoreIsn, stallingLoadIdx); 747 stalled = false; 748 stallingStoreIsn = 0; 749 iewStage->replayMemInst(loadQueue[stallingLoadIdx]); 750 } 751 752 if (!storeQueue[storeWBIdx].inst->isStoreConditional()) { 753 // The store is basically completed at this time. This 754 // only works so long as the checker doesn't try to 755 // verify the value in memory for stores. 756 storeQueue[storeWBIdx].inst->setCompleted(); 757 if (cpu->checker) { 758 cpu->checker->tick(storeQueue[storeWBIdx].inst); 759 } 760 } 761 762 if (pkt->result != Packet::Success) { 763 DPRINTF(LSQUnit,"D-Cache Write Miss on idx:%i!\n", 764 storeWBIdx); 765 766 DPRINTF(Activity, "Active st accessing mem miss [sn:%lli]\n", 767 storeQueue[storeWBIdx].inst->seqNum); 768 769 //mshrSeqNums.push_back(storeQueue[storeWBIdx].inst->seqNum); 770 771 //DPRINTF(LSQUnit, "Added MSHR. count = %i\n",mshrSeqNums.size()); 772 773 // @todo: Increment stat here. 774 } else { 775 DPRINTF(LSQUnit,"D-Cache: Write Hit on idx:%i !\n", 776 storeWBIdx); 777 778 DPRINTF(Activity, "Active st accessing mem hit [sn:%lli]\n", 779 storeQueue[storeWBIdx].inst->seqNum); 780 } 781 782 incrStIdx(storeWBIdx); 783} 784 785template <class Impl> 786void |
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772LSQUnit<Impl>::writeback(DynInstPtr &inst, PacketPtr pkt) 773{ 774 iewStage->wakeCPU(); 775 776 // Squashed instructions do not need to complete their access. 777 if (inst->isSquashed()) { 778 assert(!inst->isStore()); 779 return; --- 55 unchanged lines hidden (view full) --- 835 // may get reported twice to the checker, but the checker can 836 // handle that case. 837 if (cpu->checker) { 838 cpu->checker->tick(storeQueue[store_idx].inst); 839 } 840} 841 842template <class Impl> | 787LSQUnit<Impl>::writeback(DynInstPtr &inst, PacketPtr pkt) 788{ 789 iewStage->wakeCPU(); 790 791 // Squashed instructions do not need to complete their access. 792 if (inst->isSquashed()) { 793 assert(!inst->isStore()); 794 return; --- 55 unchanged lines hidden (view full) --- 850 // may get reported twice to the checker, but the checker can 851 // handle that case. 852 if (cpu->checker) { 853 cpu->checker->tick(storeQueue[store_idx].inst); 854 } 855} 856 857template <class Impl> |
858void 859LSQUnit<Impl>::recvRetry() 860{ 861 assert(sendingPkt != NULL); 862 863 if (isStoreBlocked) { 864 if (dcachePort->sendTiming(sendingPkt)) { 865 storePostSend(sendingPkt); 866 sendingPkt = NULL; 867 isStoreBlocked = false; 868 } else { 869 // Still blocked! 870 } 871 } else if (isLoadBlocked) { 872 DPRINTF(LSQUnit, "Loads squash themselves and all younger insts, " 873 "no need to resend packet.\n"); 874 } else { 875 DPRINTF(LSQUnit, "Retry received but LSQ is no longer blocked.\n"); 876 } 877} 878 879template <class Impl> |
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843inline void 844LSQUnit<Impl>::incrStIdx(int &store_idx) 845{ 846 if (++store_idx >= SQEntries) 847 store_idx = 0; 848} 849 850template <class Impl> --- 52 unchanged lines hidden --- | 880inline void 881LSQUnit<Impl>::incrStIdx(int &store_idx) 882{ 883 if (++store_idx >= SQEntries) 884 store_idx = 0; 885} 886 887template <class Impl> --- 52 unchanged lines hidden --- |