1
2/*
3 * Copyright (c) 2010-2012 ARM Limited
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating

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153 lsq = lsq_ptr;
154
155 lsqID = id;
156
157 // Add 1 for the sentinel entry (they are circular queues).
158 LQEntries = maxLQEntries + 1;
159 SQEntries = maxSQEntries + 1;
160
161 loadQueue.resize(LQEntries);
162 storeQueue.resize(SQEntries);
163
164 depCheckShift = params->LSQDepCheckShift;
165 checkLoads = params->LSQCheckLoads;
166 cachePorts = params->cachePorts;
167 needsTSO = params->needsTSO;
168

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301 DynInstPtr dummy;
302 loadQueue.push_back(dummy);
303 LQEntries++;
304 }
305 } else {
306 LQEntries = size_plus_sentinel;
307 }
308
309}
310
311template<class Impl>
312void
313LSQUnit<Impl>::resizeSQ(unsigned size)
314{
315 unsigned size_plus_sentinel = size + 1;
316 if (size_plus_sentinel > SQEntries) {
317 while (size_plus_sentinel > storeQueue.size()) {
318 SQEntry dummy;
319 storeQueue.push_back(dummy);
320 SQEntries++;
321 }
322 } else {
323 SQEntries = size_plus_sentinel;
324 }
325}
326
327template <class Impl>
328void
329LSQUnit<Impl>::insert(DynInstPtr &inst)
330{
331 assert(inst->isMemRef());
332

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