1/*
2 * Copyright (c) 2010-2012 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 176 unchanged lines hidden (view full) ---

185 memDepViolator = NULL;
186
187 blockedLoadSeqNum = 0;
188
189 stalled = false;
190 isLoadBlocked = false;
191 loadBlockedHandled = false;
192
193 cacheBlockMask = 0;
194}
195
196template<class Impl>
197std::string
198LSQUnit<Impl>::name() const
199{
200 if (Impl::MaxThreads == 1) {
201 return iewStage->name() + ".lsq";

--- 212 unchanged lines hidden (view full) ---

414}
415
416template <class Impl>
417void
418LSQUnit<Impl>::checkSnoop(PacketPtr pkt)
419{
420 int load_idx = loadHead;
421
422 if (!cacheBlockMask) {
423 assert(dcachePort);
424 Addr bs = dcachePort->peerBlockSize();
425
426 // Make sure we actually got a size
427 assert(bs != 0);
428
429 cacheBlockMask = ~(bs - 1);
430 }
431
432 // Unlock the cpu-local monitor when the CPU sees a snoop to a locked
433 // address. The CPU can speculatively execute a LL operation after a pending
434 // SC operation in the pipeline and that can make the cache monitor the CPU
435 // is connected to valid while it really shouldn't be.
436 for (int x = 0; x < cpu->numActiveThreads(); x++) {
437 ThreadContext *tc = cpu->getContext(x);
438 bool no_squash = cpu->thread[x]->noSquashFromTC;
439 cpu->thread[x]->noSquashFromTC = true;

--- 854 unchanged lines hidden ---