1/*
2 * Copyright (c) 2010-2012 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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46#include "base/str.hh"
47#include "config/the_isa.hh"
48#include "cpu/checker/cpu.hh"
49#include "cpu/o3/lsq.hh"
50#include "cpu/o3/lsq_unit.hh"
51#include "debug/Activity.hh"
52#include "debug/IEW.hh"
53#include "debug/LSQUnit.hh"
54#include "mem/packet.hh"
55#include "mem/request.hh"
56
57template<class Impl>
58LSQUnit<Impl>::WritebackEvent::WritebackEvent(DynInstPtr &_inst, PacketPtr _pkt,
59 LSQUnit *lsq_ptr)
60 : Event(Default_Pri, AutoDelete),
61 inst(_inst), pkt(_pkt), lsqPtr(lsq_ptr)

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1132
1133 iewStage->updateLSQNextCycle = true;
1134 }
1135
1136 DPRINTF(LSQUnit, "Completing store [sn:%lli], idx:%i, store head "
1137 "idx:%i\n",
1138 storeQueue[store_idx].inst->seqNum, store_idx, storeHead);
1139
1140 if (isStalled() &&
1141 storeQueue[store_idx].inst->seqNum == stallingStoreIsn) {
1142 DPRINTF(LSQUnit, "Unstalling, stalling store [sn:%lli] "
1143 "load idx:%i\n",
1144 stallingStoreIsn, stallingLoadIdx);
1145 stalled = false;
1146 stallingStoreIsn = 0;
1147 iewStage->replayMemInst(loadQueue[stallingLoadIdx]);

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