1/*
2 * Copyright (c) 2010-2012 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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61 inst(_inst), pkt(_pkt), lsqPtr(lsq_ptr)
62{
63}
64
65template<class Impl>
66void
67LSQUnit<Impl>::WritebackEvent::process()
68{
69 if (!lsqPtr->isSwitchedOut()) {
70 lsqPtr->writeback(inst, pkt);
71 }
72
73 if (pkt->senderState)
74 delete pkt->senderState;
75
76 delete pkt->req;
77 delete pkt;
78}
79
80template<class Impl>

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97
98 // If this is a split access, wait until all packets are received.
99 if (TheISA::HasUnalignedMemAcc && !state->complete()) {
100 delete pkt->req;
101 delete pkt;
102 return;
103 }
104
105 if (isSwitchedOut() || inst->isSquashed()) {
106 iewStage->decrWb(inst->seqNum);
107 } else {
108 if (!state->noWB) {
109 if (!TheISA::HasUnalignedMemAcc || !state->isSplit ||
110 !state->isLoad) {
111 writeback(inst, pkt);
112 } else {
113 writeback(inst, state->mainPkt);

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142 LSQ *lsq_ptr, unsigned maxLQEntries, unsigned maxSQEntries,
143 unsigned id)
144{
145 cpu = cpu_ptr;
146 iewStage = iew_ptr;
147
148 DPRINTF(LSQUnit, "Creating LSQUnit%i object.\n",id);
149
150 switchedOut = false;
151
152 cacheBlockMask = 0;
153
154 lsq = lsq_ptr;
155
156 lsqID = id;
157
158 // Add 1 for the sentinel entry (they are circular queues).
159 LQEntries = maxLQEntries + 1;
160 SQEntries = maxSQEntries + 1;
161
162 loadQueue.resize(LQEntries);
163 storeQueue.resize(SQEntries);
164
165 depCheckShift = params->LSQDepCheckShift;
166 checkLoads = params->LSQCheckLoads;
167
168 loadHead = loadTail = 0;
169
170 storeHead = storeWBIdx = storeTail = 0;
171
172 usedPorts = 0;
173 cachePorts = params->cachePorts;
174
175 retryPkt = NULL;
176 memDepViolator = NULL;
177
178 blockedLoadSeqNum = 0;
179 needsTSO = params->needsTSO;
180}
181
182template<class Impl>
183std::string
184LSQUnit<Impl>::name() const
185{
186 if (Impl::MaxThreads == 1) {
187 return iewStage->name() + ".lsq";

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253void
254LSQUnit<Impl>::clearSQ()
255{
256 storeQueue.clear();
257}
258
259template<class Impl>
260void
261LSQUnit<Impl>::switchOut()
262{
263 switchedOut = true;
264 for (int i = 0; i < loadQueue.size(); ++i) {
265 assert(!loadQueue[i]);
266 loadQueue[i] = NULL;
267 }
268
269 assert(storesToWB == 0);
270}
271
272template<class Impl>
273void
274LSQUnit<Impl>::takeOverFrom()
275{
276 switchedOut = false;
277 loads = stores = storesToWB = 0;
278
279 loadHead = loadTail = 0;
280
281 storeHead = storeWBIdx = storeTail = 0;
282
283 usedPorts = 0;
284
285 memDepViolator = NULL;
286
287 blockedLoadSeqNum = 0;
288
289 stalled = false;
290 isLoadBlocked = false;
291 loadBlockedHandled = false;
292
293 // Just incase the memory system changed out from under us
294 cacheBlockMask = 0;
295}
296
297template<class Impl>
298void
299LSQUnit<Impl>::resizeLQ(unsigned size)
300{
301 unsigned size_plus_sentinel = size + 1;
302 assert(size_plus_sentinel >= LQEntries);

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