1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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157
158 // Add 1 for the sentinel entry (they are circular queues).
159 LQEntries = maxLQEntries + 1;
160 SQEntries = maxSQEntries + 1;
161
162 loadQueue.resize(LQEntries);
163 storeQueue.resize(SQEntries);
164
165 loadHead = loadTail = 0;
166
167 storeHead = storeWBIdx = storeTail = 0;
168
169 usedPorts = 0;
170 cachePorts = params->cachePorts;
171
172 retryPkt = NULL;

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433 }
434 }
435
436 return retval;
437}
438
439template <class Impl>
440Fault
441LSQUnit<Impl>::executeLoad(DynInstPtr &inst)
442{
443 using namespace TheISA;
444 // Execute a specific load.
445 Fault load_fault = NoFault;
446
447 DPRINTF(LSQUnit, "Executing load PC %s, [sn:%lli]\n",
448 inst->pcState(), inst->seqNum);

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472 inst->setExecuted();
473 }
474 iewStage->instToCommit(inst);
475 iewStage->activityThisCycle();
476 } else if (!loadBlocked()) {
477 assert(inst->effAddrValid);
478 int load_idx = inst->lqIdx;
479 incrLdIdx(load_idx);
480 while (load_idx != loadTail) {
481 // Really only need to check loads that have actually executed
482
483 // @todo: For now this is extra conservative, detecting a
484 // violation if the addresses match assuming all accesses
485 // are quad word accesses.
486
487 // @todo: Fix this, magic number being used here
488
489 // @todo: Uncachable load is not executed until it reaches
490 // the head of the ROB. Once this if checks only the executed
491 // loads(as noted above), this check can be removed
492 if (loadQueue[load_idx]->effAddrValid &&
493 ((loadQueue[load_idx]->effAddr >> 8)
494 == (inst->effAddr >> 8)) &&
495 !loadQueue[load_idx]->uncacheable()) {
496 // A load incorrectly passed this load. Squash and refetch.
497 // For now return a fault to show that it was unsuccessful.
498 DynInstPtr violator = loadQueue[load_idx];
499 if (!memDepViolator ||
500 (violator->seqNum < memDepViolator->seqNum)) {
501 memDepViolator = violator;
502 } else {
503 break;
504 }
505
506 ++lsqMemOrderViolation;
507
508 return genMachineCheckFault();
509 }
510
511 incrLdIdx(load_idx);
512 }
513 }
514
515 return load_fault;
516}
517
518template <class Impl>
519Fault
520LSQUnit<Impl>::executeStore(DynInstPtr &store_inst)

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559 if (store_inst->isStoreConditional()) {
560 // Store conditionals need to set themselves as able to
561 // writeback if we haven't had a fault by here.
562 storeQueue[store_idx].canWB = true;
563
564 ++storesToWB;
565 }
566
567 assert(store_inst->effAddrValid);
568 while (load_idx != loadTail) {
569 // Really only need to check loads that have actually executed
570 // It's safe to check all loads because effAddr is set to
571 // InvalAddr when the dyn inst is created.
572
573 // @todo: For now this is extra conservative, detecting a
574 // violation if the addresses match assuming all accesses
575 // are quad word accesses.
576
577 // @todo: Fix this, magic number being used here
578
579 // @todo: Uncachable load is not executed until it reaches
580 // the head of the ROB. Once this if checks only the executed
581 // loads(as noted above), this check can be removed
582 if (loadQueue[load_idx]->effAddrValid &&
583 ((loadQueue[load_idx]->effAddr >> 8)
584 == (store_inst->effAddr >> 8)) &&
585 !loadQueue[load_idx]->uncacheable()) {
586 // A load incorrectly passed this store. Squash and refetch.
587 // For now return a fault to show that it was unsuccessful.
588 DynInstPtr violator = loadQueue[load_idx];
589 if (!memDepViolator ||
590 (violator->seqNum < memDepViolator->seqNum)) {
591 memDepViolator = violator;
592 } else {
593 break;
594 }
595
596 ++lsqMemOrderViolation;
597
598 return genMachineCheckFault();
599 }
600
601 incrLdIdx(load_idx);
602 }
603
604 return store_fault;
605}
606
607template <class Impl>
608void
609LSQUnit<Impl>::commitLoad()
610{
611 assert(loadQueue[loadHead]);
612

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