1/*
2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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596 storeQueue[storeWBIdx].committed = true;
597
598 assert(!inst->memData);
599 inst->memData = new uint8_t[64];
600
601 TheISA::IntReg convertedData =
602 TheISA::htog(storeQueue[storeWBIdx].data);
603
604 memcpy(inst->memData, (uint8_t *)&convertedData,
605 req->getSize());
606
607 PacketPtr data_pkt = new Packet(req, Packet::WriteReq, Packet::Broadcast);
608 data_pkt->dataStatic(inst->memData);
609
610 LSQSenderState *state = new LSQSenderState;
611 state->isLoad = false;
612 state->idx = storeWBIdx;
613 state->inst = inst;
614 data_pkt->senderState = state;
615
616 DPRINTF(LSQUnit, "D-Cache: Writing back store idx:%i PC:%#x "
617 "to Addr:%#x, data:%#x [sn:%lli]\n",
618 storeWBIdx, inst->readPC(),
619 req->getPaddr(), *(inst->memData),
620 inst->seqNum);
621
622 // @todo: Remove this SC hack once the memory system handles it.
623 if (req->isLocked()) {
624 // Disable recording the result temporarily. Writing to
625 // misc regs normally updates the result, but this is not
626 // the desired behavior when handling store conditionals.
627 inst->recordResult = false;

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