1/*
2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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120 lsq->completeDataAccess(pkt);
121 return true;
122}
123
124template <class Impl>
125void
126LSQUnit<Impl>::DcachePort::recvRetry()
127{
128 panic("Retry unsupported for now!");
129 // we shouldn't get a retry unless we have a packet that we're
130 // waiting to transmit
131/*
132 assert(cpu->dcache_pkt != NULL);
133 assert(cpu->_status == DcacheRetry);
134 PacketPtr tmp = cpu->dcache_pkt;
135 if (sendTiming(tmp)) {
136 cpu->_status = DcacheWaitResponse;
137 cpu->dcache_pkt = NULL;
138 }
139*/
140}
141
142template <class Impl>
143LSQUnit<Impl>::LSQUnit()
144 : loads(0), stores(0), storesToWB(0), stalled(false),
145 isStoreBlocked(false), isLoadBlocked(false),
146 loadBlockedHandled(false)
147{

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610 data_pkt->senderState = state;
611
612 DPRINTF(LSQUnit, "D-Cache: Writing back store idx:%i PC:%#x "
613 "to Addr:%#x, data:%#x [sn:%lli]\n",
614 storeWBIdx, storeQueue[storeWBIdx].inst->readPC(),
615 req->getPaddr(), *(inst->memData),
616 storeQueue[storeWBIdx].inst->seqNum);
617
618 if (!dcachePort->sendTiming(data_pkt)) {
619 // Need to handle becoming blocked on a store.
620 isStoreBlocked = true;
621 } else {
622 if (isStalled() &&
623 storeQueue[storeWBIdx].inst->seqNum == stallingStoreIsn) {
624 DPRINTF(LSQUnit, "Unstalling, stalling store [sn:%lli] "
625 "load idx:%i\n",
626 stallingStoreIsn, stallingLoadIdx);
627 stalled = false;
628 stallingStoreIsn = 0;
629 iewStage->replayMemInst(loadQueue[stallingLoadIdx]);
630 }
631
632 if (!(req->getFlags() & LOCKED)) {
633 assert(!storeQueue[storeWBIdx].inst->isStoreConditional());
634 // Non-store conditionals do not need a writeback.
635 state->noWB = true;
636
637 // The store is basically completed at this time. This
638 // only works so long as the checker doesn't try to
639 // verify the value in memory for stores.
640 storeQueue[storeWBIdx].inst->setCompleted();
641 if (cpu->checker) {
642 cpu->checker->tick(storeQueue[storeWBIdx].inst);
643 }
644 }
645
646 if (data_pkt->result != Packet::Success) {
647 DPRINTF(LSQUnit,"D-Cache Write Miss on idx:%i!\n",
648 storeWBIdx);
649
650 DPRINTF(Activity, "Active st accessing mem miss [sn:%lli]\n",
651 storeQueue[storeWBIdx].inst->seqNum);
652
653 //mshrSeqNums.push_back(storeQueue[storeWBIdx].inst->seqNum);
654
655 //DPRINTF(LSQUnit, "Added MSHR. count = %i\n",mshrSeqNums.size());
656
657 // @todo: Increment stat here.
658 } else {
659 DPRINTF(LSQUnit,"D-Cache: Write Hit on idx:%i !\n",
660 storeWBIdx);
661
662 DPRINTF(Activity, "Active st accessing mem hit [sn:%lli]\n",
663 storeQueue[storeWBIdx].inst->seqNum);
664 }
665
666 incrStIdx(storeWBIdx);
667 }
668 }
669
670 // Not sure this should set it to 0.
671 usedPorts = 0;
672
673 assert(stores >= 0 && storesToWB >= 0);
674}

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764 storeTail = store_idx;
765
766 decrStIdx(store_idx);
767 }
768}
769
770template <class Impl>
771void
772LSQUnit<Impl>::writeback(DynInstPtr &inst, PacketPtr pkt)
773{
774 iewStage->wakeCPU();
775
776 // Squashed instructions do not need to complete their access.
777 if (inst->isSquashed()) {
778 assert(!inst->isStore());
779 return;

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835 // may get reported twice to the checker, but the checker can
836 // handle that case.
837 if (cpu->checker) {
838 cpu->checker->tick(storeQueue[store_idx].inst);
839 }
840}
841
842template <class Impl>
843inline void
844LSQUnit<Impl>::incrStIdx(int &store_idx)
845{
846 if (++store_idx >= SQEntries)
847 store_idx = 0;
848}
849
850template <class Impl>

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