1
2/*
3 * Copyright (c) 2010-2014, 2017 ARM Limited
4 * Copyright (c) 2013 Advanced Micro Devices, Inc.
5 * All rights reserved
6 *
7 * The license below extends only to copyright in the software and shall
8 * not be construed as granting a license to any other intellectual

--- 128 unchanged lines hidden (view full) ---

137
138 pkt->req->setAccessLatency();
139 cpu->ppDataAccessComplete->notify(std::make_pair(inst, pkt));
140
141 delete state;
142}
143
144template <class Impl>
145LSQUnit::LSQUnit()
146 : loads(0), stores(0), storesToWB(0), cacheBlockMask(0), stalled(false),
147 isStoreBlocked(false), storeInFlight(false), hasPendingPkt(false),
148 pendingPkt(nullptr)
149{
150}
151
152template<class Impl>
153void
154LSQUnit<Impl>::init(O3CPU *cpu_ptr, IEW *iew_ptr, DerivO3CPUParams *params,
155 LSQ *lsq_ptr, unsigned maxLQEntries, unsigned maxSQEntries,
156 unsigned id)
157{
158 cpu = cpu_ptr;
159 iewStage = iew_ptr;
160
161 lsq = lsq_ptr;
162
163 lsqID = id;
164
165 DPRINTF(LSQUnit, "Creating LSQUnit%i object.\n",id);
166
167 // Add 1 for the sentinel entry (they are circular queues).
168 LQEntries = maxLQEntries + 1;
169 SQEntries = maxSQEntries + 1;
170
171 //Due to uint8_t index in LSQSenderState
172 assert(LQEntries <= 256);
173 assert(SQEntries <= 256);
174
175 loadQueue.resize(LQEntries);
176 storeQueue.resize(SQEntries);
177
178 depCheckShift = params->LSQDepCheckShift;
179 checkLoads = params->LSQCheckLoads;
180 cacheStorePorts = params->cacheStorePorts;
181 needsTSO = params->needsTSO;
182
183 resetState();
184}
185

--- 1140 unchanged lines hidden ---