1
2/*
3 * Copyright (c) 2010-2013 ARM Limited
4 * Copyright (c) 2013 Advanced Micro Devices, Inc.
5 * All rights reserved
6 *
7 * The license below extends only to copyright in the software and shall
8 * not be construed as granting a license to any other intellectual

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104 // If this is a split access, wait until all packets are received.
105 if (TheISA::HasUnalignedMemAcc && !state->complete()) {
106 delete pkt->req;
107 delete pkt;
108 return;
109 }
110
111 assert(!cpu->switchedOut());
112 if (inst->isSquashed()) {
113 iewStage->decrWb(inst->seqNum);
114 } else {
115 if (!state->noWB) {
116 if (!TheISA::HasUnalignedMemAcc || !state->isSplit ||
117 !state->isLoad) {
118 writeback(inst, pkt);
119 } else {
120 writeback(inst, state->mainPkt);
121 }
122 }

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1125template <class Impl>
1126void
1127LSQUnit<Impl>::writeback(DynInstPtr &inst, PacketPtr pkt)
1128{
1129 iewStage->wakeCPU();
1130
1131 // Squashed instructions do not need to complete their access.
1132 if (inst->isSquashed()) {
1133 iewStage->decrWb(inst->seqNum);
1134 assert(!inst->isStore());
1135 ++lsqIgnoredResponses;
1136 return;
1137 }
1138
1139 if (!inst->isExecuted()) {
1140 inst->setExecuted();
1141

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