1/*
2 * Copyright (c) 2010-2012 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2004-2005 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Kevin Lim
41 * Korey Sewell
42 */
43
44#include "arch/generic/debugfaults.hh"
45#include "arch/locked_mem.hh"
46#include "base/str.hh"
47#include "config/the_isa.hh"
48#include "cpu/checker/cpu.hh"
49#include "cpu/o3/lsq.hh"
50#include "cpu/o3/lsq_unit.hh"
51#include "debug/Activity.hh"
52#include "debug/IEW.hh"
53#include "debug/LSQUnit.hh"
54#include "mem/packet.hh"
55#include "mem/request.hh"
56
57template<class Impl>
58LSQUnit<Impl>::WritebackEvent::WritebackEvent(DynInstPtr &_inst, PacketPtr _pkt,
59 LSQUnit *lsq_ptr)
60 : Event(Default_Pri, AutoDelete),
61 inst(_inst), pkt(_pkt), lsqPtr(lsq_ptr)
62{
63}
64
65template<class Impl>
66void
67LSQUnit<Impl>::WritebackEvent::process()
68{
69 assert(!lsqPtr->cpu->switchedOut());
70
71 lsqPtr->writeback(inst, pkt);
72
73 if (pkt->senderState)
74 delete pkt->senderState;
75
76 delete pkt->req;
77 delete pkt;
78}
79
80template<class Impl>
81const char *
82LSQUnit<Impl>::WritebackEvent::description() const
83{
84 return "Store writeback";
85}
86
87template<class Impl>
88void
89LSQUnit<Impl>::completeDataAccess(PacketPtr pkt)
90{
91 LSQSenderState *state = dynamic_cast<LSQSenderState *>(pkt->senderState);
92 DynInstPtr inst = state->inst;
93 DPRINTF(IEW, "Writeback event [sn:%lli].\n", inst->seqNum);
94 DPRINTF(Activity, "Activity: Writeback event [sn:%lli].\n", inst->seqNum);
95
96 //iewStage->ldstQueue.removeMSHR(inst->threadNumber,inst->seqNum);
97
98 // If this is a split access, wait until all packets are received.
99 if (TheISA::HasUnalignedMemAcc && !state->complete()) {
100 delete pkt->req;
101 delete pkt;
102 return;
103 }
104
105 assert(!cpu->switchedOut());
106 if (inst->isSquashed()) {
107 iewStage->decrWb(inst->seqNum);
108 } else {
109 if (!state->noWB) {
110 if (!TheISA::HasUnalignedMemAcc || !state->isSplit ||
111 !state->isLoad) {
112 writeback(inst, pkt);
113 } else {
114 writeback(inst, state->mainPkt);
115 }
116 }
117
118 if (inst->isStore()) {
119 completeStore(state->idx);
120 }
121 }
122
123 if (TheISA::HasUnalignedMemAcc && state->isSplit && state->isLoad) {
124 delete state->mainPkt->req;
125 delete state->mainPkt;
126 }
127 delete state;
128 delete pkt->req;
129 delete pkt;
130}
131
132template <class Impl>
133LSQUnit<Impl>::LSQUnit()
134 : loads(0), stores(0), storesToWB(0), cacheBlockMask(0), stalled(false),
135 isStoreBlocked(false), isLoadBlocked(false),
136 loadBlockedHandled(false), storeInFlight(false), hasPendingPkt(false)
137{
138}
139
140template<class Impl>
141void
142LSQUnit<Impl>::init(O3CPU *cpu_ptr, IEW *iew_ptr, DerivO3CPUParams *params,
143 LSQ *lsq_ptr, unsigned maxLQEntries, unsigned maxSQEntries,
144 unsigned id)
145{
146 cpu = cpu_ptr;
147 iewStage = iew_ptr;
148
149 DPRINTF(LSQUnit, "Creating LSQUnit%i object.\n",id);
150
151 lsq = lsq_ptr;
152
153 lsqID = id;
154
155 // Add 1 for the sentinel entry (they are circular queues).
156 LQEntries = maxLQEntries + 1;
157 SQEntries = maxSQEntries + 1;
158
159 loadQueue.resize(LQEntries);
160 storeQueue.resize(SQEntries);
161
162 depCheckShift = params->LSQDepCheckShift;
163 checkLoads = params->LSQCheckLoads;
164 cachePorts = params->cachePorts;
165 needsTSO = params->needsTSO;
166
167 resetState();
168}
169
170
171template<class Impl>
172void
173LSQUnit<Impl>::resetState()
174{
175 loads = stores = storesToWB = 0;
176
177 loadHead = loadTail = 0;
178
179 storeHead = storeWBIdx = storeTail = 0;
180
181 usedPorts = 0;
182
183 retryPkt = NULL;
184 memDepViolator = NULL;
185
186 blockedLoadSeqNum = 0;
187
188 stalled = false;
189 isLoadBlocked = false;
190 loadBlockedHandled = false;
191
192 cacheBlockMask = 0;
193}
194
195template<class Impl>
196std::string
197LSQUnit<Impl>::name() const
198{
199 if (Impl::MaxThreads == 1) {
200 return iewStage->name() + ".lsq";
201 } else {
202 return iewStage->name() + ".lsq.thread" + to_string(lsqID);
203 }
204}
205
206template<class Impl>
207void
208LSQUnit<Impl>::regStats()
209{
210 lsqForwLoads
211 .name(name() + ".forwLoads")
212 .desc("Number of loads that had data forwarded from stores");
213
214 invAddrLoads
215 .name(name() + ".invAddrLoads")
216 .desc("Number of loads ignored due to an invalid address");
217
218 lsqSquashedLoads
219 .name(name() + ".squashedLoads")
220 .desc("Number of loads squashed");
221
222 lsqIgnoredResponses
223 .name(name() + ".ignoredResponses")
224 .desc("Number of memory responses ignored because the instruction is squashed");
225
226 lsqMemOrderViolation
227 .name(name() + ".memOrderViolation")
228 .desc("Number of memory ordering violations");
229
230 lsqSquashedStores
231 .name(name() + ".squashedStores")
232 .desc("Number of stores squashed");
233
234 invAddrSwpfs
235 .name(name() + ".invAddrSwpfs")
236 .desc("Number of software prefetches ignored due to an invalid address");
237
238 lsqBlockedLoads
239 .name(name() + ".blockedLoads")
240 .desc("Number of blocked loads due to partial load-store forwarding");
241
242 lsqRescheduledLoads
243 .name(name() + ".rescheduledLoads")
244 .desc("Number of loads that were rescheduled");
245
246 lsqCacheBlocked
247 .name(name() + ".cacheBlocked")
248 .desc("Number of times an access to memory failed due to the cache being blocked");
249}
250
251template<class Impl>
252void
253LSQUnit<Impl>::setDcachePort(MasterPort *dcache_port)
254{
255 dcachePort = dcache_port;
256}
257
258template<class Impl>
259void
260LSQUnit<Impl>::clearLQ()
261{
262 loadQueue.clear();
263}
264
265template<class Impl>
266void
267LSQUnit<Impl>::clearSQ()
268{
269 storeQueue.clear();
270}
271
272template<class Impl>
273void
274LSQUnit<Impl>::drainSanityCheck() const
275{
276 for (int i = 0; i < loadQueue.size(); ++i)
277 assert(!loadQueue[i]);
278
279 assert(storesToWB == 0);
280 assert(!retryPkt);
281}
282
283template<class Impl>
284void
285LSQUnit<Impl>::takeOverFrom()
286{
287 resetState();
288}
289
290template<class Impl>
291void
292LSQUnit<Impl>::resizeLQ(unsigned size)
293{
294 unsigned size_plus_sentinel = size + 1;
295 assert(size_plus_sentinel >= LQEntries);
296
297 if (size_plus_sentinel > LQEntries) {
298 while (size_plus_sentinel > loadQueue.size()) {
299 DynInstPtr dummy;
300 loadQueue.push_back(dummy);
301 LQEntries++;
302 }
303 } else {
304 LQEntries = size_plus_sentinel;
305 }
306
307}
308
309template<class Impl>
310void
311LSQUnit<Impl>::resizeSQ(unsigned size)
312{
313 unsigned size_plus_sentinel = size + 1;
314 if (size_plus_sentinel > SQEntries) {
315 while (size_plus_sentinel > storeQueue.size()) {
316 SQEntry dummy;
317 storeQueue.push_back(dummy);
318 SQEntries++;
319 }
320 } else {
321 SQEntries = size_plus_sentinel;
322 }
323}
324
325template <class Impl>
326void
327LSQUnit<Impl>::insert(DynInstPtr &inst)
328{
329 assert(inst->isMemRef());
330
331 assert(inst->isLoad() || inst->isStore());
332
333 if (inst->isLoad()) {
334 insertLoad(inst);
335 } else {
336 insertStore(inst);
337 }
338
339 inst->setInLSQ();
340}
341
342template <class Impl>
343void
344LSQUnit<Impl>::insertLoad(DynInstPtr &load_inst)
345{
346 assert((loadTail + 1) % LQEntries != loadHead);
347 assert(loads < LQEntries);
348
349 DPRINTF(LSQUnit, "Inserting load PC %s, idx:%i [sn:%lli]\n",
350 load_inst->pcState(), loadTail, load_inst->seqNum);
351
352 load_inst->lqIdx = loadTail;
353
354 if (stores == 0) {
355 load_inst->sqIdx = -1;
356 } else {
357 load_inst->sqIdx = storeTail;
358 }
359
360 loadQueue[loadTail] = load_inst;
361
362 incrLdIdx(loadTail);
363
364 ++loads;
365}
366
367template <class Impl>
368void
369LSQUnit<Impl>::insertStore(DynInstPtr &store_inst)
370{
371 // Make sure it is not full before inserting an instruction.
372 assert((storeTail + 1) % SQEntries != storeHead);
373 assert(stores < SQEntries);
374
375 DPRINTF(LSQUnit, "Inserting store PC %s, idx:%i [sn:%lli]\n",
376 store_inst->pcState(), storeTail, store_inst->seqNum);
377
378 store_inst->sqIdx = storeTail;
379 store_inst->lqIdx = loadTail;
380
381 storeQueue[storeTail] = SQEntry(store_inst);
382
383 incrStIdx(storeTail);
384
385 ++stores;
386}
387
388template <class Impl>
389typename Impl::DynInstPtr
390LSQUnit<Impl>::getMemDepViolator()
391{
392 DynInstPtr temp = memDepViolator;
393
394 memDepViolator = NULL;
395
396 return temp;
397}
398
399template <class Impl>
400unsigned
401LSQUnit<Impl>::numFreeEntries()
402{
403 unsigned free_lq_entries = LQEntries - loads;
404 unsigned free_sq_entries = SQEntries - stores;
405
406 // Both the LQ and SQ entries have an extra dummy entry to differentiate
407 // empty/full conditions. Subtract 1 from the free entries.
408 if (free_lq_entries < free_sq_entries) {
409 return free_lq_entries - 1;
410 } else {
411 return free_sq_entries - 1;
412 }
413}
414
415template <class Impl>
416void
417LSQUnit<Impl>::checkSnoop(PacketPtr pkt)
418{
419 int load_idx = loadHead;
420
421 if (!cacheBlockMask) {
422 assert(dcachePort);
423 Addr bs = dcachePort->peerBlockSize();
424
425 // Make sure we actually got a size
426 assert(bs != 0);
427
428 cacheBlockMask = ~(bs - 1);
429 }
430
431 // Unlock the cpu-local monitor when the CPU sees a snoop to a locked
432 // address. The CPU can speculatively execute a LL operation after a pending
433 // SC operation in the pipeline and that can make the cache monitor the CPU
434 // is connected to valid while it really shouldn't be.
435 for (int x = 0; x < cpu->numActiveThreads(); x++) {
436 ThreadContext *tc = cpu->getContext(x);
437 bool no_squash = cpu->thread[x]->noSquashFromTC;
438 cpu->thread[x]->noSquashFromTC = true;
439 TheISA::handleLockedSnoop(tc, pkt, cacheBlockMask);
440 cpu->thread[x]->noSquashFromTC = no_squash;
441 }
442
443 // If this is the only load in the LSQ we don't care
444 if (load_idx == loadTail)
445 return;
446 incrLdIdx(load_idx);
447
448 DPRINTF(LSQUnit, "Got snoop for address %#x\n", pkt->getAddr());
449 Addr invalidate_addr = pkt->getAddr() & cacheBlockMask;
450 while (load_idx != loadTail) {
451 DynInstPtr ld_inst = loadQueue[load_idx];
452
453 if (!ld_inst->effAddrValid() || ld_inst->uncacheable()) {
454 incrLdIdx(load_idx);
455 continue;
456 }
457
458 Addr load_addr = ld_inst->physEffAddr & cacheBlockMask;
459 DPRINTF(LSQUnit, "-- inst [sn:%lli] load_addr: %#x to pktAddr:%#x\n",
460 ld_inst->seqNum, load_addr, invalidate_addr);
461
462 if (load_addr == invalidate_addr) {
463 if (ld_inst->possibleLoadViolation()) {
464 DPRINTF(LSQUnit, "Conflicting load at addr %#x [sn:%lli]\n",
465 ld_inst->physEffAddr, pkt->getAddr(), ld_inst->seqNum);
466
467 // Mark the load for re-execution
468 ld_inst->fault = new ReExec;
469 } else {
470 // If a older load checks this and it's true
471 // then we might have missed the snoop
472 // in which case we need to invalidate to be sure
473 ld_inst->hitExternalSnoop(true);
474 }
475 }
476 incrLdIdx(load_idx);
477 }
478 return;
479}
480
481template <class Impl>
482Fault
483LSQUnit<Impl>::checkViolations(int load_idx, DynInstPtr &inst)
484{
485 Addr inst_eff_addr1 = inst->effAddr >> depCheckShift;
486 Addr inst_eff_addr2 = (inst->effAddr + inst->effSize - 1) >> depCheckShift;
487
488 /** @todo in theory you only need to check an instruction that has executed
489 * however, there isn't a good way in the pipeline at the moment to check
490 * all instructions that will execute before the store writes back. Thus,
491 * like the implementation that came before it, we're overly conservative.
492 */
493 while (load_idx != loadTail) {
494 DynInstPtr ld_inst = loadQueue[load_idx];
495 if (!ld_inst->effAddrValid() || ld_inst->uncacheable()) {
496 incrLdIdx(load_idx);
497 continue;
498 }
499
500 Addr ld_eff_addr1 = ld_inst->effAddr >> depCheckShift;
501 Addr ld_eff_addr2 =
502 (ld_inst->effAddr + ld_inst->effSize - 1) >> depCheckShift;
503
504 if (inst_eff_addr2 >= ld_eff_addr1 && inst_eff_addr1 <= ld_eff_addr2) {
505 if (inst->isLoad()) {
506 // If this load is to the same block as an external snoop
507 // invalidate that we've observed then the load needs to be
508 // squashed as it could have newer data
509 if (ld_inst->hitExternalSnoop()) {
510 if (!memDepViolator ||
511 ld_inst->seqNum < memDepViolator->seqNum) {
512 DPRINTF(LSQUnit, "Detected fault with inst [sn:%lli] "
513 "and [sn:%lli] at address %#x\n",
514 inst->seqNum, ld_inst->seqNum, ld_eff_addr1);
515 memDepViolator = ld_inst;
516
517 ++lsqMemOrderViolation;
518
519 return new GenericISA::M5PanicFault(
520 "Detected fault with inst [sn:%lli] and "
521 "[sn:%lli] at address %#x\n",
522 inst->seqNum, ld_inst->seqNum, ld_eff_addr1);
523 }
524 }
525
526 // Otherwise, mark the load has a possible load violation
527 // and if we see a snoop before it's commited, we need to squash
528 ld_inst->possibleLoadViolation(true);
529 DPRINTF(LSQUnit, "Found possible load violaiton at addr: %#x"
530 " between instructions [sn:%lli] and [sn:%lli]\n",
531 inst_eff_addr1, inst->seqNum, ld_inst->seqNum);
532 } else {
533 // A load/store incorrectly passed this store.
534 // Check if we already have a violator, or if it's newer
535 // squash and refetch.
536 if (memDepViolator && ld_inst->seqNum > memDepViolator->seqNum)
537 break;
538
539 DPRINTF(LSQUnit, "Detected fault with inst [sn:%lli] and "
540 "[sn:%lli] at address %#x\n",
541 inst->seqNum, ld_inst->seqNum, ld_eff_addr1);
542 memDepViolator = ld_inst;
543
544 ++lsqMemOrderViolation;
545
546 return new GenericISA::M5PanicFault("Detected fault with "
547 "inst [sn:%lli] and [sn:%lli] at address %#x\n",
548 inst->seqNum, ld_inst->seqNum, ld_eff_addr1);
549 }
550 }
551
552 incrLdIdx(load_idx);
553 }
554 return NoFault;
555}
556
557
558
559
560template <class Impl>
561Fault
562LSQUnit<Impl>::executeLoad(DynInstPtr &inst)
563{
564 using namespace TheISA;
565 // Execute a specific load.
566 Fault load_fault = NoFault;
567
568 DPRINTF(LSQUnit, "Executing load PC %s, [sn:%lli]\n",
569 inst->pcState(), inst->seqNum);
570
571 assert(!inst->isSquashed());
572
573 load_fault = inst->initiateAcc();
574
575 if (inst->isTranslationDelayed() &&
576 load_fault == NoFault)
577 return load_fault;
578
579 // If the instruction faulted or predicated false, then we need to send it
580 // along to commit without the instruction completing.
581 if (load_fault != NoFault || inst->readPredicate() == false) {
582 // Send this instruction to commit, also make sure iew stage
583 // realizes there is activity.
584 // Mark it as executed unless it is an uncached load that
585 // needs to hit the head of commit.
586 if (inst->readPredicate() == false)
587 inst->forwardOldRegs();
588 DPRINTF(LSQUnit, "Load [sn:%lli] not executed from %s\n",
589 inst->seqNum,
590 (load_fault != NoFault ? "fault" : "predication"));
591 if (!(inst->hasRequest() && inst->uncacheable()) ||
592 inst->isAtCommit()) {
593 inst->setExecuted();
594 }
595 iewStage->instToCommit(inst);
596 iewStage->activityThisCycle();
597 } else if (!loadBlocked()) {
598 assert(inst->effAddrValid());
599 int load_idx = inst->lqIdx;
600 incrLdIdx(load_idx);
601
602 if (checkLoads)
603 return checkViolations(load_idx, inst);
604 }
605
606 return load_fault;
607}
608
609template <class Impl>
610Fault
611LSQUnit<Impl>::executeStore(DynInstPtr &store_inst)
612{
613 using namespace TheISA;
614 // Make sure that a store exists.
615 assert(stores != 0);
616
617 int store_idx = store_inst->sqIdx;
618
619 DPRINTF(LSQUnit, "Executing store PC %s [sn:%lli]\n",
620 store_inst->pcState(), store_inst->seqNum);
621
622 assert(!store_inst->isSquashed());
623
624 // Check the recently completed loads to see if any match this store's
625 // address. If so, then we have a memory ordering violation.
626 int load_idx = store_inst->lqIdx;
627
628 Fault store_fault = store_inst->initiateAcc();
629
630 if (store_inst->isTranslationDelayed() &&
631 store_fault == NoFault)
632 return store_fault;
633
634 if (store_inst->readPredicate() == false)
635 store_inst->forwardOldRegs();
636
637 if (storeQueue[store_idx].size == 0) {
638 DPRINTF(LSQUnit,"Fault on Store PC %s, [sn:%lli], Size = 0\n",
639 store_inst->pcState(), store_inst->seqNum);
640
641 return store_fault;
642 } else if (store_inst->readPredicate() == false) {
643 DPRINTF(LSQUnit, "Store [sn:%lli] not executed from predication\n",
644 store_inst->seqNum);
645 return store_fault;
646 }
647
648 assert(store_fault == NoFault);
649
650 if (store_inst->isStoreConditional()) {
651 // Store conditionals need to set themselves as able to
652 // writeback if we haven't had a fault by here.
653 storeQueue[store_idx].canWB = true;
654
655 ++storesToWB;
656 }
657
658 return checkViolations(load_idx, store_inst);
659
660}
661
662template <class Impl>
663void
664LSQUnit<Impl>::commitLoad()
665{
666 assert(loadQueue[loadHead]);
667
668 DPRINTF(LSQUnit, "Committing head load instruction, PC %s\n",
669 loadQueue[loadHead]->pcState());
670
671 loadQueue[loadHead] = NULL;
672
673 incrLdIdx(loadHead);
674
675 --loads;
676}
677
678template <class Impl>
679void
680LSQUnit<Impl>::commitLoads(InstSeqNum &youngest_inst)
681{
682 assert(loads == 0 || loadQueue[loadHead]);
683
684 while (loads != 0 && loadQueue[loadHead]->seqNum <= youngest_inst) {
685 commitLoad();
686 }
687}
688
689template <class Impl>
690void
691LSQUnit<Impl>::commitStores(InstSeqNum &youngest_inst)
692{
693 assert(stores == 0 || storeQueue[storeHead].inst);
694
695 int store_idx = storeHead;
696
697 while (store_idx != storeTail) {
698 assert(storeQueue[store_idx].inst);
699 // Mark any stores that are now committed and have not yet
700 // been marked as able to write back.
701 if (!storeQueue[store_idx].canWB) {
702 if (storeQueue[store_idx].inst->seqNum > youngest_inst) {
703 break;
704 }
705 DPRINTF(LSQUnit, "Marking store as able to write back, PC "
706 "%s [sn:%lli]\n",
707 storeQueue[store_idx].inst->pcState(),
708 storeQueue[store_idx].inst->seqNum);
709
710 storeQueue[store_idx].canWB = true;
711
712 ++storesToWB;
713 }
714
715 incrStIdx(store_idx);
716 }
717}
718
719template <class Impl>
720void
721LSQUnit<Impl>::writebackPendingStore()
722{
723 if (hasPendingPkt) {
724 assert(pendingPkt != NULL);
725
726 // If the cache is blocked, this will store the packet for retry.
727 if (sendStore(pendingPkt)) {
728 storePostSend(pendingPkt);
729 }
730 pendingPkt = NULL;
731 hasPendingPkt = false;
732 }
733}
734
735template <class Impl>
736void
737LSQUnit<Impl>::writebackStores()
738{
739 // First writeback the second packet from any split store that didn't
740 // complete last cycle because there weren't enough cache ports available.
741 if (TheISA::HasUnalignedMemAcc) {
742 writebackPendingStore();
743 }
744
745 while (storesToWB > 0 &&
746 storeWBIdx != storeTail &&
747 storeQueue[storeWBIdx].inst &&
748 storeQueue[storeWBIdx].canWB &&
749 ((!needsTSO) || (!storeInFlight)) &&
750 usedPorts < cachePorts) {
751
752 if (isStoreBlocked || lsq->cacheBlocked()) {
753 DPRINTF(LSQUnit, "Unable to write back any more stores, cache"
754 " is blocked!\n");
755 break;
756 }
757
758 // Store didn't write any data so no need to write it back to
759 // memory.
760 if (storeQueue[storeWBIdx].size == 0) {
761 completeStore(storeWBIdx);
762
763 incrStIdx(storeWBIdx);
764
765 continue;
766 }
767
768 ++usedPorts;
769
770 if (storeQueue[storeWBIdx].inst->isDataPrefetch()) {
771 incrStIdx(storeWBIdx);
772
773 continue;
774 }
775
776 assert(storeQueue[storeWBIdx].req);
777 assert(!storeQueue[storeWBIdx].committed);
778
779 if (TheISA::HasUnalignedMemAcc && storeQueue[storeWBIdx].isSplit) {
780 assert(storeQueue[storeWBIdx].sreqLow);
781 assert(storeQueue[storeWBIdx].sreqHigh);
782 }
783
784 DynInstPtr inst = storeQueue[storeWBIdx].inst;
785
786 Request *req = storeQueue[storeWBIdx].req;
787 RequestPtr sreqLow = storeQueue[storeWBIdx].sreqLow;
788 RequestPtr sreqHigh = storeQueue[storeWBIdx].sreqHigh;
789
790 storeQueue[storeWBIdx].committed = true;
791
792 assert(!inst->memData);
793 inst->memData = new uint8_t[64];
794
795 memcpy(inst->memData, storeQueue[storeWBIdx].data, req->getSize());
796
797 MemCmd command =
798 req->isSwap() ? MemCmd::SwapReq :
799 (req->isLLSC() ? MemCmd::StoreCondReq : MemCmd::WriteReq);
800 PacketPtr data_pkt;
801 PacketPtr snd_data_pkt = NULL;
802
803 LSQSenderState *state = new LSQSenderState;
804 state->isLoad = false;
805 state->idx = storeWBIdx;
806 state->inst = inst;
807
808 if (!TheISA::HasUnalignedMemAcc || !storeQueue[storeWBIdx].isSplit) {
809
810 // Build a single data packet if the store isn't split.
811 data_pkt = new Packet(req, command);
812 data_pkt->dataStatic(inst->memData);
813 data_pkt->senderState = state;
814 } else {
815 // Create two packets if the store is split in two.
816 data_pkt = new Packet(sreqLow, command);
817 snd_data_pkt = new Packet(sreqHigh, command);
818
819 data_pkt->dataStatic(inst->memData);
820 snd_data_pkt->dataStatic(inst->memData + sreqLow->getSize());
821
822 data_pkt->senderState = state;
823 snd_data_pkt->senderState = state;
824
825 state->isSplit = true;
826 state->outstanding = 2;
827
828 // Can delete the main request now.
829 delete req;
830 req = sreqLow;
831 }
832
833 DPRINTF(LSQUnit, "D-Cache: Writing back store idx:%i PC:%s "
834 "to Addr:%#x, data:%#x [sn:%lli]\n",
835 storeWBIdx, inst->pcState(),
836 req->getPaddr(), (int)*(inst->memData),
837 inst->seqNum);
838
839 // @todo: Remove this SC hack once the memory system handles it.
840 if (inst->isStoreConditional()) {
841 assert(!storeQueue[storeWBIdx].isSplit);
842 // Disable recording the result temporarily. Writing to
843 // misc regs normally updates the result, but this is not
844 // the desired behavior when handling store conditionals.
845 inst->recordResult(false);
846 bool success = TheISA::handleLockedWrite(inst.get(), req);
847 inst->recordResult(true);
848
849 if (!success) {
850 // Instantly complete this store.
851 DPRINTF(LSQUnit, "Store conditional [sn:%lli] failed. "
852 "Instantly completing it.\n",
853 inst->seqNum);
854 WritebackEvent *wb = new WritebackEvent(inst, data_pkt, this);
855 cpu->schedule(wb, curTick() + 1);
856 if (cpu->checker) {
857 // Make sure to set the LLSC data for verification
858 // if checker is loaded
859 inst->reqToVerify->setExtraData(0);
860 inst->completeAcc(data_pkt);
861 }
862 completeStore(storeWBIdx);
863 incrStIdx(storeWBIdx);
864 continue;
865 }
866 } else {
867 // Non-store conditionals do not need a writeback.
868 state->noWB = true;
869 }
870
871 bool split =
872 TheISA::HasUnalignedMemAcc && storeQueue[storeWBIdx].isSplit;
873
874 ThreadContext *thread = cpu->tcBase(lsqID);
875
876 if (req->isMmappedIpr()) {
877 assert(!inst->isStoreConditional());
878 TheISA::handleIprWrite(thread, data_pkt);
879 delete data_pkt;
880 if (split) {
881 assert(snd_data_pkt->req->isMmappedIpr());
882 TheISA::handleIprWrite(thread, snd_data_pkt);
883 delete snd_data_pkt;
884 delete sreqLow;
885 delete sreqHigh;
886 }
887 delete state;
888 delete req;
889 completeStore(storeWBIdx);
890 incrStIdx(storeWBIdx);
891 } else if (!sendStore(data_pkt)) {
892 DPRINTF(IEW, "D-Cache became blocked when writing [sn:%lli], will"
893 "retry later\n",
894 inst->seqNum);
895
896 // Need to store the second packet, if split.
897 if (split) {
898 state->pktToSend = true;
899 state->pendingPacket = snd_data_pkt;
900 }
901 } else {
902
903 // If split, try to send the second packet too
904 if (split) {
905 assert(snd_data_pkt);
906
907 // Ensure there are enough ports to use.
908 if (usedPorts < cachePorts) {
909 ++usedPorts;
910 if (sendStore(snd_data_pkt)) {
911 storePostSend(snd_data_pkt);
912 } else {
913 DPRINTF(IEW, "D-Cache became blocked when writing"
914 " [sn:%lli] second packet, will retry later\n",
915 inst->seqNum);
916 }
917 } else {
918
919 // Store the packet for when there's free ports.
920 assert(pendingPkt == NULL);
921 pendingPkt = snd_data_pkt;
922 hasPendingPkt = true;
923 }
924 } else {
925
926 // Not a split store.
927 storePostSend(data_pkt);
928 }
929 }
930 }
931
932 // Not sure this should set it to 0.
933 usedPorts = 0;
934
935 assert(stores >= 0 && storesToWB >= 0);
936}
937
938/*template <class Impl>
939void
940LSQUnit<Impl>::removeMSHR(InstSeqNum seqNum)
941{
942 list<InstSeqNum>::iterator mshr_it = find(mshrSeqNums.begin(),
943 mshrSeqNums.end(),
944 seqNum);
945
946 if (mshr_it != mshrSeqNums.end()) {
947 mshrSeqNums.erase(mshr_it);
948 DPRINTF(LSQUnit, "Removing MSHR. count = %i\n",mshrSeqNums.size());
949 }
950}*/
951
952template <class Impl>
953void
954LSQUnit<Impl>::squash(const InstSeqNum &squashed_num)
955{
956 DPRINTF(LSQUnit, "Squashing until [sn:%lli]!"
957 "(Loads:%i Stores:%i)\n", squashed_num, loads, stores);
958
959 int load_idx = loadTail;
960 decrLdIdx(load_idx);
961
962 while (loads != 0 && loadQueue[load_idx]->seqNum > squashed_num) {
963 DPRINTF(LSQUnit,"Load Instruction PC %s squashed, "
964 "[sn:%lli]\n",
965 loadQueue[load_idx]->pcState(),
966 loadQueue[load_idx]->seqNum);
967
968 if (isStalled() && load_idx == stallingLoadIdx) {
969 stalled = false;
970 stallingStoreIsn = 0;
971 stallingLoadIdx = 0;
972 }
973
974 // Clear the smart pointer to make sure it is decremented.
975 loadQueue[load_idx]->setSquashed();
976 loadQueue[load_idx] = NULL;
977 --loads;
978
979 // Inefficient!
980 loadTail = load_idx;
981
982 decrLdIdx(load_idx);
983 ++lsqSquashedLoads;
984 }
985
986 if (isLoadBlocked) {
987 if (squashed_num < blockedLoadSeqNum) {
988 isLoadBlocked = false;
989 loadBlockedHandled = false;
990 blockedLoadSeqNum = 0;
991 }
992 }
993
994 if (memDepViolator && squashed_num < memDepViolator->seqNum) {
995 memDepViolator = NULL;
996 }
997
998 int store_idx = storeTail;
999 decrStIdx(store_idx);
1000
1001 while (stores != 0 &&
1002 storeQueue[store_idx].inst->seqNum > squashed_num) {
1003 // Instructions marked as can WB are already committed.
1004 if (storeQueue[store_idx].canWB) {
1005 break;
1006 }
1007
1008 DPRINTF(LSQUnit,"Store Instruction PC %s squashed, "
1009 "idx:%i [sn:%lli]\n",
1010 storeQueue[store_idx].inst->pcState(),
1011 store_idx, storeQueue[store_idx].inst->seqNum);
1012
1013 // I don't think this can happen. It should have been cleared
1014 // by the stalling load.
1015 if (isStalled() &&
1016 storeQueue[store_idx].inst->seqNum == stallingStoreIsn) {
1017 panic("Is stalled should have been cleared by stalling load!\n");
1018 stalled = false;
1019 stallingStoreIsn = 0;
1020 }
1021
1022 // Clear the smart pointer to make sure it is decremented.
1023 storeQueue[store_idx].inst->setSquashed();
1024 storeQueue[store_idx].inst = NULL;
1025 storeQueue[store_idx].canWB = 0;
1026
1027 // Must delete request now that it wasn't handed off to
1028 // memory. This is quite ugly. @todo: Figure out the proper
1029 // place to really handle request deletes.
1030 delete storeQueue[store_idx].req;
1031 if (TheISA::HasUnalignedMemAcc && storeQueue[store_idx].isSplit) {
1032 delete storeQueue[store_idx].sreqLow;
1033 delete storeQueue[store_idx].sreqHigh;
1034
1035 storeQueue[store_idx].sreqLow = NULL;
1036 storeQueue[store_idx].sreqHigh = NULL;
1037 }
1038
1039 storeQueue[store_idx].req = NULL;
1040 --stores;
1041
1042 // Inefficient!
1043 storeTail = store_idx;
1044
1045 decrStIdx(store_idx);
1046 ++lsqSquashedStores;
1047 }
1048}
1049
1050template <class Impl>
1051void
1052LSQUnit<Impl>::storePostSend(PacketPtr pkt)
1053{
1054 if (isStalled() &&
1055 storeQueue[storeWBIdx].inst->seqNum == stallingStoreIsn) {
1056 DPRINTF(LSQUnit, "Unstalling, stalling store [sn:%lli] "
1057 "load idx:%i\n",
1058 stallingStoreIsn, stallingLoadIdx);
1059 stalled = false;
1060 stallingStoreIsn = 0;
1061 iewStage->replayMemInst(loadQueue[stallingLoadIdx]);
1062 }
1063
1064 if (!storeQueue[storeWBIdx].inst->isStoreConditional()) {
1065 // The store is basically completed at this time. This
1066 // only works so long as the checker doesn't try to
1067 // verify the value in memory for stores.
1068 storeQueue[storeWBIdx].inst->setCompleted();
1069
1070 if (cpu->checker) {
1071 cpu->checker->verify(storeQueue[storeWBIdx].inst);
1072 }
1073 }
1074
1075 if (needsTSO) {
1076 storeInFlight = true;
1077 }
1078
1079 incrStIdx(storeWBIdx);
1080}
1081
1082template <class Impl>
1083void
1084LSQUnit<Impl>::writeback(DynInstPtr &inst, PacketPtr pkt)
1085{
1086 iewStage->wakeCPU();
1087
1088 // Squashed instructions do not need to complete their access.
1089 if (inst->isSquashed()) {
1090 iewStage->decrWb(inst->seqNum);
1091 assert(!inst->isStore());
1092 ++lsqIgnoredResponses;
1093 return;
1094 }
1095
1096 if (!inst->isExecuted()) {
1097 inst->setExecuted();
1098
1099 // Complete access to copy data to proper place.
1100 inst->completeAcc(pkt);
1101 }
1102
1103 // Need to insert instruction into queue to commit
1104 iewStage->instToCommit(inst);
1105
1106 iewStage->activityThisCycle();
1107
1108 // see if this load changed the PC
1109 iewStage->checkMisprediction(inst);
1110}
1111
1112template <class Impl>
1113void
1114LSQUnit<Impl>::completeStore(int store_idx)
1115{
1116 assert(storeQueue[store_idx].inst);
1117 storeQueue[store_idx].completed = true;
1118 --storesToWB;
1119 // A bit conservative because a store completion may not free up entries,
1120 // but hopefully avoids two store completions in one cycle from making
1121 // the CPU tick twice.
1122 cpu->wakeCPU();
1123 cpu->activityThisCycle();
1124
1125 if (store_idx == storeHead) {
1126 do {
1127 incrStIdx(storeHead);
1128
1129 --stores;
1130 } while (storeQueue[storeHead].completed &&
1131 storeHead != storeTail);
1132
1133 iewStage->updateLSQNextCycle = true;
1134 }
1135
1136 DPRINTF(LSQUnit, "Completing store [sn:%lli], idx:%i, store head "
1137 "idx:%i\n",
1138 storeQueue[store_idx].inst->seqNum, store_idx, storeHead);
1139
1140 if (isStalled() &&
1141 storeQueue[store_idx].inst->seqNum == stallingStoreIsn) {
1142 DPRINTF(LSQUnit, "Unstalling, stalling store [sn:%lli] "
1143 "load idx:%i\n",
1144 stallingStoreIsn, stallingLoadIdx);
1145 stalled = false;
1146 stallingStoreIsn = 0;
1147 iewStage->replayMemInst(loadQueue[stallingLoadIdx]);
1148 }
1149
1150 storeQueue[store_idx].inst->setCompleted();
1151
1152 if (needsTSO) {
1153 storeInFlight = false;
1154 }
1155
1156 // Tell the checker we've completed this instruction. Some stores
1157 // may get reported twice to the checker, but the checker can
1158 // handle that case.
1159 if (cpu->checker) {
1160 cpu->checker->verify(storeQueue[store_idx].inst);
1161 }
1162}
1163
1164template <class Impl>
1165bool
1166LSQUnit<Impl>::sendStore(PacketPtr data_pkt)
1167{
1168 if (!dcachePort->sendTimingReq(data_pkt)) {
1169 // Need to handle becoming blocked on a store.
1170 isStoreBlocked = true;
1171 ++lsqCacheBlocked;
1172 assert(retryPkt == NULL);
1173 retryPkt = data_pkt;
1174 lsq->setRetryTid(lsqID);
1175 return false;
1176 }
1177 return true;
1178}
1179
1180template <class Impl>
1181void
1182LSQUnit<Impl>::recvRetry()
1183{
1184 if (isStoreBlocked) {
1185 DPRINTF(LSQUnit, "Receiving retry: store blocked\n");
1186 assert(retryPkt != NULL);
1187
1188 LSQSenderState *state =
1189 dynamic_cast<LSQSenderState *>(retryPkt->senderState);
1190
1191 if (dcachePort->sendTimingReq(retryPkt)) {
1192 // Don't finish the store unless this is the last packet.
1193 if (!TheISA::HasUnalignedMemAcc || !state->pktToSend ||
1194 state->pendingPacket == retryPkt) {
1195 state->pktToSend = false;
1196 storePostSend(retryPkt);
1197 }
1198 retryPkt = NULL;
1199 isStoreBlocked = false;
1200 lsq->setRetryTid(InvalidThreadID);
1201
1202 // Send any outstanding packet.
1203 if (TheISA::HasUnalignedMemAcc && state->pktToSend) {
1204 assert(state->pendingPacket);
1205 if (sendStore(state->pendingPacket)) {
1206 storePostSend(state->pendingPacket);
1207 }
1208 }
1209 } else {
1210 // Still blocked!
1211 ++lsqCacheBlocked;
1212 lsq->setRetryTid(lsqID);
1213 }
1214 } else if (isLoadBlocked) {
1215 DPRINTF(LSQUnit, "Loads squash themselves and all younger insts, "
1216 "no need to resend packet.\n");
1217 } else {
1218 DPRINTF(LSQUnit, "Retry received but LSQ is no longer blocked.\n");
1219 }
1220}
1221
1222template <class Impl>
1223inline void
1224LSQUnit<Impl>::incrStIdx(int &store_idx) const
1225{
1226 if (++store_idx >= SQEntries)
1227 store_idx = 0;
1228}
1229
1230template <class Impl>
1231inline void
1232LSQUnit<Impl>::decrStIdx(int &store_idx) const
1233{
1234 if (--store_idx < 0)
1235 store_idx += SQEntries;
1236}
1237
1238template <class Impl>
1239inline void
1240LSQUnit<Impl>::incrLdIdx(int &load_idx) const
1241{
1242 if (++load_idx >= LQEntries)
1243 load_idx = 0;
1244}
1245
1246template <class Impl>
1247inline void
1248LSQUnit<Impl>::decrLdIdx(int &load_idx) const
1249{
1250 if (--load_idx < 0)
1251 load_idx += LQEntries;
1252}
1253
1254template <class Impl>
1255void
1256LSQUnit<Impl>::dumpInsts() const
1257{
1258 cprintf("Load store queue: Dumping instructions.\n");
1259 cprintf("Load queue size: %i\n", loads);
1260 cprintf("Load queue: ");
1261
1262 int load_idx = loadHead;
1263
1264 while (load_idx != loadTail && loadQueue[load_idx]) {
1265 const DynInstPtr &inst(loadQueue[load_idx]);
1266 cprintf("%s.[sn:%i] ", inst->pcState(), inst->seqNum);
1267
1268 incrLdIdx(load_idx);
1269 }
1270 cprintf("\n");
1271
1272 cprintf("Store queue size: %i\n", stores);
1273 cprintf("Store queue: ");
1274
1275 int store_idx = storeHead;
1276
1277 while (store_idx != storeTail && storeQueue[store_idx].inst) {
1278 const DynInstPtr &inst(storeQueue[store_idx].inst);
1279 cprintf("%s.[sn:%i] ", inst->pcState(), inst->seqNum);
1280
1281 incrStIdx(store_idx);
1282 }
1283
1284 cprintf("\n");
1285}