1/*
2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Kevin Lim
29 * Korey Sewell
30 */
31
32#include "cpu/checker/cpu.hh"
33#include "cpu/o3/lsq_unit.hh"
34#include "base/str.hh"
35#include "mem/packet.hh"
36#include "mem/request.hh"
37
38template<class Impl>
39LSQUnit<Impl>::WritebackEvent::WritebackEvent(DynInstPtr &_inst, PacketPtr _pkt,
40 LSQUnit *lsq_ptr)
41 : Event(&mainEventQueue), inst(_inst), pkt(_pkt), lsqPtr(lsq_ptr)
42{
43 this->setFlags(Event::AutoDelete);
44}
45
46template<class Impl>
47void
48LSQUnit<Impl>::WritebackEvent::process()
49{
50 if (!lsqPtr->isSwitchedOut()) {
51 lsqPtr->writeback(inst, pkt);
52 }
53 delete pkt;
54}
55
56template<class Impl>
57const char *
58LSQUnit<Impl>::WritebackEvent::description()
59{
60 return "Store writeback event";
61}
62
63template<class Impl>
64void
65LSQUnit<Impl>::completeDataAccess(PacketPtr pkt)
66{
67 LSQSenderState *state = dynamic_cast<LSQSenderState *>(pkt->senderState);
68 DynInstPtr inst = state->inst;
69 DPRINTF(IEW, "Writeback event [sn:%lli]\n", inst->seqNum);
70 DPRINTF(Activity, "Activity: Writeback event [sn:%lli]\n", inst->seqNum);
71
72 //iewStage->ldstQueue.removeMSHR(inst->threadNumber,inst->seqNum);
73
74 if (isSwitchedOut() || inst->isSquashed()) {
75 delete state;
76 delete pkt;
77 return;
78 } else {
79 if (!state->noWB) {
80 writeback(inst, pkt);
81 }
82
83 if (inst->isStore()) {
84 completeStore(state->idx);
85 }
86 }
87
88 delete state;
89 delete pkt;
90}
91
92template <class Impl>
93Tick
94LSQUnit<Impl>::DcachePort::recvAtomic(PacketPtr pkt)
95{
96 panic("O3CPU model does not work with atomic mode!");
97 return curTick;
98}
99
100template <class Impl>
101void
102LSQUnit<Impl>::DcachePort::recvFunctional(PacketPtr pkt)
103{
104 panic("O3CPU doesn't expect recvFunctional callback!");
105}
106
107template <class Impl>
108void
109LSQUnit<Impl>::DcachePort::recvStatusChange(Status status)
110{
111 if (status == RangeChange)
112 return;
113
114 panic("O3CPU doesn't expect recvStatusChange callback!");
115}
116
117template <class Impl>
118bool
119LSQUnit<Impl>::DcachePort::recvTiming(PacketPtr pkt)
120{
121 lsq->completeDataAccess(pkt);
122 return true;
123}
124
125template <class Impl>
126void
127LSQUnit<Impl>::DcachePort::recvRetry()
128{
129 lsq->recvRetry();
130}
131
132template <class Impl>
133LSQUnit<Impl>::LSQUnit()
134 : loads(0), stores(0), storesToWB(0), stalled(false),
135 isStoreBlocked(false), isLoadBlocked(false),
136 loadBlockedHandled(false)
137{
138}
139
140template<class Impl>
141void
142LSQUnit<Impl>::init(Params *params, unsigned maxLQEntries,
143 unsigned maxSQEntries, unsigned id)
144{
145 DPRINTF(LSQUnit, "Creating LSQUnit%i object.\n",id);
146
147 switchedOut = false;
148
149 lsqID = id;
150
151 // Add 1 for the sentinel entry (they are circular queues).
152 LQEntries = maxLQEntries + 1;
153 SQEntries = maxSQEntries + 1;
154
155 loadQueue.resize(LQEntries);
156 storeQueue.resize(SQEntries);
157
158 loadHead = loadTail = 0;
159
160 storeHead = storeWBIdx = storeTail = 0;
161
162 usedPorts = 0;
163 cachePorts = params->cachePorts;
164
165 mem = params->mem;
166
167 memDepViolator = NULL;
168
169 blockedLoadSeqNum = 0;
170}
171
172template<class Impl>
173void
174LSQUnit<Impl>::setCPU(FullCPU *cpu_ptr)
175{
176 cpu = cpu_ptr;
177 dcachePort = new DcachePort(cpu, this);
178
179 Port *mem_dport = mem->getPort("");
180 dcachePort->setPeer(mem_dport);
181 mem_dport->setPeer(dcachePort);
182
183 if (cpu->checker) {
184 cpu->checker->setDcachePort(dcachePort);
185 }
186}
187
188template<class Impl>
189std::string
190LSQUnit<Impl>::name() const
191{
192 if (Impl::MaxThreads == 1) {
193 return iewStage->name() + ".lsq";
194 } else {
195 return iewStage->name() + ".lsq.thread." + to_string(lsqID);
196 }
197}
198
199template<class Impl>
200void
201LSQUnit<Impl>::regStats()
202{
203 lsqForwLoads
204 .name(name() + ".forwLoads")
205 .desc("Number of loads that had data forwarded from stores");
206
207 invAddrLoads
208 .name(name() + ".invAddrLoads")
209 .desc("Number of loads ignored due to an invalid address");
210
211 lsqSquashedLoads
212 .name(name() + ".squashedLoads")
213 .desc("Number of loads squashed");
214
215 lsqIgnoredResponses
216 .name(name() + ".ignoredResponses")
217 .desc("Number of memory responses ignored because the instruction is squashed");
218
219 lsqSquashedStores
220 .name(name() + ".squashedStores")
221 .desc("Number of stores squashed");
222
223 invAddrSwpfs
224 .name(name() + ".invAddrSwpfs")
225 .desc("Number of software prefetches ignored due to an invalid address");
226
227 lsqBlockedLoads
228 .name(name() + ".blockedLoads")
229 .desc("Number of blocked loads due to partial load-store forwarding");
230
231 lsqRescheduledLoads
232 .name(name() + ".rescheduledLoads")
233 .desc("Number of loads that were rescheduled");
234
235 lsqCacheBlocked
236 .name(name() + ".cacheBlocked")
237 .desc("Number of times an access to memory failed due to the cache being blocked");
238}
239
240template<class Impl>
241void
242LSQUnit<Impl>::clearLQ()
243{
244 loadQueue.clear();
245}
246
247template<class Impl>
248void
249LSQUnit<Impl>::clearSQ()
250{
251 storeQueue.clear();
252}
253
254template<class Impl>
255void
256LSQUnit<Impl>::switchOut()
257{
258 switchedOut = true;
259 for (int i = 0; i < loadQueue.size(); ++i)
260 loadQueue[i] = NULL;
261
262 assert(storesToWB == 0);
263}
264
265template<class Impl>
266void
267LSQUnit<Impl>::takeOverFrom()
268{
269 switchedOut = false;
270 loads = stores = storesToWB = 0;
271
272 loadHead = loadTail = 0;
273
274 storeHead = storeWBIdx = storeTail = 0;
275
276 usedPorts = 0;
277
278 memDepViolator = NULL;
279
280 blockedLoadSeqNum = 0;
281
282 stalled = false;
283 isLoadBlocked = false;
284 loadBlockedHandled = false;
285}
286
287template<class Impl>
288void
289LSQUnit<Impl>::resizeLQ(unsigned size)
290{
291 unsigned size_plus_sentinel = size + 1;
292 assert(size_plus_sentinel >= LQEntries);
293
294 if (size_plus_sentinel > LQEntries) {
295 while (size_plus_sentinel > loadQueue.size()) {
296 DynInstPtr dummy;
297 loadQueue.push_back(dummy);
298 LQEntries++;
299 }
300 } else {
301 LQEntries = size_plus_sentinel;
302 }
303
304}
305
306template<class Impl>
307void
308LSQUnit<Impl>::resizeSQ(unsigned size)
309{
310 unsigned size_plus_sentinel = size + 1;
311 if (size_plus_sentinel > SQEntries) {
312 while (size_plus_sentinel > storeQueue.size()) {
313 SQEntry dummy;
314 storeQueue.push_back(dummy);
315 SQEntries++;
316 }
317 } else {
318 SQEntries = size_plus_sentinel;
319 }
320}
321
322template <class Impl>
323void
324LSQUnit<Impl>::insert(DynInstPtr &inst)
325{
326 assert(inst->isMemRef());
327
328 assert(inst->isLoad() || inst->isStore());
329
330 if (inst->isLoad()) {
331 insertLoad(inst);
332 } else {
333 insertStore(inst);
334 }
335
336 inst->setInLSQ();
337}
338
339template <class Impl>
340void
341LSQUnit<Impl>::insertLoad(DynInstPtr &load_inst)
342{
343 assert((loadTail + 1) % LQEntries != loadHead);
344 assert(loads < LQEntries);
345
346 DPRINTF(LSQUnit, "Inserting load PC %#x, idx:%i [sn:%lli]\n",
347 load_inst->readPC(), loadTail, load_inst->seqNum);
348
349 load_inst->lqIdx = loadTail;
350
351 if (stores == 0) {
352 load_inst->sqIdx = -1;
353 } else {
354 load_inst->sqIdx = storeTail;
355 }
356
357 loadQueue[loadTail] = load_inst;
358
359 incrLdIdx(loadTail);
360
361 ++loads;
362}
363
364template <class Impl>
365void
366LSQUnit<Impl>::insertStore(DynInstPtr &store_inst)
367{
368 // Make sure it is not full before inserting an instruction.
369 assert((storeTail + 1) % SQEntries != storeHead);
370 assert(stores < SQEntries);
371
372 DPRINTF(LSQUnit, "Inserting store PC %#x, idx:%i [sn:%lli]\n",
373 store_inst->readPC(), storeTail, store_inst->seqNum);
374
375 store_inst->sqIdx = storeTail;
376 store_inst->lqIdx = loadTail;
377
378 storeQueue[storeTail] = SQEntry(store_inst);
379
380 incrStIdx(storeTail);
381
382 ++stores;
383}
384
385template <class Impl>
386typename Impl::DynInstPtr
387LSQUnit<Impl>::getMemDepViolator()
388{
389 DynInstPtr temp = memDepViolator;
390
391 memDepViolator = NULL;
392
393 return temp;
394}
395
396template <class Impl>
397unsigned
398LSQUnit<Impl>::numFreeEntries()
399{
400 unsigned free_lq_entries = LQEntries - loads;
401 unsigned free_sq_entries = SQEntries - stores;
402
403 // Both the LQ and SQ entries have an extra dummy entry to differentiate
404 // empty/full conditions. Subtract 1 from the free entries.
405 if (free_lq_entries < free_sq_entries) {
406 return free_lq_entries - 1;
407 } else {
408 return free_sq_entries - 1;
409 }
410}
411
412template <class Impl>
413int
414LSQUnit<Impl>::numLoadsReady()
415{
416 int load_idx = loadHead;
417 int retval = 0;
418
419 while (load_idx != loadTail) {
420 assert(loadQueue[load_idx]);
421
422 if (loadQueue[load_idx]->readyToIssue()) {
423 ++retval;
424 }
425 }
426
427 return retval;
428}
429
430template <class Impl>
431Fault
432LSQUnit<Impl>::executeLoad(DynInstPtr &inst)
433{
434 // Execute a specific load.
435 Fault load_fault = NoFault;
436
437 DPRINTF(LSQUnit, "Executing load PC %#x, [sn:%lli]\n",
438 inst->readPC(),inst->seqNum);
439
440 load_fault = inst->initiateAcc();
441
442 // If the instruction faulted, then we need to send it along to commit
443 // without the instruction completing.
444 if (load_fault != NoFault) {
445 // Send this instruction to commit, also make sure iew stage
446 // realizes there is activity.
447 iewStage->instToCommit(inst);
448 iewStage->activityThisCycle();
449 }
450
451 return load_fault;
452}
453
454template <class Impl>
455Fault
456LSQUnit<Impl>::executeStore(DynInstPtr &store_inst)
457{
458 using namespace TheISA;
459 // Make sure that a store exists.
460 assert(stores != 0);
461
462 int store_idx = store_inst->sqIdx;
463
464 DPRINTF(LSQUnit, "Executing store PC %#x [sn:%lli]\n",
465 store_inst->readPC(), store_inst->seqNum);
466
467 // Check the recently completed loads to see if any match this store's
468 // address. If so, then we have a memory ordering violation.
469 int load_idx = store_inst->lqIdx;
470
471 Fault store_fault = store_inst->initiateAcc();
472
473 if (storeQueue[store_idx].size == 0) {
474 DPRINTF(LSQUnit,"Fault on Store PC %#x, [sn:%lli],Size = 0\n",
475 store_inst->readPC(),store_inst->seqNum);
476
477 return store_fault;
478 }
479
480 assert(store_fault == NoFault);
481
482 if (store_inst->isStoreConditional()) {
483 // Store conditionals need to set themselves as able to
484 // writeback if we haven't had a fault by here.
485 storeQueue[store_idx].canWB = true;
486
487 ++storesToWB;
488 }
489
490 if (!memDepViolator) {
491 while (load_idx != loadTail) {
492 // Really only need to check loads that have actually executed
493 // It's safe to check all loads because effAddr is set to
494 // InvalAddr when the dyn inst is created.
495
496 // @todo: For now this is extra conservative, detecting a
497 // violation if the addresses match assuming all accesses
498 // are quad word accesses.
499
500 // @todo: Fix this, magic number being used here
501 if ((loadQueue[load_idx]->effAddr >> 8) ==
502 (store_inst->effAddr >> 8)) {
503 // A load incorrectly passed this store. Squash and refetch.
504 // For now return a fault to show that it was unsuccessful.
505 memDepViolator = loadQueue[load_idx];
506
507 return genMachineCheckFault();
508 }
509
510 incrLdIdx(load_idx);
511 }
512
513 // If we've reached this point, there was no violation.
514 memDepViolator = NULL;
515 }
516
517 return store_fault;
518}
519
520template <class Impl>
521void
522LSQUnit<Impl>::commitLoad()
523{
524 assert(loadQueue[loadHead]);
525
526 DPRINTF(LSQUnit, "Committing head load instruction, PC %#x\n",
527 loadQueue[loadHead]->readPC());
528
529 loadQueue[loadHead] = NULL;
530
531 incrLdIdx(loadHead);
532
533 --loads;
534}
535
536template <class Impl>
537void
538LSQUnit<Impl>::commitLoads(InstSeqNum &youngest_inst)
539{
540 assert(loads == 0 || loadQueue[loadHead]);
541
542 while (loads != 0 && loadQueue[loadHead]->seqNum <= youngest_inst) {
543 commitLoad();
544 }
545}
546
547template <class Impl>
548void
549LSQUnit<Impl>::commitStores(InstSeqNum &youngest_inst)
550{
551 assert(stores == 0 || storeQueue[storeHead].inst);
552
553 int store_idx = storeHead;
554
555 while (store_idx != storeTail) {
556 assert(storeQueue[store_idx].inst);
557 // Mark any stores that are now committed and have not yet
558 // been marked as able to write back.
559 if (!storeQueue[store_idx].canWB) {
560 if (storeQueue[store_idx].inst->seqNum > youngest_inst) {
561 break;
562 }
563 DPRINTF(LSQUnit, "Marking store as able to write back, PC "
564 "%#x [sn:%lli]\n",
565 storeQueue[store_idx].inst->readPC(),
566 storeQueue[store_idx].inst->seqNum);
567
568 storeQueue[store_idx].canWB = true;
569
570 ++storesToWB;
571 }
572
573 incrStIdx(store_idx);
574 }
575}
576
577template <class Impl>
578void
579LSQUnit<Impl>::writebackStores()
580{
581 while (storesToWB > 0 &&
582 storeWBIdx != storeTail &&
583 storeQueue[storeWBIdx].inst &&
584 storeQueue[storeWBIdx].canWB &&
585 usedPorts < cachePorts) {
586
587 if (isStoreBlocked) {
588 DPRINTF(LSQUnit, "Unable to write back any more stores, cache"
589 " is blocked!\n");
590 break;
591 }
592
593 // Store didn't write any data so no need to write it back to
594 // memory.
595 if (storeQueue[storeWBIdx].size == 0) {
596 completeStore(storeWBIdx);
597
598 incrStIdx(storeWBIdx);
599
600 continue;
601 }
602
603 ++usedPorts;
604
605 if (storeQueue[storeWBIdx].inst->isDataPrefetch()) {
606 incrStIdx(storeWBIdx);
607
608 continue;
609 }
610
611 assert(storeQueue[storeWBIdx].req);
612 assert(!storeQueue[storeWBIdx].committed);
613
614 DynInstPtr inst = storeQueue[storeWBIdx].inst;
615
616 Request *req = storeQueue[storeWBIdx].req;
617 storeQueue[storeWBIdx].committed = true;
618
619 assert(!inst->memData);
620 inst->memData = new uint8_t[64];
621 memcpy(inst->memData, (uint8_t *)&storeQueue[storeWBIdx].data,
622 req->getSize());
623
624 PacketPtr data_pkt = new Packet(req, Packet::WriteReq, Packet::Broadcast);
625 data_pkt->dataStatic(inst->memData);
626
627 LSQSenderState *state = new LSQSenderState;
628 state->isLoad = false;
629 state->idx = storeWBIdx;
630 state->inst = inst;
631 data_pkt->senderState = state;
632
633 DPRINTF(LSQUnit, "D-Cache: Writing back store idx:%i PC:%#x "
634 "to Addr:%#x, data:%#x [sn:%lli]\n",
635 storeWBIdx, storeQueue[storeWBIdx].inst->readPC(),
636 req->getPaddr(), *(inst->memData),
637 storeQueue[storeWBIdx].inst->seqNum);
638
639 // @todo: Remove this SC hack once the memory system handles it.
640 if (req->getFlags() & LOCKED) {
641 if (req->getFlags() & UNCACHEABLE) {
642 req->setScResult(2);
643 } else {
644 if (cpu->lockFlag) {
645 req->setScResult(1);
646 } else {
647 req->setScResult(0);
648 // Hack: Instantly complete this store.
649 completeDataAccess(data_pkt);
650 incrStIdx(storeWBIdx);
651 continue;
652 }
653 }
654 } else {
655 // Non-store conditionals do not need a writeback.
656 state->noWB = true;
657 }
658
659 if (!dcachePort->sendTiming(data_pkt)) {
660 // Need to handle becoming blocked on a store.
661 isStoreBlocked = true;
662 ++lsqCacheBlocked;
663 assert(retryPkt == NULL);
664 retryPkt = data_pkt;
665 } else {
666 storePostSend(data_pkt);
667 }
668 }
669
670 // Not sure this should set it to 0.
671 usedPorts = 0;
672
673 assert(stores >= 0 && storesToWB >= 0);
674}
675
676/*template <class Impl>
677void
678LSQUnit<Impl>::removeMSHR(InstSeqNum seqNum)
679{
680 list<InstSeqNum>::iterator mshr_it = find(mshrSeqNums.begin(),
681 mshrSeqNums.end(),
682 seqNum);
683
684 if (mshr_it != mshrSeqNums.end()) {
685 mshrSeqNums.erase(mshr_it);
686 DPRINTF(LSQUnit, "Removing MSHR. count = %i\n",mshrSeqNums.size());
687 }
688}*/
689
690template <class Impl>
691void
692LSQUnit<Impl>::squash(const InstSeqNum &squashed_num)
693{
694 DPRINTF(LSQUnit, "Squashing until [sn:%lli]!"
695 "(Loads:%i Stores:%i)\n", squashed_num, loads, stores);
696
697 int load_idx = loadTail;
698 decrLdIdx(load_idx);
699
700 while (loads != 0 && loadQueue[load_idx]->seqNum > squashed_num) {
701 DPRINTF(LSQUnit,"Load Instruction PC %#x squashed, "
702 "[sn:%lli]\n",
703 loadQueue[load_idx]->readPC(),
704 loadQueue[load_idx]->seqNum);
705
706 if (isStalled() && load_idx == stallingLoadIdx) {
707 stalled = false;
708 stallingStoreIsn = 0;
709 stallingLoadIdx = 0;
710 }
711
712 // Clear the smart pointer to make sure it is decremented.
713 loadQueue[load_idx]->squashed = true;
714 loadQueue[load_idx] = NULL;
715 --loads;
716
717 // Inefficient!
718 loadTail = load_idx;
719
720 decrLdIdx(load_idx);
721 ++lsqSquashedLoads;
722 }
723
724 if (isLoadBlocked) {
725 if (squashed_num < blockedLoadSeqNum) {
726 isLoadBlocked = false;
727 loadBlockedHandled = false;
728 blockedLoadSeqNum = 0;
729 }
730 }
731
732 int store_idx = storeTail;
733 decrStIdx(store_idx);
734
735 while (stores != 0 &&
736 storeQueue[store_idx].inst->seqNum > squashed_num) {
737 // Instructions marked as can WB are already committed.
738 if (storeQueue[store_idx].canWB) {
739 break;
740 }
741
742 DPRINTF(LSQUnit,"Store Instruction PC %#x squashed, "
743 "idx:%i [sn:%lli]\n",
744 storeQueue[store_idx].inst->readPC(),
745 store_idx, storeQueue[store_idx].inst->seqNum);
746
747 // I don't think this can happen. It should have been cleared
748 // by the stalling load.
749 if (isStalled() &&
750 storeQueue[store_idx].inst->seqNum == stallingStoreIsn) {
751 panic("Is stalled should have been cleared by stalling load!\n");
752 stalled = false;
753 stallingStoreIsn = 0;
754 }
755
756 // Clear the smart pointer to make sure it is decremented.
757 storeQueue[store_idx].inst->squashed = true;
758 storeQueue[store_idx].inst = NULL;
759 storeQueue[store_idx].canWB = 0;
760
761 storeQueue[store_idx].req = NULL;
762 --stores;
763
764 // Inefficient!
765 storeTail = store_idx;
766
767 decrStIdx(store_idx);
768 ++lsqSquashedStores;
769 }
770}
771
772template <class Impl>
773void
774LSQUnit<Impl>::storePostSend(Packet *pkt)
775{
776 if (isStalled() &&
777 storeQueue[storeWBIdx].inst->seqNum == stallingStoreIsn) {
778 DPRINTF(LSQUnit, "Unstalling, stalling store [sn:%lli] "
779 "load idx:%i\n",
780 stallingStoreIsn, stallingLoadIdx);
781 stalled = false;
782 stallingStoreIsn = 0;
783 iewStage->replayMemInst(loadQueue[stallingLoadIdx]);
784 }
785
786 if (!storeQueue[storeWBIdx].inst->isStoreConditional()) {
787 // The store is basically completed at this time. This
788 // only works so long as the checker doesn't try to
789 // verify the value in memory for stores.
790 storeQueue[storeWBIdx].inst->setCompleted();
791 if (cpu->checker) {
792 cpu->checker->tick(storeQueue[storeWBIdx].inst);
793 }
794 }
795
796 if (pkt->result != Packet::Success) {
797 DPRINTF(LSQUnit,"D-Cache Write Miss on idx:%i!\n",
798 storeWBIdx);
799
800 DPRINTF(Activity, "Active st accessing mem miss [sn:%lli]\n",
801 storeQueue[storeWBIdx].inst->seqNum);
802
803 //mshrSeqNums.push_back(storeQueue[storeWBIdx].inst->seqNum);
804
805 //DPRINTF(LSQUnit, "Added MSHR. count = %i\n",mshrSeqNums.size());
806
807 // @todo: Increment stat here.
808 } else {
809 DPRINTF(LSQUnit,"D-Cache: Write Hit on idx:%i !\n",
810 storeWBIdx);
811
812 DPRINTF(Activity, "Active st accessing mem hit [sn:%lli]\n",
813 storeQueue[storeWBIdx].inst->seqNum);
814 }
815
816 incrStIdx(storeWBIdx);
817}
818
819template <class Impl>
820void
821LSQUnit<Impl>::writeback(DynInstPtr &inst, PacketPtr pkt)
822{
823 iewStage->wakeCPU();
824
825 // Squashed instructions do not need to complete their access.
826 if (inst->isSquashed()) {
827 assert(!inst->isStore());
828 ++lsqIgnoredResponses;
829 return;
830 }
831
832 if (!inst->isExecuted()) {
833 inst->setExecuted();
834
835 // Complete access to copy data to proper place.
836 inst->completeAcc(pkt);
837 }
838
839 // Need to insert instruction into queue to commit
840 iewStage->instToCommit(inst);
841
842 iewStage->activityThisCycle();
843}
844
845template <class Impl>
846void
847LSQUnit<Impl>::completeStore(int store_idx)
848{
849 assert(storeQueue[store_idx].inst);
850 storeQueue[store_idx].completed = true;
851 --storesToWB;
852 // A bit conservative because a store completion may not free up entries,
853 // but hopefully avoids two store completions in one cycle from making
854 // the CPU tick twice.
855 cpu->activityThisCycle();
856
857 if (store_idx == storeHead) {
858 do {
859 incrStIdx(storeHead);
860
861 --stores;
862 } while (storeQueue[storeHead].completed &&
863 storeHead != storeTail);
864
865 iewStage->updateLSQNextCycle = true;
866 }
867
868 DPRINTF(LSQUnit, "Completing store [sn:%lli], idx:%i, store head "
869 "idx:%i\n",
870 storeQueue[store_idx].inst->seqNum, store_idx, storeHead);
871
872 if (isStalled() &&
873 storeQueue[store_idx].inst->seqNum == stallingStoreIsn) {
874 DPRINTF(LSQUnit, "Unstalling, stalling store [sn:%lli] "
875 "load idx:%i\n",
876 stallingStoreIsn, stallingLoadIdx);
877 stalled = false;
878 stallingStoreIsn = 0;
879 iewStage->replayMemInst(loadQueue[stallingLoadIdx]);
880 }
881
882 storeQueue[store_idx].inst->setCompleted();
883
884 // Tell the checker we've completed this instruction. Some stores
885 // may get reported twice to the checker, but the checker can
886 // handle that case.
887 if (cpu->checker) {
888 cpu->checker->tick(storeQueue[store_idx].inst);
889 }
890}
891
892template <class Impl>
893void
894LSQUnit<Impl>::recvRetry()
895{
896 if (isStoreBlocked) {
897 assert(retryPkt != NULL);
898
899 if (dcachePort->sendTiming(retryPkt)) {
900 storePostSend(retryPkt);
901 retryPkt = NULL;
902 isStoreBlocked = false;
903 } else {
904 // Still blocked!
905 ++lsqCacheBlocked;
906 }
907 } else if (isLoadBlocked) {
908 DPRINTF(LSQUnit, "Loads squash themselves and all younger insts, "
909 "no need to resend packet.\n");
910 } else {
911 DPRINTF(LSQUnit, "Retry received but LSQ is no longer blocked.\n");
912 }
913}
914
915template <class Impl>
916inline void
917LSQUnit<Impl>::incrStIdx(int &store_idx)
918{
919 if (++store_idx >= SQEntries)
920 store_idx = 0;
921}
922
923template <class Impl>
924inline void
925LSQUnit<Impl>::decrStIdx(int &store_idx)
926{
927 if (--store_idx < 0)
928 store_idx += SQEntries;
929}
930
931template <class Impl>
932inline void
933LSQUnit<Impl>::incrLdIdx(int &load_idx)
934{
935 if (++load_idx >= LQEntries)
936 load_idx = 0;
937}
938
939template <class Impl>
940inline void
941LSQUnit<Impl>::decrLdIdx(int &load_idx)
942{
943 if (--load_idx < 0)
944 load_idx += LQEntries;
945}
946
947template <class Impl>
948void
949LSQUnit<Impl>::dumpInsts()
950{
951 cprintf("Load store queue: Dumping instructions.\n");
952 cprintf("Load queue size: %i\n", loads);
953 cprintf("Load queue: ");
954
955 int load_idx = loadHead;
956
957 while (load_idx != loadTail && loadQueue[load_idx]) {
958 cprintf("%#x ", loadQueue[load_idx]->readPC());
959
960 incrLdIdx(load_idx);
961 }
962
963 cprintf("Store queue size: %i\n", stores);
964 cprintf("Store queue: ");
965
966 int store_idx = storeHead;
967
968 while (store_idx != storeTail && storeQueue[store_idx].inst) {
969 cprintf("%#x ", storeQueue[store_idx].inst->readPC());
970
971 incrStIdx(store_idx);
972 }
973
974 cprintf("\n");
975}
2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Kevin Lim
29 * Korey Sewell
30 */
31
32#include "cpu/checker/cpu.hh"
33#include "cpu/o3/lsq_unit.hh"
34#include "base/str.hh"
35#include "mem/packet.hh"
36#include "mem/request.hh"
37
38template<class Impl>
39LSQUnit<Impl>::WritebackEvent::WritebackEvent(DynInstPtr &_inst, PacketPtr _pkt,
40 LSQUnit *lsq_ptr)
41 : Event(&mainEventQueue), inst(_inst), pkt(_pkt), lsqPtr(lsq_ptr)
42{
43 this->setFlags(Event::AutoDelete);
44}
45
46template<class Impl>
47void
48LSQUnit<Impl>::WritebackEvent::process()
49{
50 if (!lsqPtr->isSwitchedOut()) {
51 lsqPtr->writeback(inst, pkt);
52 }
53 delete pkt;
54}
55
56template<class Impl>
57const char *
58LSQUnit<Impl>::WritebackEvent::description()
59{
60 return "Store writeback event";
61}
62
63template<class Impl>
64void
65LSQUnit<Impl>::completeDataAccess(PacketPtr pkt)
66{
67 LSQSenderState *state = dynamic_cast<LSQSenderState *>(pkt->senderState);
68 DynInstPtr inst = state->inst;
69 DPRINTF(IEW, "Writeback event [sn:%lli]\n", inst->seqNum);
70 DPRINTF(Activity, "Activity: Writeback event [sn:%lli]\n", inst->seqNum);
71
72 //iewStage->ldstQueue.removeMSHR(inst->threadNumber,inst->seqNum);
73
74 if (isSwitchedOut() || inst->isSquashed()) {
75 delete state;
76 delete pkt;
77 return;
78 } else {
79 if (!state->noWB) {
80 writeback(inst, pkt);
81 }
82
83 if (inst->isStore()) {
84 completeStore(state->idx);
85 }
86 }
87
88 delete state;
89 delete pkt;
90}
91
92template <class Impl>
93Tick
94LSQUnit<Impl>::DcachePort::recvAtomic(PacketPtr pkt)
95{
96 panic("O3CPU model does not work with atomic mode!");
97 return curTick;
98}
99
100template <class Impl>
101void
102LSQUnit<Impl>::DcachePort::recvFunctional(PacketPtr pkt)
103{
104 panic("O3CPU doesn't expect recvFunctional callback!");
105}
106
107template <class Impl>
108void
109LSQUnit<Impl>::DcachePort::recvStatusChange(Status status)
110{
111 if (status == RangeChange)
112 return;
113
114 panic("O3CPU doesn't expect recvStatusChange callback!");
115}
116
117template <class Impl>
118bool
119LSQUnit<Impl>::DcachePort::recvTiming(PacketPtr pkt)
120{
121 lsq->completeDataAccess(pkt);
122 return true;
123}
124
125template <class Impl>
126void
127LSQUnit<Impl>::DcachePort::recvRetry()
128{
129 lsq->recvRetry();
130}
131
132template <class Impl>
133LSQUnit<Impl>::LSQUnit()
134 : loads(0), stores(0), storesToWB(0), stalled(false),
135 isStoreBlocked(false), isLoadBlocked(false),
136 loadBlockedHandled(false)
137{
138}
139
140template<class Impl>
141void
142LSQUnit<Impl>::init(Params *params, unsigned maxLQEntries,
143 unsigned maxSQEntries, unsigned id)
144{
145 DPRINTF(LSQUnit, "Creating LSQUnit%i object.\n",id);
146
147 switchedOut = false;
148
149 lsqID = id;
150
151 // Add 1 for the sentinel entry (they are circular queues).
152 LQEntries = maxLQEntries + 1;
153 SQEntries = maxSQEntries + 1;
154
155 loadQueue.resize(LQEntries);
156 storeQueue.resize(SQEntries);
157
158 loadHead = loadTail = 0;
159
160 storeHead = storeWBIdx = storeTail = 0;
161
162 usedPorts = 0;
163 cachePorts = params->cachePorts;
164
165 mem = params->mem;
166
167 memDepViolator = NULL;
168
169 blockedLoadSeqNum = 0;
170}
171
172template<class Impl>
173void
174LSQUnit<Impl>::setCPU(FullCPU *cpu_ptr)
175{
176 cpu = cpu_ptr;
177 dcachePort = new DcachePort(cpu, this);
178
179 Port *mem_dport = mem->getPort("");
180 dcachePort->setPeer(mem_dport);
181 mem_dport->setPeer(dcachePort);
182
183 if (cpu->checker) {
184 cpu->checker->setDcachePort(dcachePort);
185 }
186}
187
188template<class Impl>
189std::string
190LSQUnit<Impl>::name() const
191{
192 if (Impl::MaxThreads == 1) {
193 return iewStage->name() + ".lsq";
194 } else {
195 return iewStage->name() + ".lsq.thread." + to_string(lsqID);
196 }
197}
198
199template<class Impl>
200void
201LSQUnit<Impl>::regStats()
202{
203 lsqForwLoads
204 .name(name() + ".forwLoads")
205 .desc("Number of loads that had data forwarded from stores");
206
207 invAddrLoads
208 .name(name() + ".invAddrLoads")
209 .desc("Number of loads ignored due to an invalid address");
210
211 lsqSquashedLoads
212 .name(name() + ".squashedLoads")
213 .desc("Number of loads squashed");
214
215 lsqIgnoredResponses
216 .name(name() + ".ignoredResponses")
217 .desc("Number of memory responses ignored because the instruction is squashed");
218
219 lsqSquashedStores
220 .name(name() + ".squashedStores")
221 .desc("Number of stores squashed");
222
223 invAddrSwpfs
224 .name(name() + ".invAddrSwpfs")
225 .desc("Number of software prefetches ignored due to an invalid address");
226
227 lsqBlockedLoads
228 .name(name() + ".blockedLoads")
229 .desc("Number of blocked loads due to partial load-store forwarding");
230
231 lsqRescheduledLoads
232 .name(name() + ".rescheduledLoads")
233 .desc("Number of loads that were rescheduled");
234
235 lsqCacheBlocked
236 .name(name() + ".cacheBlocked")
237 .desc("Number of times an access to memory failed due to the cache being blocked");
238}
239
240template<class Impl>
241void
242LSQUnit<Impl>::clearLQ()
243{
244 loadQueue.clear();
245}
246
247template<class Impl>
248void
249LSQUnit<Impl>::clearSQ()
250{
251 storeQueue.clear();
252}
253
254template<class Impl>
255void
256LSQUnit<Impl>::switchOut()
257{
258 switchedOut = true;
259 for (int i = 0; i < loadQueue.size(); ++i)
260 loadQueue[i] = NULL;
261
262 assert(storesToWB == 0);
263}
264
265template<class Impl>
266void
267LSQUnit<Impl>::takeOverFrom()
268{
269 switchedOut = false;
270 loads = stores = storesToWB = 0;
271
272 loadHead = loadTail = 0;
273
274 storeHead = storeWBIdx = storeTail = 0;
275
276 usedPorts = 0;
277
278 memDepViolator = NULL;
279
280 blockedLoadSeqNum = 0;
281
282 stalled = false;
283 isLoadBlocked = false;
284 loadBlockedHandled = false;
285}
286
287template<class Impl>
288void
289LSQUnit<Impl>::resizeLQ(unsigned size)
290{
291 unsigned size_plus_sentinel = size + 1;
292 assert(size_plus_sentinel >= LQEntries);
293
294 if (size_plus_sentinel > LQEntries) {
295 while (size_plus_sentinel > loadQueue.size()) {
296 DynInstPtr dummy;
297 loadQueue.push_back(dummy);
298 LQEntries++;
299 }
300 } else {
301 LQEntries = size_plus_sentinel;
302 }
303
304}
305
306template<class Impl>
307void
308LSQUnit<Impl>::resizeSQ(unsigned size)
309{
310 unsigned size_plus_sentinel = size + 1;
311 if (size_plus_sentinel > SQEntries) {
312 while (size_plus_sentinel > storeQueue.size()) {
313 SQEntry dummy;
314 storeQueue.push_back(dummy);
315 SQEntries++;
316 }
317 } else {
318 SQEntries = size_plus_sentinel;
319 }
320}
321
322template <class Impl>
323void
324LSQUnit<Impl>::insert(DynInstPtr &inst)
325{
326 assert(inst->isMemRef());
327
328 assert(inst->isLoad() || inst->isStore());
329
330 if (inst->isLoad()) {
331 insertLoad(inst);
332 } else {
333 insertStore(inst);
334 }
335
336 inst->setInLSQ();
337}
338
339template <class Impl>
340void
341LSQUnit<Impl>::insertLoad(DynInstPtr &load_inst)
342{
343 assert((loadTail + 1) % LQEntries != loadHead);
344 assert(loads < LQEntries);
345
346 DPRINTF(LSQUnit, "Inserting load PC %#x, idx:%i [sn:%lli]\n",
347 load_inst->readPC(), loadTail, load_inst->seqNum);
348
349 load_inst->lqIdx = loadTail;
350
351 if (stores == 0) {
352 load_inst->sqIdx = -1;
353 } else {
354 load_inst->sqIdx = storeTail;
355 }
356
357 loadQueue[loadTail] = load_inst;
358
359 incrLdIdx(loadTail);
360
361 ++loads;
362}
363
364template <class Impl>
365void
366LSQUnit<Impl>::insertStore(DynInstPtr &store_inst)
367{
368 // Make sure it is not full before inserting an instruction.
369 assert((storeTail + 1) % SQEntries != storeHead);
370 assert(stores < SQEntries);
371
372 DPRINTF(LSQUnit, "Inserting store PC %#x, idx:%i [sn:%lli]\n",
373 store_inst->readPC(), storeTail, store_inst->seqNum);
374
375 store_inst->sqIdx = storeTail;
376 store_inst->lqIdx = loadTail;
377
378 storeQueue[storeTail] = SQEntry(store_inst);
379
380 incrStIdx(storeTail);
381
382 ++stores;
383}
384
385template <class Impl>
386typename Impl::DynInstPtr
387LSQUnit<Impl>::getMemDepViolator()
388{
389 DynInstPtr temp = memDepViolator;
390
391 memDepViolator = NULL;
392
393 return temp;
394}
395
396template <class Impl>
397unsigned
398LSQUnit<Impl>::numFreeEntries()
399{
400 unsigned free_lq_entries = LQEntries - loads;
401 unsigned free_sq_entries = SQEntries - stores;
402
403 // Both the LQ and SQ entries have an extra dummy entry to differentiate
404 // empty/full conditions. Subtract 1 from the free entries.
405 if (free_lq_entries < free_sq_entries) {
406 return free_lq_entries - 1;
407 } else {
408 return free_sq_entries - 1;
409 }
410}
411
412template <class Impl>
413int
414LSQUnit<Impl>::numLoadsReady()
415{
416 int load_idx = loadHead;
417 int retval = 0;
418
419 while (load_idx != loadTail) {
420 assert(loadQueue[load_idx]);
421
422 if (loadQueue[load_idx]->readyToIssue()) {
423 ++retval;
424 }
425 }
426
427 return retval;
428}
429
430template <class Impl>
431Fault
432LSQUnit<Impl>::executeLoad(DynInstPtr &inst)
433{
434 // Execute a specific load.
435 Fault load_fault = NoFault;
436
437 DPRINTF(LSQUnit, "Executing load PC %#x, [sn:%lli]\n",
438 inst->readPC(),inst->seqNum);
439
440 load_fault = inst->initiateAcc();
441
442 // If the instruction faulted, then we need to send it along to commit
443 // without the instruction completing.
444 if (load_fault != NoFault) {
445 // Send this instruction to commit, also make sure iew stage
446 // realizes there is activity.
447 iewStage->instToCommit(inst);
448 iewStage->activityThisCycle();
449 }
450
451 return load_fault;
452}
453
454template <class Impl>
455Fault
456LSQUnit<Impl>::executeStore(DynInstPtr &store_inst)
457{
458 using namespace TheISA;
459 // Make sure that a store exists.
460 assert(stores != 0);
461
462 int store_idx = store_inst->sqIdx;
463
464 DPRINTF(LSQUnit, "Executing store PC %#x [sn:%lli]\n",
465 store_inst->readPC(), store_inst->seqNum);
466
467 // Check the recently completed loads to see if any match this store's
468 // address. If so, then we have a memory ordering violation.
469 int load_idx = store_inst->lqIdx;
470
471 Fault store_fault = store_inst->initiateAcc();
472
473 if (storeQueue[store_idx].size == 0) {
474 DPRINTF(LSQUnit,"Fault on Store PC %#x, [sn:%lli],Size = 0\n",
475 store_inst->readPC(),store_inst->seqNum);
476
477 return store_fault;
478 }
479
480 assert(store_fault == NoFault);
481
482 if (store_inst->isStoreConditional()) {
483 // Store conditionals need to set themselves as able to
484 // writeback if we haven't had a fault by here.
485 storeQueue[store_idx].canWB = true;
486
487 ++storesToWB;
488 }
489
490 if (!memDepViolator) {
491 while (load_idx != loadTail) {
492 // Really only need to check loads that have actually executed
493 // It's safe to check all loads because effAddr is set to
494 // InvalAddr when the dyn inst is created.
495
496 // @todo: For now this is extra conservative, detecting a
497 // violation if the addresses match assuming all accesses
498 // are quad word accesses.
499
500 // @todo: Fix this, magic number being used here
501 if ((loadQueue[load_idx]->effAddr >> 8) ==
502 (store_inst->effAddr >> 8)) {
503 // A load incorrectly passed this store. Squash and refetch.
504 // For now return a fault to show that it was unsuccessful.
505 memDepViolator = loadQueue[load_idx];
506
507 return genMachineCheckFault();
508 }
509
510 incrLdIdx(load_idx);
511 }
512
513 // If we've reached this point, there was no violation.
514 memDepViolator = NULL;
515 }
516
517 return store_fault;
518}
519
520template <class Impl>
521void
522LSQUnit<Impl>::commitLoad()
523{
524 assert(loadQueue[loadHead]);
525
526 DPRINTF(LSQUnit, "Committing head load instruction, PC %#x\n",
527 loadQueue[loadHead]->readPC());
528
529 loadQueue[loadHead] = NULL;
530
531 incrLdIdx(loadHead);
532
533 --loads;
534}
535
536template <class Impl>
537void
538LSQUnit<Impl>::commitLoads(InstSeqNum &youngest_inst)
539{
540 assert(loads == 0 || loadQueue[loadHead]);
541
542 while (loads != 0 && loadQueue[loadHead]->seqNum <= youngest_inst) {
543 commitLoad();
544 }
545}
546
547template <class Impl>
548void
549LSQUnit<Impl>::commitStores(InstSeqNum &youngest_inst)
550{
551 assert(stores == 0 || storeQueue[storeHead].inst);
552
553 int store_idx = storeHead;
554
555 while (store_idx != storeTail) {
556 assert(storeQueue[store_idx].inst);
557 // Mark any stores that are now committed and have not yet
558 // been marked as able to write back.
559 if (!storeQueue[store_idx].canWB) {
560 if (storeQueue[store_idx].inst->seqNum > youngest_inst) {
561 break;
562 }
563 DPRINTF(LSQUnit, "Marking store as able to write back, PC "
564 "%#x [sn:%lli]\n",
565 storeQueue[store_idx].inst->readPC(),
566 storeQueue[store_idx].inst->seqNum);
567
568 storeQueue[store_idx].canWB = true;
569
570 ++storesToWB;
571 }
572
573 incrStIdx(store_idx);
574 }
575}
576
577template <class Impl>
578void
579LSQUnit<Impl>::writebackStores()
580{
581 while (storesToWB > 0 &&
582 storeWBIdx != storeTail &&
583 storeQueue[storeWBIdx].inst &&
584 storeQueue[storeWBIdx].canWB &&
585 usedPorts < cachePorts) {
586
587 if (isStoreBlocked) {
588 DPRINTF(LSQUnit, "Unable to write back any more stores, cache"
589 " is blocked!\n");
590 break;
591 }
592
593 // Store didn't write any data so no need to write it back to
594 // memory.
595 if (storeQueue[storeWBIdx].size == 0) {
596 completeStore(storeWBIdx);
597
598 incrStIdx(storeWBIdx);
599
600 continue;
601 }
602
603 ++usedPorts;
604
605 if (storeQueue[storeWBIdx].inst->isDataPrefetch()) {
606 incrStIdx(storeWBIdx);
607
608 continue;
609 }
610
611 assert(storeQueue[storeWBIdx].req);
612 assert(!storeQueue[storeWBIdx].committed);
613
614 DynInstPtr inst = storeQueue[storeWBIdx].inst;
615
616 Request *req = storeQueue[storeWBIdx].req;
617 storeQueue[storeWBIdx].committed = true;
618
619 assert(!inst->memData);
620 inst->memData = new uint8_t[64];
621 memcpy(inst->memData, (uint8_t *)&storeQueue[storeWBIdx].data,
622 req->getSize());
623
624 PacketPtr data_pkt = new Packet(req, Packet::WriteReq, Packet::Broadcast);
625 data_pkt->dataStatic(inst->memData);
626
627 LSQSenderState *state = new LSQSenderState;
628 state->isLoad = false;
629 state->idx = storeWBIdx;
630 state->inst = inst;
631 data_pkt->senderState = state;
632
633 DPRINTF(LSQUnit, "D-Cache: Writing back store idx:%i PC:%#x "
634 "to Addr:%#x, data:%#x [sn:%lli]\n",
635 storeWBIdx, storeQueue[storeWBIdx].inst->readPC(),
636 req->getPaddr(), *(inst->memData),
637 storeQueue[storeWBIdx].inst->seqNum);
638
639 // @todo: Remove this SC hack once the memory system handles it.
640 if (req->getFlags() & LOCKED) {
641 if (req->getFlags() & UNCACHEABLE) {
642 req->setScResult(2);
643 } else {
644 if (cpu->lockFlag) {
645 req->setScResult(1);
646 } else {
647 req->setScResult(0);
648 // Hack: Instantly complete this store.
649 completeDataAccess(data_pkt);
650 incrStIdx(storeWBIdx);
651 continue;
652 }
653 }
654 } else {
655 // Non-store conditionals do not need a writeback.
656 state->noWB = true;
657 }
658
659 if (!dcachePort->sendTiming(data_pkt)) {
660 // Need to handle becoming blocked on a store.
661 isStoreBlocked = true;
662 ++lsqCacheBlocked;
663 assert(retryPkt == NULL);
664 retryPkt = data_pkt;
665 } else {
666 storePostSend(data_pkt);
667 }
668 }
669
670 // Not sure this should set it to 0.
671 usedPorts = 0;
672
673 assert(stores >= 0 && storesToWB >= 0);
674}
675
676/*template <class Impl>
677void
678LSQUnit<Impl>::removeMSHR(InstSeqNum seqNum)
679{
680 list<InstSeqNum>::iterator mshr_it = find(mshrSeqNums.begin(),
681 mshrSeqNums.end(),
682 seqNum);
683
684 if (mshr_it != mshrSeqNums.end()) {
685 mshrSeqNums.erase(mshr_it);
686 DPRINTF(LSQUnit, "Removing MSHR. count = %i\n",mshrSeqNums.size());
687 }
688}*/
689
690template <class Impl>
691void
692LSQUnit<Impl>::squash(const InstSeqNum &squashed_num)
693{
694 DPRINTF(LSQUnit, "Squashing until [sn:%lli]!"
695 "(Loads:%i Stores:%i)\n", squashed_num, loads, stores);
696
697 int load_idx = loadTail;
698 decrLdIdx(load_idx);
699
700 while (loads != 0 && loadQueue[load_idx]->seqNum > squashed_num) {
701 DPRINTF(LSQUnit,"Load Instruction PC %#x squashed, "
702 "[sn:%lli]\n",
703 loadQueue[load_idx]->readPC(),
704 loadQueue[load_idx]->seqNum);
705
706 if (isStalled() && load_idx == stallingLoadIdx) {
707 stalled = false;
708 stallingStoreIsn = 0;
709 stallingLoadIdx = 0;
710 }
711
712 // Clear the smart pointer to make sure it is decremented.
713 loadQueue[load_idx]->squashed = true;
714 loadQueue[load_idx] = NULL;
715 --loads;
716
717 // Inefficient!
718 loadTail = load_idx;
719
720 decrLdIdx(load_idx);
721 ++lsqSquashedLoads;
722 }
723
724 if (isLoadBlocked) {
725 if (squashed_num < blockedLoadSeqNum) {
726 isLoadBlocked = false;
727 loadBlockedHandled = false;
728 blockedLoadSeqNum = 0;
729 }
730 }
731
732 int store_idx = storeTail;
733 decrStIdx(store_idx);
734
735 while (stores != 0 &&
736 storeQueue[store_idx].inst->seqNum > squashed_num) {
737 // Instructions marked as can WB are already committed.
738 if (storeQueue[store_idx].canWB) {
739 break;
740 }
741
742 DPRINTF(LSQUnit,"Store Instruction PC %#x squashed, "
743 "idx:%i [sn:%lli]\n",
744 storeQueue[store_idx].inst->readPC(),
745 store_idx, storeQueue[store_idx].inst->seqNum);
746
747 // I don't think this can happen. It should have been cleared
748 // by the stalling load.
749 if (isStalled() &&
750 storeQueue[store_idx].inst->seqNum == stallingStoreIsn) {
751 panic("Is stalled should have been cleared by stalling load!\n");
752 stalled = false;
753 stallingStoreIsn = 0;
754 }
755
756 // Clear the smart pointer to make sure it is decremented.
757 storeQueue[store_idx].inst->squashed = true;
758 storeQueue[store_idx].inst = NULL;
759 storeQueue[store_idx].canWB = 0;
760
761 storeQueue[store_idx].req = NULL;
762 --stores;
763
764 // Inefficient!
765 storeTail = store_idx;
766
767 decrStIdx(store_idx);
768 ++lsqSquashedStores;
769 }
770}
771
772template <class Impl>
773void
774LSQUnit<Impl>::storePostSend(Packet *pkt)
775{
776 if (isStalled() &&
777 storeQueue[storeWBIdx].inst->seqNum == stallingStoreIsn) {
778 DPRINTF(LSQUnit, "Unstalling, stalling store [sn:%lli] "
779 "load idx:%i\n",
780 stallingStoreIsn, stallingLoadIdx);
781 stalled = false;
782 stallingStoreIsn = 0;
783 iewStage->replayMemInst(loadQueue[stallingLoadIdx]);
784 }
785
786 if (!storeQueue[storeWBIdx].inst->isStoreConditional()) {
787 // The store is basically completed at this time. This
788 // only works so long as the checker doesn't try to
789 // verify the value in memory for stores.
790 storeQueue[storeWBIdx].inst->setCompleted();
791 if (cpu->checker) {
792 cpu->checker->tick(storeQueue[storeWBIdx].inst);
793 }
794 }
795
796 if (pkt->result != Packet::Success) {
797 DPRINTF(LSQUnit,"D-Cache Write Miss on idx:%i!\n",
798 storeWBIdx);
799
800 DPRINTF(Activity, "Active st accessing mem miss [sn:%lli]\n",
801 storeQueue[storeWBIdx].inst->seqNum);
802
803 //mshrSeqNums.push_back(storeQueue[storeWBIdx].inst->seqNum);
804
805 //DPRINTF(LSQUnit, "Added MSHR. count = %i\n",mshrSeqNums.size());
806
807 // @todo: Increment stat here.
808 } else {
809 DPRINTF(LSQUnit,"D-Cache: Write Hit on idx:%i !\n",
810 storeWBIdx);
811
812 DPRINTF(Activity, "Active st accessing mem hit [sn:%lli]\n",
813 storeQueue[storeWBIdx].inst->seqNum);
814 }
815
816 incrStIdx(storeWBIdx);
817}
818
819template <class Impl>
820void
821LSQUnit<Impl>::writeback(DynInstPtr &inst, PacketPtr pkt)
822{
823 iewStage->wakeCPU();
824
825 // Squashed instructions do not need to complete their access.
826 if (inst->isSquashed()) {
827 assert(!inst->isStore());
828 ++lsqIgnoredResponses;
829 return;
830 }
831
832 if (!inst->isExecuted()) {
833 inst->setExecuted();
834
835 // Complete access to copy data to proper place.
836 inst->completeAcc(pkt);
837 }
838
839 // Need to insert instruction into queue to commit
840 iewStage->instToCommit(inst);
841
842 iewStage->activityThisCycle();
843}
844
845template <class Impl>
846void
847LSQUnit<Impl>::completeStore(int store_idx)
848{
849 assert(storeQueue[store_idx].inst);
850 storeQueue[store_idx].completed = true;
851 --storesToWB;
852 // A bit conservative because a store completion may not free up entries,
853 // but hopefully avoids two store completions in one cycle from making
854 // the CPU tick twice.
855 cpu->activityThisCycle();
856
857 if (store_idx == storeHead) {
858 do {
859 incrStIdx(storeHead);
860
861 --stores;
862 } while (storeQueue[storeHead].completed &&
863 storeHead != storeTail);
864
865 iewStage->updateLSQNextCycle = true;
866 }
867
868 DPRINTF(LSQUnit, "Completing store [sn:%lli], idx:%i, store head "
869 "idx:%i\n",
870 storeQueue[store_idx].inst->seqNum, store_idx, storeHead);
871
872 if (isStalled() &&
873 storeQueue[store_idx].inst->seqNum == stallingStoreIsn) {
874 DPRINTF(LSQUnit, "Unstalling, stalling store [sn:%lli] "
875 "load idx:%i\n",
876 stallingStoreIsn, stallingLoadIdx);
877 stalled = false;
878 stallingStoreIsn = 0;
879 iewStage->replayMemInst(loadQueue[stallingLoadIdx]);
880 }
881
882 storeQueue[store_idx].inst->setCompleted();
883
884 // Tell the checker we've completed this instruction. Some stores
885 // may get reported twice to the checker, but the checker can
886 // handle that case.
887 if (cpu->checker) {
888 cpu->checker->tick(storeQueue[store_idx].inst);
889 }
890}
891
892template <class Impl>
893void
894LSQUnit<Impl>::recvRetry()
895{
896 if (isStoreBlocked) {
897 assert(retryPkt != NULL);
898
899 if (dcachePort->sendTiming(retryPkt)) {
900 storePostSend(retryPkt);
901 retryPkt = NULL;
902 isStoreBlocked = false;
903 } else {
904 // Still blocked!
905 ++lsqCacheBlocked;
906 }
907 } else if (isLoadBlocked) {
908 DPRINTF(LSQUnit, "Loads squash themselves and all younger insts, "
909 "no need to resend packet.\n");
910 } else {
911 DPRINTF(LSQUnit, "Retry received but LSQ is no longer blocked.\n");
912 }
913}
914
915template <class Impl>
916inline void
917LSQUnit<Impl>::incrStIdx(int &store_idx)
918{
919 if (++store_idx >= SQEntries)
920 store_idx = 0;
921}
922
923template <class Impl>
924inline void
925LSQUnit<Impl>::decrStIdx(int &store_idx)
926{
927 if (--store_idx < 0)
928 store_idx += SQEntries;
929}
930
931template <class Impl>
932inline void
933LSQUnit<Impl>::incrLdIdx(int &load_idx)
934{
935 if (++load_idx >= LQEntries)
936 load_idx = 0;
937}
938
939template <class Impl>
940inline void
941LSQUnit<Impl>::decrLdIdx(int &load_idx)
942{
943 if (--load_idx < 0)
944 load_idx += LQEntries;
945}
946
947template <class Impl>
948void
949LSQUnit<Impl>::dumpInsts()
950{
951 cprintf("Load store queue: Dumping instructions.\n");
952 cprintf("Load queue size: %i\n", loads);
953 cprintf("Load queue: ");
954
955 int load_idx = loadHead;
956
957 while (load_idx != loadTail && loadQueue[load_idx]) {
958 cprintf("%#x ", loadQueue[load_idx]->readPC());
959
960 incrLdIdx(load_idx);
961 }
962
963 cprintf("Store queue size: %i\n", stores);
964 cprintf("Store queue: ");
965
966 int store_idx = storeHead;
967
968 while (store_idx != storeTail && storeQueue[store_idx].inst) {
969 cprintf("%#x ", storeQueue[store_idx].inst->readPC());
970
971 incrStIdx(store_idx);
972 }
973
974 cprintf("\n");
975}