1/*
2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Kevin Lim
29 * Korey Sewell
30 */
31
32#include "cpu/checker/cpu.hh"
33#include "cpu/o3/lsq_unit.hh"
34#include "base/str.hh"
35#include "mem/packet.hh"
36#include "mem/request.hh"
37
38template<class Impl>
39LSQUnit<Impl>::WritebackEvent::WritebackEvent(DynInstPtr &_inst, PacketPtr _pkt,
40 LSQUnit *lsq_ptr)
41 : Event(&mainEventQueue), inst(_inst), pkt(_pkt), lsqPtr(lsq_ptr)
42{
43 this->setFlags(Event::AutoDelete);
44}
45
46template<class Impl>
47void
48LSQUnit<Impl>::WritebackEvent::process()
49{
50 if (!lsqPtr->isSwitchedOut()) {
51 lsqPtr->writeback(inst, pkt);
52 }
53 delete pkt;
54}
55
56template<class Impl>
57const char *
58LSQUnit<Impl>::WritebackEvent::description()
59{
60 return "Store writeback event";
61}
62
63template<class Impl>
64void
65LSQUnit<Impl>::completeDataAccess(PacketPtr pkt)
66{
67 LSQSenderState *state = dynamic_cast<LSQSenderState *>(pkt->senderState);
68 DynInstPtr inst = state->inst;
69 DPRINTF(IEW, "Writeback event [sn:%lli]\n", inst->seqNum);
70 DPRINTF(Activity, "Activity: Writeback event [sn:%lli]\n", inst->seqNum);
71
72 //iewStage->ldstQueue.removeMSHR(inst->threadNumber,inst->seqNum);
73
74 if (isSwitchedOut() || inst->isSquashed()) {
75 delete state;
76 delete pkt;
77 return;
78 } else {
79 if (!state->noWB) {
80 writeback(inst, pkt);
81 }
82
83 if (inst->isStore()) {
84 completeStore(state->idx);
85 }
86 }
87
88 delete state;
89 delete pkt;
90}
91
92template <class Impl>
93Tick
94LSQUnit<Impl>::DcachePort::recvAtomic(PacketPtr pkt)
95{
96 panic("O3CPU model does not work with atomic mode!");
97 return curTick;
98}
99
100template <class Impl>
101void
102LSQUnit<Impl>::DcachePort::recvFunctional(PacketPtr pkt)
103{
104 panic("O3CPU doesn't expect recvFunctional callback!");
105}
106
107template <class Impl>
108void
109LSQUnit<Impl>::DcachePort::recvStatusChange(Status status)
110{
111 if (status == RangeChange)
112 return;
113
114 panic("O3CPU doesn't expect recvStatusChange callback!");
115}
116
117template <class Impl>
118bool
119LSQUnit<Impl>::DcachePort::recvTiming(PacketPtr pkt)
120{
121 lsq->completeDataAccess(pkt);
122 return true;
123}
124
125template <class Impl>
126void
127LSQUnit<Impl>::DcachePort::recvRetry()
128{
129 lsq->recvRetry();
130}
131
132template <class Impl>
133LSQUnit<Impl>::LSQUnit()
134 : loads(0), stores(0), storesToWB(0), stalled(false),
135 isStoreBlocked(false), isLoadBlocked(false),
136 loadBlockedHandled(false)
137{
138}
139
140template<class Impl>
141void
142LSQUnit<Impl>::init(Params *params, unsigned maxLQEntries,
143 unsigned maxSQEntries, unsigned id)
144{
145 DPRINTF(LSQUnit, "Creating LSQUnit%i object.\n",id);
146
147 switchedOut = false;
148
149 lsqID = id;
150
151 // Add 1 for the sentinel entry (they are circular queues).
152 LQEntries = maxLQEntries + 1;
153 SQEntries = maxSQEntries + 1;
154
155 loadQueue.resize(LQEntries);
156 storeQueue.resize(SQEntries);
157
158 loadHead = loadTail = 0;
159
160 storeHead = storeWBIdx = storeTail = 0;
161
162 usedPorts = 0;
163 cachePorts = params->cachePorts;
164
165 mem = params->mem;
166
167 memDepViolator = NULL;
168
169 blockedLoadSeqNum = 0;
170}
171
172template<class Impl>
173void
174LSQUnit<Impl>::setCPU(FullCPU *cpu_ptr)
175{
176 cpu = cpu_ptr;
177 dcachePort = new DcachePort(cpu, this);
178
179 Port *mem_dport = mem->getPort("");
180 dcachePort->setPeer(mem_dport);
181 mem_dport->setPeer(dcachePort);
182
183 if (cpu->checker) {
184 cpu->checker->setDcachePort(dcachePort);
185 }
186}
187
188template<class Impl>
189std::string
190LSQUnit<Impl>::name() const
191{
192 if (Impl::MaxThreads == 1) {
193 return iewStage->name() + ".lsq";
194 } else {
195 return iewStage->name() + ".lsq.thread." + to_string(lsqID);
196 }
197}
198
199template<class Impl>
200void
201LSQUnit<Impl>::clearLQ()
202{
203 loadQueue.clear();
204}
205
206template<class Impl>
207void
208LSQUnit<Impl>::clearSQ()
209{
210 storeQueue.clear();
211}
212
213template<class Impl>
214void
215LSQUnit<Impl>::switchOut()
216{
217 switchedOut = true;
218 for (int i = 0; i < loadQueue.size(); ++i)
219 loadQueue[i] = NULL;
220
221 assert(storesToWB == 0);
222}
223
224template<class Impl>
225void
226LSQUnit<Impl>::takeOverFrom()
227{
228 switchedOut = false;
229 loads = stores = storesToWB = 0;
230
231 loadHead = loadTail = 0;
232
233 storeHead = storeWBIdx = storeTail = 0;
234
235 usedPorts = 0;
236
237 memDepViolator = NULL;
238
239 blockedLoadSeqNum = 0;
240
241 stalled = false;
242 isLoadBlocked = false;
243 loadBlockedHandled = false;
244}
245
246template<class Impl>
247void
248LSQUnit<Impl>::resizeLQ(unsigned size)
249{
250 unsigned size_plus_sentinel = size + 1;
251 assert(size_plus_sentinel >= LQEntries);
252
253 if (size_plus_sentinel > LQEntries) {
254 while (size_plus_sentinel > loadQueue.size()) {
255 DynInstPtr dummy;
256 loadQueue.push_back(dummy);
257 LQEntries++;
258 }
259 } else {
260 LQEntries = size_plus_sentinel;
261 }
262
263}
264
265template<class Impl>
266void
267LSQUnit<Impl>::resizeSQ(unsigned size)
268{
269 unsigned size_plus_sentinel = size + 1;
270 if (size_plus_sentinel > SQEntries) {
271 while (size_plus_sentinel > storeQueue.size()) {
272 SQEntry dummy;
273 storeQueue.push_back(dummy);
274 SQEntries++;
275 }
276 } else {
277 SQEntries = size_plus_sentinel;
278 }
279}
280
281template <class Impl>
282void
283LSQUnit<Impl>::insert(DynInstPtr &inst)
284{
285 assert(inst->isMemRef());
286
287 assert(inst->isLoad() || inst->isStore());
288
289 if (inst->isLoad()) {
290 insertLoad(inst);
291 } else {
292 insertStore(inst);
293 }
294
295 inst->setInLSQ();
296}
297
298template <class Impl>
299void
300LSQUnit<Impl>::insertLoad(DynInstPtr &load_inst)
301{
302 assert((loadTail + 1) % LQEntries != loadHead);
303 assert(loads < LQEntries);
304
305 DPRINTF(LSQUnit, "Inserting load PC %#x, idx:%i [sn:%lli]\n",
306 load_inst->readPC(), loadTail, load_inst->seqNum);
307
308 load_inst->lqIdx = loadTail;
309
310 if (stores == 0) {
311 load_inst->sqIdx = -1;
312 } else {
313 load_inst->sqIdx = storeTail;
314 }
315
316 loadQueue[loadTail] = load_inst;
317
318 incrLdIdx(loadTail);
319
320 ++loads;
321}
322
323template <class Impl>
324void
325LSQUnit<Impl>::insertStore(DynInstPtr &store_inst)
326{
327 // Make sure it is not full before inserting an instruction.
328 assert((storeTail + 1) % SQEntries != storeHead);
329 assert(stores < SQEntries);
330
331 DPRINTF(LSQUnit, "Inserting store PC %#x, idx:%i [sn:%lli]\n",
332 store_inst->readPC(), storeTail, store_inst->seqNum);
333
334 store_inst->sqIdx = storeTail;
335 store_inst->lqIdx = loadTail;
336
337 storeQueue[storeTail] = SQEntry(store_inst);
338
339 incrStIdx(storeTail);
340
341 ++stores;
342}
343
344template <class Impl>
345typename Impl::DynInstPtr
346LSQUnit<Impl>::getMemDepViolator()
347{
348 DynInstPtr temp = memDepViolator;
349
350 memDepViolator = NULL;
351
352 return temp;
353}
354
355template <class Impl>
356unsigned
357LSQUnit<Impl>::numFreeEntries()
358{
359 unsigned free_lq_entries = LQEntries - loads;
360 unsigned free_sq_entries = SQEntries - stores;
361
362 // Both the LQ and SQ entries have an extra dummy entry to differentiate
363 // empty/full conditions. Subtract 1 from the free entries.
364 if (free_lq_entries < free_sq_entries) {
365 return free_lq_entries - 1;
366 } else {
367 return free_sq_entries - 1;
368 }
369}
370
371template <class Impl>
372int
373LSQUnit<Impl>::numLoadsReady()
374{
375 int load_idx = loadHead;
376 int retval = 0;
377
378 while (load_idx != loadTail) {
379 assert(loadQueue[load_idx]);
380
381 if (loadQueue[load_idx]->readyToIssue()) {
382 ++retval;
383 }
384 }
385
386 return retval;
387}
388
389template <class Impl>
390Fault
391LSQUnit<Impl>::executeLoad(DynInstPtr &inst)
392{
393 // Execute a specific load.
394 Fault load_fault = NoFault;
395
396 DPRINTF(LSQUnit, "Executing load PC %#x, [sn:%lli]\n",
397 inst->readPC(),inst->seqNum);
398
399 load_fault = inst->initiateAcc();
400
401 // If the instruction faulted, then we need to send it along to commit
402 // without the instruction completing.
403 if (load_fault != NoFault) {
404 // Send this instruction to commit, also make sure iew stage
405 // realizes there is activity.
406 iewStage->instToCommit(inst);
407 iewStage->activityThisCycle();
408 }
409
410 return load_fault;
411}
412
413template <class Impl>
414Fault
415LSQUnit<Impl>::executeStore(DynInstPtr &store_inst)
416{
417 using namespace TheISA;
418 // Make sure that a store exists.
419 assert(stores != 0);
420
421 int store_idx = store_inst->sqIdx;
422
423 DPRINTF(LSQUnit, "Executing store PC %#x [sn:%lli]\n",
424 store_inst->readPC(), store_inst->seqNum);
425
426 // Check the recently completed loads to see if any match this store's
427 // address. If so, then we have a memory ordering violation.
428 int load_idx = store_inst->lqIdx;
429
430 Fault store_fault = store_inst->initiateAcc();
431
432 if (storeQueue[store_idx].size == 0) {
433 DPRINTF(LSQUnit,"Fault on Store PC %#x, [sn:%lli],Size = 0\n",
434 store_inst->readPC(),store_inst->seqNum);
435
436 return store_fault;
437 }
438
439 assert(store_fault == NoFault);
440
441 if (store_inst->isStoreConditional()) {
442 // Store conditionals need to set themselves as able to
443 // writeback if we haven't had a fault by here.
444 storeQueue[store_idx].canWB = true;
445
446 ++storesToWB;
447 }
448
449 if (!memDepViolator) {
450 while (load_idx != loadTail) {
451 // Really only need to check loads that have actually executed
452 // It's safe to check all loads because effAddr is set to
453 // InvalAddr when the dyn inst is created.
454
455 // @todo: For now this is extra conservative, detecting a
456 // violation if the addresses match assuming all accesses
457 // are quad word accesses.
458
459 // @todo: Fix this, magic number being used here
460 if ((loadQueue[load_idx]->effAddr >> 8) ==
461 (store_inst->effAddr >> 8)) {
462 // A load incorrectly passed this store. Squash and refetch.
463 // For now return a fault to show that it was unsuccessful.
464 memDepViolator = loadQueue[load_idx];
465
466 return genMachineCheckFault();
467 }
468
469 incrLdIdx(load_idx);
470 }
471
472 // If we've reached this point, there was no violation.
473 memDepViolator = NULL;
474 }
475
476 return store_fault;
477}
478
479template <class Impl>
480void
481LSQUnit<Impl>::commitLoad()
482{
483 assert(loadQueue[loadHead]);
484
485 DPRINTF(LSQUnit, "Committing head load instruction, PC %#x\n",
486 loadQueue[loadHead]->readPC());
487
488 loadQueue[loadHead] = NULL;
489
490 incrLdIdx(loadHead);
491
492 --loads;
493}
494
495template <class Impl>
496void
497LSQUnit<Impl>::commitLoads(InstSeqNum &youngest_inst)
498{
499 assert(loads == 0 || loadQueue[loadHead]);
500
501 while (loads != 0 && loadQueue[loadHead]->seqNum <= youngest_inst) {
502 commitLoad();
503 }
504}
505
506template <class Impl>
507void
508LSQUnit<Impl>::commitStores(InstSeqNum &youngest_inst)
509{
510 assert(stores == 0 || storeQueue[storeHead].inst);
511
512 int store_idx = storeHead;
513
514 while (store_idx != storeTail) {
515 assert(storeQueue[store_idx].inst);
516 // Mark any stores that are now committed and have not yet
517 // been marked as able to write back.
518 if (!storeQueue[store_idx].canWB) {
519 if (storeQueue[store_idx].inst->seqNum > youngest_inst) {
520 break;
521 }
522 DPRINTF(LSQUnit, "Marking store as able to write back, PC "
523 "%#x [sn:%lli]\n",
524 storeQueue[store_idx].inst->readPC(),
525 storeQueue[store_idx].inst->seqNum);
526
527 storeQueue[store_idx].canWB = true;
528
529 ++storesToWB;
530 }
531
532 incrStIdx(store_idx);
533 }
534}
535
536template <class Impl>
537void
538LSQUnit<Impl>::writebackStores()
539{
540 while (storesToWB > 0 &&
541 storeWBIdx != storeTail &&
542 storeQueue[storeWBIdx].inst &&
543 storeQueue[storeWBIdx].canWB &&
544 usedPorts < cachePorts) {
545
546 if (isStoreBlocked) {
547 DPRINTF(LSQUnit, "Unable to write back any more stores, cache"
548 " is blocked!\n");
549 break;
550 }
551
552 // Store didn't write any data so no need to write it back to
553 // memory.
554 if (storeQueue[storeWBIdx].size == 0) {
555 completeStore(storeWBIdx);
556
557 incrStIdx(storeWBIdx);
558
559 continue;
560 }
561
562 ++usedPorts;
563
564 if (storeQueue[storeWBIdx].inst->isDataPrefetch()) {
565 incrStIdx(storeWBIdx);
566
567 continue;
568 }
569
570 assert(storeQueue[storeWBIdx].req);
571 assert(!storeQueue[storeWBIdx].committed);
572
573 DynInstPtr inst = storeQueue[storeWBIdx].inst;
574
575 Request *req = storeQueue[storeWBIdx].req;
576 storeQueue[storeWBIdx].committed = true;
577
578 assert(!inst->memData);
579 inst->memData = new uint8_t[64];
580 memcpy(inst->memData, (uint8_t *)&storeQueue[storeWBIdx].data,
581 req->getSize());
582
583 PacketPtr data_pkt = new Packet(req, Packet::WriteReq, Packet::Broadcast);
584 data_pkt->dataStatic(inst->memData);
585
586 LSQSenderState *state = new LSQSenderState;
587 state->isLoad = false;
588 state->idx = storeWBIdx;
589 state->inst = inst;
590 data_pkt->senderState = state;
591
592 DPRINTF(LSQUnit, "D-Cache: Writing back store idx:%i PC:%#x "
593 "to Addr:%#x, data:%#x [sn:%lli]\n",
594 storeWBIdx, storeQueue[storeWBIdx].inst->readPC(),
595 req->getPaddr(), *(inst->memData),
596 storeQueue[storeWBIdx].inst->seqNum);
597
598 // @todo: Remove this SC hack once the memory system handles it.
599 if (req->getFlags() & LOCKED) {
600 if (req->getFlags() & UNCACHEABLE) {
601 req->setScResult(2);
602 } else {
603 if (cpu->lockFlag) {
604 req->setScResult(1);
605 } else {
606 req->setScResult(0);
607 // Hack: Instantly complete this store.
608 completeDataAccess(data_pkt);
609 incrStIdx(storeWBIdx);
610 continue;
611 }
612 }
613 } else {
614 // Non-store conditionals do not need a writeback.
615 state->noWB = true;
616 }
617
618 if (!dcachePort->sendTiming(data_pkt)) {
619 // Need to handle becoming blocked on a store.
620 isStoreBlocked = true;
621
622 assert(retryPkt == NULL);
623 retryPkt = data_pkt;
624 } else {
625 storePostSend(data_pkt);
626 }
627 }
628
629 // Not sure this should set it to 0.
630 usedPorts = 0;
631
632 assert(stores >= 0 && storesToWB >= 0);
633}
634
635/*template <class Impl>
636void
637LSQUnit<Impl>::removeMSHR(InstSeqNum seqNum)
638{
639 list<InstSeqNum>::iterator mshr_it = find(mshrSeqNums.begin(),
640 mshrSeqNums.end(),
641 seqNum);
642
643 if (mshr_it != mshrSeqNums.end()) {
644 mshrSeqNums.erase(mshr_it);
645 DPRINTF(LSQUnit, "Removing MSHR. count = %i\n",mshrSeqNums.size());
646 }
647}*/
648
649template <class Impl>
650void
651LSQUnit<Impl>::squash(const InstSeqNum &squashed_num)
652{
653 DPRINTF(LSQUnit, "Squashing until [sn:%lli]!"
654 "(Loads:%i Stores:%i)\n", squashed_num, loads, stores);
655
656 int load_idx = loadTail;
657 decrLdIdx(load_idx);
658
659 while (loads != 0 && loadQueue[load_idx]->seqNum > squashed_num) {
660 DPRINTF(LSQUnit,"Load Instruction PC %#x squashed, "
661 "[sn:%lli]\n",
662 loadQueue[load_idx]->readPC(),
663 loadQueue[load_idx]->seqNum);
664
665 if (isStalled() && load_idx == stallingLoadIdx) {
666 stalled = false;
667 stallingStoreIsn = 0;
668 stallingLoadIdx = 0;
669 }
670
671 // Clear the smart pointer to make sure it is decremented.
672 loadQueue[load_idx]->squashed = true;
673 loadQueue[load_idx] = NULL;
674 --loads;
675
676 // Inefficient!
677 loadTail = load_idx;
678
679 decrLdIdx(load_idx);
680 }
681
682 if (isLoadBlocked) {
683 if (squashed_num < blockedLoadSeqNum) {
684 isLoadBlocked = false;
685 loadBlockedHandled = false;
686 blockedLoadSeqNum = 0;
687 }
688 }
689
690 int store_idx = storeTail;
691 decrStIdx(store_idx);
692
693 while (stores != 0 &&
694 storeQueue[store_idx].inst->seqNum > squashed_num) {
695 // Instructions marked as can WB are already committed.
696 if (storeQueue[store_idx].canWB) {
697 break;
698 }
699
700 DPRINTF(LSQUnit,"Store Instruction PC %#x squashed, "
701 "idx:%i [sn:%lli]\n",
702 storeQueue[store_idx].inst->readPC(),
703 store_idx, storeQueue[store_idx].inst->seqNum);
704
705 // I don't think this can happen. It should have been cleared
706 // by the stalling load.
707 if (isStalled() &&
708 storeQueue[store_idx].inst->seqNum == stallingStoreIsn) {
709 panic("Is stalled should have been cleared by stalling load!\n");
710 stalled = false;
711 stallingStoreIsn = 0;
712 }
713
714 // Clear the smart pointer to make sure it is decremented.
715 storeQueue[store_idx].inst->squashed = true;
716 storeQueue[store_idx].inst = NULL;
717 storeQueue[store_idx].canWB = 0;
718
719 storeQueue[store_idx].req = NULL;
720 --stores;
721
722 // Inefficient!
723 storeTail = store_idx;
724
725 decrStIdx(store_idx);
726 }
727}
728
729template <class Impl>
730void
731LSQUnit<Impl>::storePostSend(Packet *pkt)
732{
733 if (isStalled() &&
734 storeQueue[storeWBIdx].inst->seqNum == stallingStoreIsn) {
735 DPRINTF(LSQUnit, "Unstalling, stalling store [sn:%lli] "
736 "load idx:%i\n",
737 stallingStoreIsn, stallingLoadIdx);
738 stalled = false;
739 stallingStoreIsn = 0;
740 iewStage->replayMemInst(loadQueue[stallingLoadIdx]);
741 }
742
743 if (!storeQueue[storeWBIdx].inst->isStoreConditional()) {
744 // The store is basically completed at this time. This
745 // only works so long as the checker doesn't try to
746 // verify the value in memory for stores.
747 storeQueue[storeWBIdx].inst->setCompleted();
748 if (cpu->checker) {
749 cpu->checker->tick(storeQueue[storeWBIdx].inst);
750 }
751 }
752
753 if (pkt->result != Packet::Success) {
754 DPRINTF(LSQUnit,"D-Cache Write Miss on idx:%i!\n",
755 storeWBIdx);
756
757 DPRINTF(Activity, "Active st accessing mem miss [sn:%lli]\n",
758 storeQueue[storeWBIdx].inst->seqNum);
759
760 //mshrSeqNums.push_back(storeQueue[storeWBIdx].inst->seqNum);
761
762 //DPRINTF(LSQUnit, "Added MSHR. count = %i\n",mshrSeqNums.size());
763
764 // @todo: Increment stat here.
765 } else {
766 DPRINTF(LSQUnit,"D-Cache: Write Hit on idx:%i !\n",
767 storeWBIdx);
768
769 DPRINTF(Activity, "Active st accessing mem hit [sn:%lli]\n",
770 storeQueue[storeWBIdx].inst->seqNum);
771 }
772
773 incrStIdx(storeWBIdx);
774}
775
776template <class Impl>
777void
778LSQUnit<Impl>::writeback(DynInstPtr &inst, PacketPtr pkt)
779{
780 iewStage->wakeCPU();
781
782 // Squashed instructions do not need to complete their access.
783 if (inst->isSquashed()) {
784 assert(!inst->isStore());
785 return;
786 }
787
788 if (!inst->isExecuted()) {
789 inst->setExecuted();
790
791 // Complete access to copy data to proper place.
792 inst->completeAcc(pkt);
793 }
794
795 // Need to insert instruction into queue to commit
796 iewStage->instToCommit(inst);
797
798 iewStage->activityThisCycle();
799}
800
801template <class Impl>
802void
803LSQUnit<Impl>::completeStore(int store_idx)
804{
805 assert(storeQueue[store_idx].inst);
806 storeQueue[store_idx].completed = true;
807 --storesToWB;
808 // A bit conservative because a store completion may not free up entries,
809 // but hopefully avoids two store completions in one cycle from making
810 // the CPU tick twice.
811 cpu->activityThisCycle();
812
813 if (store_idx == storeHead) {
814 do {
815 incrStIdx(storeHead);
816
817 --stores;
818 } while (storeQueue[storeHead].completed &&
819 storeHead != storeTail);
820
821 iewStage->updateLSQNextCycle = true;
822 }
823
824 DPRINTF(LSQUnit, "Completing store [sn:%lli], idx:%i, store head "
825 "idx:%i\n",
826 storeQueue[store_idx].inst->seqNum, store_idx, storeHead);
827
828 if (isStalled() &&
829 storeQueue[store_idx].inst->seqNum == stallingStoreIsn) {
830 DPRINTF(LSQUnit, "Unstalling, stalling store [sn:%lli] "
831 "load idx:%i\n",
832 stallingStoreIsn, stallingLoadIdx);
833 stalled = false;
834 stallingStoreIsn = 0;
835 iewStage->replayMemInst(loadQueue[stallingLoadIdx]);
836 }
837
838 storeQueue[store_idx].inst->setCompleted();
839
840 // Tell the checker we've completed this instruction. Some stores
841 // may get reported twice to the checker, but the checker can
842 // handle that case.
843 if (cpu->checker) {
844 cpu->checker->tick(storeQueue[store_idx].inst);
845 }
846}
847
848template <class Impl>
849void
850LSQUnit<Impl>::recvRetry()
851{
852 if (isStoreBlocked) {
853 assert(retryPkt != NULL);
854
855 if (dcachePort->sendTiming(retryPkt)) {
856 storePostSend(retryPkt);
857 retryPkt = NULL;
858 isStoreBlocked = false;
859 } else {
860 // Still blocked!
861 }
862 } else if (isLoadBlocked) {
863 DPRINTF(LSQUnit, "Loads squash themselves and all younger insts, "
864 "no need to resend packet.\n");
865 } else {
866 DPRINTF(LSQUnit, "Retry received but LSQ is no longer blocked.\n");
867 }
868}
869
870template <class Impl>
871inline void
872LSQUnit<Impl>::incrStIdx(int &store_idx)
873{
874 if (++store_idx >= SQEntries)
875 store_idx = 0;
876}
877
878template <class Impl>
879inline void
880LSQUnit<Impl>::decrStIdx(int &store_idx)
881{
882 if (--store_idx < 0)
883 store_idx += SQEntries;
884}
885
886template <class Impl>
887inline void
888LSQUnit<Impl>::incrLdIdx(int &load_idx)
889{
890 if (++load_idx >= LQEntries)
891 load_idx = 0;
892}
893
894template <class Impl>
895inline void
896LSQUnit<Impl>::decrLdIdx(int &load_idx)
897{
898 if (--load_idx < 0)
899 load_idx += LQEntries;
900}
901
902template <class Impl>
903void
904LSQUnit<Impl>::dumpInsts()
905{
906 cprintf("Load store queue: Dumping instructions.\n");
907 cprintf("Load queue size: %i\n", loads);
908 cprintf("Load queue: ");
909
910 int load_idx = loadHead;
911
912 while (load_idx != loadTail && loadQueue[load_idx]) {
913 cprintf("%#x ", loadQueue[load_idx]->readPC());
914
915 incrLdIdx(load_idx);
916 }
917
918 cprintf("Store queue size: %i\n", stores);
919 cprintf("Store queue: ");
920
921 int store_idx = storeHead;
922
923 while (store_idx != storeTail && storeQueue[store_idx].inst) {
924 cprintf("%#x ", storeQueue[store_idx].inst->readPC());
925
926 incrStIdx(store_idx);
927 }
928
929 cprintf("\n");
930}