lsq_unit.hh (9440:fdc91cab5760) lsq_unit.hh (9444:ab47fe7f03f0)
1/*
1/*
2 * Copyright (c) 2012 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright

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86 std::string name() const;
87
88 /** Registers statistics. */
89 void regStats();
90
91 /** Sets the pointer to the dcache port. */
92 void setDcachePort(MasterPort *dcache_port);
93
14 * Copyright (c) 2004-2006 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright

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98 std::string name() const;
99
100 /** Registers statistics. */
101 void regStats();
102
103 /** Sets the pointer to the dcache port. */
104 void setDcachePort(MasterPort *dcache_port);
105
94 /** Switches out LSQ unit. */
95 void switchOut();
106 /** Perform sanity checks after a drain. */
107 void drainSanityCheck() const;
96
97 /** Takes over from another CPU's thread. */
98 void takeOverFrom();
99
108
109 /** Takes over from another CPU's thread. */
110 void takeOverFrom();
111
100 /** Returns if the LSQ is switched out. */
101 bool isSwitchedOut() { return switchedOut; }
102
103 /** Ticks the LSQ unit, which in this case only resets the number of
104 * used cache ports.
105 * @todo: Move the number of used ports up to the LSQ level so it can
106 * be shared by all LSQ units.
107 */
108 void tick() { usedPorts = 0; }
109
110 /** Inserts an instruction. */

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196 int numLoads() { return loads; }
197
198 /** Returns the number of stores in the SQ. */
199 int numStores() { return stores; }
200
201 /** Returns if either the LQ or SQ is full. */
202 bool isFull() { return lqFull() || sqFull(); }
203
112 /** Ticks the LSQ unit, which in this case only resets the number of
113 * used cache ports.
114 * @todo: Move the number of used ports up to the LSQ level so it can
115 * be shared by all LSQ units.
116 */
117 void tick() { usedPorts = 0; }
118
119 /** Inserts an instruction. */

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205 int numLoads() { return loads; }
206
207 /** Returns the number of stores in the SQ. */
208 int numStores() { return stores; }
209
210 /** Returns if either the LQ or SQ is full. */
211 bool isFull() { return lqFull() || sqFull(); }
212
213 /** Returns if both the LQ and SQ are empty. */
214 bool isEmpty() const { return lqEmpty() && sqEmpty(); }
215
204 /** Returns if the LQ is full. */
205 bool lqFull() { return loads >= (LQEntries - 1); }
206
207 /** Returns if the SQ is full. */
208 bool sqFull() { return stores >= (SQEntries - 1); }
209
216 /** Returns if the LQ is full. */
217 bool lqFull() { return loads >= (LQEntries - 1); }
218
219 /** Returns if the SQ is full. */
220 bool sqFull() { return stores >= (SQEntries - 1); }
221
222 /** Returns if the LQ is empty. */
223 bool lqEmpty() const { return loads == 0; }
224
225 /** Returns if the SQ is empty. */
226 bool sqEmpty() const { return stores == 0; }
227
210 /** Returns the number of instructions in the LSQ. */
211 unsigned getCount() { return loads + stores; }
212
213 /** Returns if there are any stores to writeback. */
214 bool hasStoresToWB() { return storesToWB; }
215
216 /** Returns the number of stores to writeback. */
217 int numStoresToWB() { return storesToWB; }
218
219 /** Returns if the LSQ unit will writeback on this cycle. */
220 bool willWB() { return storeQueue[storeWBIdx].canWB &&
221 !storeQueue[storeWBIdx].completed &&
222 !isStoreBlocked; }
223
224 /** Handles doing the retry. */
225 void recvRetry();
226
227 private:
228 /** Returns the number of instructions in the LSQ. */
229 unsigned getCount() { return loads + stores; }
230
231 /** Returns if there are any stores to writeback. */
232 bool hasStoresToWB() { return storesToWB; }
233
234 /** Returns the number of stores to writeback. */
235 int numStoresToWB() { return storesToWB; }
236
237 /** Returns if the LSQ unit will writeback on this cycle. */
238 bool willWB() { return storeQueue[storeWBIdx].canWB &&
239 !storeQueue[storeWBIdx].completed &&
240 !isStoreBlocked; }
241
242 /** Handles doing the retry. */
243 void recvRetry();
244
245 private:
246 /** Reset the LSQ state */
247 void resetState();
248
228 /** Writes back the instruction, sending it to IEW. */
229 void writeback(DynInstPtr &inst, PacketPtr pkt);
230
231 /** Writes back a store that couldn't be completed the previous cycle. */
232 void writebackPendingStore();
233
234 /** Handles completing the send of a store to memory. */
235 void storePostSend(PacketPtr pkt);

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415
416 /// @todo Consider moving to a more advanced model with write vs read ports
417 /** The number of cache ports available each cycle. */
418 int cachePorts;
419
420 /** The number of used cache ports in this cycle. */
421 int usedPorts;
422
249 /** Writes back the instruction, sending it to IEW. */
250 void writeback(DynInstPtr &inst, PacketPtr pkt);
251
252 /** Writes back a store that couldn't be completed the previous cycle. */
253 void writebackPendingStore();
254
255 /** Handles completing the send of a store to memory. */
256 void storePostSend(PacketPtr pkt);

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436
437 /// @todo Consider moving to a more advanced model with write vs read ports
438 /** The number of cache ports available each cycle. */
439 int cachePorts;
440
441 /** The number of used cache ports in this cycle. */
442 int usedPorts;
443
423 /** Is the LSQ switched out. */
424 bool switchedOut;
425
426 //list<InstSeqNum> mshrSeqNums;
427
428 /** Address Mask for a cache block (e.g. ~(cache_block_size-1)) */
429 Addr cacheBlockMask;
430
431 /** Wire to read information from the issue stage time queue. */
432 typename TimeBuffer<IssueStruct>::wire fromIssue;
433

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445
446 /** Address Mask for a cache block (e.g. ~(cache_block_size-1)) */
447 Addr cacheBlockMask;
448
449 /** Wire to read information from the issue stage time queue. */
450 typename TimeBuffer<IssueStruct>::wire fromIssue;
451

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