lsq_unit.hh (9044:904ddeecc653) lsq_unit.hh (9046:a1104cc13db2)
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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270 MasterPort *dcachePort;
271
272 /** Derived class to hold any sender state the LSQ needs. */
273 class LSQSenderState : public Packet::SenderState
274 {
275 public:
276 /** Default constructor. */
277 LSQSenderState()
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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270 MasterPort *dcachePort;
271
272 /** Derived class to hold any sender state the LSQ needs. */
273 class LSQSenderState : public Packet::SenderState
274 {
275 public:
276 /** Default constructor. */
277 LSQSenderState()
278 : noWB(false), isSplit(false), pktToSend(false), outstanding(1),
279 mainPkt(NULL), pendingPacket(NULL)
280 { }
278 : mainPkt(NULL), pendingPacket(NULL), outstanding(1),
279 noWB(false), isSplit(false), pktToSend(false)
280 { }
281
282 /** Instruction who initiated the access to memory. */
283 DynInstPtr inst;
281
282 /** Instruction who initiated the access to memory. */
283 DynInstPtr inst;
284 /** The main packet from a split load, used during writeback. */
285 PacketPtr mainPkt;
286 /** A second packet from a split store that needs sending. */
287 PacketPtr pendingPacket;
288 /** The LQ/SQ index of the instruction. */
289 uint8_t idx;
290 /** Number of outstanding packets to complete. */
291 uint8_t outstanding;
284 /** Whether or not it is a load. */
285 bool isLoad;
292 /** Whether or not it is a load. */
293 bool isLoad;
286 /** The LQ/SQ index of the instruction. */
287 int idx;
288 /** Whether or not the instruction will need to writeback. */
289 bool noWB;
290 /** Whether or not this access is split in two. */
291 bool isSplit;
292 /** Whether or not there is a packet that needs sending. */
293 bool pktToSend;
294 /** Whether or not the instruction will need to writeback. */
295 bool noWB;
296 /** Whether or not this access is split in two. */
297 bool isSplit;
298 /** Whether or not there is a packet that needs sending. */
299 bool pktToSend;
294 /** Number of outstanding packets to complete. */
295 int outstanding;
296 /** The main packet from a split load, used during writeback. */
297 PacketPtr mainPkt;
298 /** A second packet from a split store that needs sending. */
299 PacketPtr pendingPacket;
300
301 /** Completes a packet and returns whether the access is finished. */
302 inline bool complete() { return --outstanding == 0; }
303 };
304
305 /** Writeback event, specifically for when stores forward data to loads. */
306 class WritebackEvent : public Event {
307 public:

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337
338 /** Constructs a store queue entry for a given instruction. */
339 SQEntry(DynInstPtr &_inst)
340 : inst(_inst), req(NULL), sreqLow(NULL), sreqHigh(NULL), size(0),
341 isSplit(0), canWB(0), committed(0), completed(0)
342 {
343 std::memset(data, 0, sizeof(data));
344 }
300
301 /** Completes a packet and returns whether the access is finished. */
302 inline bool complete() { return --outstanding == 0; }
303 };
304
305 /** Writeback event, specifically for when stores forward data to loads. */
306 class WritebackEvent : public Event {
307 public:

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337
338 /** Constructs a store queue entry for a given instruction. */
339 SQEntry(DynInstPtr &_inst)
340 : inst(_inst), req(NULL), sreqLow(NULL), sreqHigh(NULL), size(0),
341 isSplit(0), canWB(0), committed(0), completed(0)
342 {
343 std::memset(data, 0, sizeof(data));
344 }
345
345 /** The store data. */
346 char data[16];
346 /** The store instruction. */
347 DynInstPtr inst;
348 /** The request for the store. */
349 RequestPtr req;
350 /** The split requests for the store. */
351 RequestPtr sreqLow;
352 RequestPtr sreqHigh;
353 /** The size of the store. */
347 /** The store instruction. */
348 DynInstPtr inst;
349 /** The request for the store. */
350 RequestPtr req;
351 /** The split requests for the store. */
352 RequestPtr sreqLow;
353 RequestPtr sreqHigh;
354 /** The size of the store. */
354 int size;
355 /** The store data. */
356 char data[16];
355 uint8_t size;
357 /** Whether or not the store is split into two requests. */
358 bool isSplit;
359 /** Whether or not the store can writeback. */
360 bool canWB;
361 /** Whether or not the store is committed. */
362 bool committed;
363 /** Whether or not the store is completed. */
364 bool completed;

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588 load_idx, store_idx, storeHead, req->getPaddr(),
589 sreqLow ? " split" : "");
590
591 if (req->isLLSC()) {
592 assert(!sreqLow);
593 // Disable recording the result temporarily. Writing to misc
594 // regs normally updates the result, but this is not the
595 // desired behavior when handling store conditionals.
356 /** Whether or not the store is split into two requests. */
357 bool isSplit;
358 /** Whether or not the store can writeback. */
359 bool canWB;
360 /** Whether or not the store is committed. */
361 bool committed;
362 /** Whether or not the store is completed. */
363 bool completed;

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587 load_idx, store_idx, storeHead, req->getPaddr(),
588 sreqLow ? " split" : "");
589
590 if (req->isLLSC()) {
591 assert(!sreqLow);
592 // Disable recording the result temporarily. Writing to misc
593 // regs normally updates the result, but this is not the
594 // desired behavior when handling store conditionals.
596 load_inst->recordResult = false;
595 load_inst->recordResult(false);
597 TheISA::handleLockedRead(load_inst.get(), req);
596 TheISA::handleLockedRead(load_inst.get(), req);
598 load_inst->recordResult = true;
597 load_inst->recordResult(true);
599 }
600
601 if (req->isMmappedIpr()) {
602 assert(!load_inst->memData);
603 load_inst->memData = new uint8_t[64];
604
605 ThreadContext *thread = cpu->tcBase(lsqID);
606 Tick delay;

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646
647 store_size = storeQueue[store_idx].size;
648
649 if (store_size == 0)
650 continue;
651 else if (storeQueue[store_idx].inst->uncacheable())
652 continue;
653
598 }
599
600 if (req->isMmappedIpr()) {
601 assert(!load_inst->memData);
602 load_inst->memData = new uint8_t[64];
603
604 ThreadContext *thread = cpu->tcBase(lsqID);
605 Tick delay;

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645
646 store_size = storeQueue[store_idx].size;
647
648 if (store_size == 0)
649 continue;
650 else if (storeQueue[store_idx].inst->uncacheable())
651 continue;
652
654 assert(storeQueue[store_idx].inst->effAddrValid);
653 assert(storeQueue[store_idx].inst->effAddrValid());
655
656 // Check if the store data is within the lower and upper bounds of
657 // addresses that the request needs.
658 bool store_has_lower_limit =
659 req->getVaddr() >= storeQueue[store_idx].inst->effAddr;
660 bool store_has_upper_limit =
661 (req->getVaddr() + req->getSize()) <=
662 (storeQueue[store_idx].inst->effAddr + store_size);

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655 // Check if the store data is within the lower and upper bounds of
656 // addresses that the request needs.
657 bool store_has_lower_limit =
658 req->getVaddr() >= storeQueue[store_idx].inst->effAddr;
659 bool store_has_upper_limit =
660 (req->getVaddr() + req->getSize()) <=
661 (storeQueue[store_idx].inst->effAddr + store_size);

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