lsq_unit.hh (8922:17f037ad8918) lsq_unit.hh (8949:3fa1ee293096)
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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600 }
601
602 if (req->isMmappedIpr()) {
603 assert(!load_inst->memData);
604 load_inst->memData = new uint8_t[64];
605
606 ThreadContext *thread = cpu->tcBase(lsqID);
607 Tick delay;
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 591 unchanged lines hidden (view full) ---

600 }
601
602 if (req->isMmappedIpr()) {
603 assert(!load_inst->memData);
604 load_inst->memData = new uint8_t[64];
605
606 ThreadContext *thread = cpu->tcBase(lsqID);
607 Tick delay;
608 PacketPtr data_pkt =
609 new Packet(req, MemCmd::ReadReq, Packet::Broadcast);
608 PacketPtr data_pkt = new Packet(req, MemCmd::ReadReq);
610
611 if (!TheISA::HasUnalignedMemAcc || !sreqLow) {
612 data_pkt->dataStatic(load_inst->memData);
613 delay = TheISA::handleIprRead(thread, data_pkt);
614 } else {
615 assert(sreqLow->isMmappedIpr() && sreqHigh->isMmappedIpr());
609
610 if (!TheISA::HasUnalignedMemAcc || !sreqLow) {
611 data_pkt->dataStatic(load_inst->memData);
612 delay = TheISA::handleIprRead(thread, data_pkt);
613 } else {
614 assert(sreqLow->isMmappedIpr() && sreqHigh->isMmappedIpr());
616 PacketPtr fst_data_pkt =
617 new Packet(sreqLow, MemCmd::ReadReq, Packet::Broadcast);
618 PacketPtr snd_data_pkt =
619 new Packet(sreqHigh, MemCmd::ReadReq, Packet::Broadcast);
615 PacketPtr fst_data_pkt = new Packet(sreqLow, MemCmd::ReadReq);
616 PacketPtr snd_data_pkt = new Packet(sreqHigh, MemCmd::ReadReq);
620
621 fst_data_pkt->dataStatic(load_inst->memData);
622 snd_data_pkt->dataStatic(load_inst->memData + sreqLow->getSize());
623
624 delay = TheISA::handleIprRead(thread, fst_data_pkt);
625 unsigned delay2 = TheISA::handleIprRead(thread, snd_data_pkt);
626 if (delay2 > delay)
627 delay = delay2;

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684
685 memcpy(load_inst->memData,
686 storeQueue[store_idx].data + shift_amt, req->getSize());
687
688 DPRINTF(LSQUnit, "Forwarding from store idx %i to load to "
689 "addr %#x, data %#x\n",
690 store_idx, req->getVaddr(), data);
691
617
618 fst_data_pkt->dataStatic(load_inst->memData);
619 snd_data_pkt->dataStatic(load_inst->memData + sreqLow->getSize());
620
621 delay = TheISA::handleIprRead(thread, fst_data_pkt);
622 unsigned delay2 = TheISA::handleIprRead(thread, snd_data_pkt);
623 if (delay2 > delay)
624 delay = delay2;

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681
682 memcpy(load_inst->memData,
683 storeQueue[store_idx].data + shift_amt, req->getSize());
684
685 DPRINTF(LSQUnit, "Forwarding from store idx %i to load to "
686 "addr %#x, data %#x\n",
687 store_idx, req->getVaddr(), data);
688
692 PacketPtr data_pkt = new Packet(req, MemCmd::ReadReq,
693 Packet::Broadcast);
689 PacketPtr data_pkt = new Packet(req, MemCmd::ReadReq);
694 data_pkt->dataStatic(load_inst->memData);
695
696 WritebackEvent *wb = new WritebackEvent(load_inst, data_pkt, this);
697
698 // We'll say this has a 1 cycle load-store forwarding latency
699 // for now.
700 // @todo: Need to make this a parameter.
701 cpu->schedule(wb, curTick());

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767
768 ++usedPorts;
769
770 // if we the cache is not blocked, do cache access
771 bool completedFirst = false;
772 if (!lsq->cacheBlocked()) {
773 MemCmd command =
774 req->isLLSC() ? MemCmd::LoadLockedReq : MemCmd::ReadReq;
690 data_pkt->dataStatic(load_inst->memData);
691
692 WritebackEvent *wb = new WritebackEvent(load_inst, data_pkt, this);
693
694 // We'll say this has a 1 cycle load-store forwarding latency
695 // for now.
696 // @todo: Need to make this a parameter.
697 cpu->schedule(wb, curTick());

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763
764 ++usedPorts;
765
766 // if we the cache is not blocked, do cache access
767 bool completedFirst = false;
768 if (!lsq->cacheBlocked()) {
769 MemCmd command =
770 req->isLLSC() ? MemCmd::LoadLockedReq : MemCmd::ReadReq;
775 PacketPtr data_pkt = new Packet(req, command, Packet::Broadcast);
771 PacketPtr data_pkt = new Packet(req, command);
776 PacketPtr fst_data_pkt = NULL;
777 PacketPtr snd_data_pkt = NULL;
778
779 data_pkt->dataStatic(load_inst->memData);
780
781 LSQSenderState *state = new LSQSenderState;
782 state->isLoad = true;
783 state->idx = load_idx;
784 state->inst = load_inst;
785 data_pkt->senderState = state;
786
787 if (!TheISA::HasUnalignedMemAcc || !sreqLow) {
788
789 // Point the first packet at the main data packet.
790 fst_data_pkt = data_pkt;
791 } else {
792
793 // Create the split packets.
772 PacketPtr fst_data_pkt = NULL;
773 PacketPtr snd_data_pkt = NULL;
774
775 data_pkt->dataStatic(load_inst->memData);
776
777 LSQSenderState *state = new LSQSenderState;
778 state->isLoad = true;
779 state->idx = load_idx;
780 state->inst = load_inst;
781 data_pkt->senderState = state;
782
783 if (!TheISA::HasUnalignedMemAcc || !sreqLow) {
784
785 // Point the first packet at the main data packet.
786 fst_data_pkt = data_pkt;
787 } else {
788
789 // Create the split packets.
794 fst_data_pkt = new Packet(sreqLow, command, Packet::Broadcast);
795 snd_data_pkt = new Packet(sreqHigh, command, Packet::Broadcast);
790 fst_data_pkt = new Packet(sreqLow, command);
791 snd_data_pkt = new Packet(sreqHigh, command);
796
797 fst_data_pkt->dataStatic(load_inst->memData);
798 snd_data_pkt->dataStatic(load_inst->memData + sreqLow->getSize());
799
800 fst_data_pkt->senderState = state;
801 snd_data_pkt->senderState = state;
802
803 state->isSplit = true;

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793 fst_data_pkt->dataStatic(load_inst->memData);
794 snd_data_pkt->dataStatic(load_inst->memData + sreqLow->getSize());
795
796 fst_data_pkt->senderState = state;
797 snd_data_pkt->senderState = state;
798
799 state->isSplit = true;

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