lsq_unit.hh (8545:a3992291e230) lsq_unit.hh (8591:8f23aeaf6a91)
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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33#define __CPU_O3_LSQ_UNIT_HH__
34
35#include <algorithm>
36#include <cstring>
37#include <map>
38#include <queue>
39
40#include "arch/faults.hh"
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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33#define __CPU_O3_LSQ_UNIT_HH__
34
35#include <algorithm>
36#include <cstring>
37#include <map>
38#include <queue>
39
40#include "arch/faults.hh"
41#include "arch/generic/debugfaults.hh"
41#include "arch/isa_traits.hh"
42#include "arch/locked_mem.hh"
43#include "arch/mmapped_ipr.hh"
44#include "base/fast_alloc.hh"
45#include "base/hashmap.hh"
46#include "config/full_system.hh"
47#include "config/the_isa.hh"
48#include "cpu/inst_seq.hh"

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563 // Must delete request now that it wasn't handed off to
564 // memory. This is quite ugly. @todo: Figure out the proper
565 // place to really handle request deletes.
566 delete req;
567 if (TheISA::HasUnalignedMemAcc && sreqLow) {
568 delete sreqLow;
569 delete sreqHigh;
570 }
42#include "arch/isa_traits.hh"
43#include "arch/locked_mem.hh"
44#include "arch/mmapped_ipr.hh"
45#include "base/fast_alloc.hh"
46#include "base/hashmap.hh"
47#include "config/full_system.hh"
48#include "config/the_isa.hh"
49#include "cpu/inst_seq.hh"

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564 // Must delete request now that it wasn't handed off to
565 // memory. This is quite ugly. @todo: Figure out the proper
566 // place to really handle request deletes.
567 delete req;
568 if (TheISA::HasUnalignedMemAcc && sreqLow) {
569 delete sreqLow;
570 delete sreqHigh;
571 }
571 return TheISA::genMachineCheckFault();
572 return new GenericISA::M5PanicFault(
573 "Uncachable load [sn:%llx] PC %s\n",
574 load_inst->seqNum, load_inst->pcState());
572 }
573
574 // Check the SQ for any previous stores that might lead to forwarding
575 int store_idx = load_inst->sqIdx;
576
577 int store_size = 0;
578
579 DPRINTF(LSQUnit, "Read called, load idx: %i, store idx: %i, "

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576
577 // Check the SQ for any previous stores that might lead to forwarding
578 int store_idx = load_inst->sqIdx;
579
580 int store_size = 0;
581
582 DPRINTF(LSQUnit, "Read called, load idx: %i, store idx: %i, "

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