lsq_unit.hh (8316:6fd588813142) lsq_unit.hh (8481:818aea9960f5)
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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34
35#include <algorithm>
36#include <cstring>
37#include <map>
38#include <queue>
39
40#include "arch/faults.hh"
41#include "arch/locked_mem.hh"
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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34
35#include <algorithm>
36#include <cstring>
37#include <map>
38#include <queue>
39
40#include "arch/faults.hh"
41#include "arch/locked_mem.hh"
42#include "arch/mmapped_ipr.hh"
42#include "base/fast_alloc.hh"
43#include "base/hashmap.hh"
44#include "config/full_system.hh"
45#include "config/the_isa.hh"
46#include "cpu/inst_seq.hh"
47#include "cpu/timebuf.hh"
48#include "debug/LSQUnit.hh"
49#include "mem/packet.hh"

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573 // Disable recording the result temporarily. Writing to misc
574 // regs normally updates the result, but this is not the
575 // desired behavior when handling store conditionals.
576 load_inst->recordResult = false;
577 TheISA::handleLockedRead(load_inst.get(), req);
578 load_inst->recordResult = true;
579 }
580
43#include "base/fast_alloc.hh"
44#include "base/hashmap.hh"
45#include "config/full_system.hh"
46#include "config/the_isa.hh"
47#include "cpu/inst_seq.hh"
48#include "cpu/timebuf.hh"
49#include "debug/LSQUnit.hh"
50#include "mem/packet.hh"

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574 // Disable recording the result temporarily. Writing to misc
575 // regs normally updates the result, but this is not the
576 // desired behavior when handling store conditionals.
577 load_inst->recordResult = false;
578 TheISA::handleLockedRead(load_inst.get(), req);
579 load_inst->recordResult = true;
580 }
581
582 if (req->isMmappedIpr()) {
583 assert(!load_inst->memData);
584 load_inst->memData = new uint8_t[64];
585
586 ThreadContext *thread = cpu->tcBase(lsqID);
587 Tick delay;
588 PacketPtr data_pkt =
589 new Packet(req, MemCmd::ReadReq, Packet::Broadcast);
590
591 if (!TheISA::HasUnalignedMemAcc || !sreqLow) {
592 data_pkt->dataStatic(load_inst->memData);
593 delay = TheISA::handleIprRead(thread, data_pkt);
594 } else {
595 assert(sreqLow->isMmappedIpr() && sreqHigh->isMmappedIpr());
596 PacketPtr fst_data_pkt =
597 new Packet(sreqLow, MemCmd::ReadReq, Packet::Broadcast);
598 PacketPtr snd_data_pkt =
599 new Packet(sreqHigh, MemCmd::ReadReq, Packet::Broadcast);
600
601 fst_data_pkt->dataStatic(load_inst->memData);
602 snd_data_pkt->dataStatic(load_inst->memData + sreqLow->getSize());
603
604 delay = TheISA::handleIprRead(thread, fst_data_pkt);
605 unsigned delay2 = TheISA::handleIprRead(thread, snd_data_pkt);
606 if (delay2 > delay)
607 delay = delay2;
608
609 delete sreqLow;
610 delete sreqHigh;
611 delete fst_data_pkt;
612 delete snd_data_pkt;
613 }
614 WritebackEvent *wb = new WritebackEvent(load_inst, data_pkt, this);
615 cpu->schedule(wb, curTick() + delay);
616 return NoFault;
617 }
618
581 while (store_idx != -1) {
582 // End once we've reached the top of the LSQ
583 if (store_idx == storeWBIdx) {
584 break;
585 }
586
587 // Move the index to one younger
588 if (--store_idx < 0)

--- 274 unchanged lines hidden --- 		619 while (store_idx != -1) {
620 // End once we've reached the top of the LSQ
621 if (store_idx == storeWBIdx) {
622 break;
623 }
624
625 // Move the index to one younger
626 if (--store_idx < 0)

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