lsq_unit.hh (7786:bafa8a197088) lsq_unit.hh (7823:dac01f14f20f)
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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619 Packet::Broadcast);
620 data_pkt->dataStatic(load_inst->memData);
621
622 WritebackEvent *wb = new WritebackEvent(load_inst, data_pkt, this);
623
624 // We'll say this has a 1 cycle load-store forwarding latency
625 // for now.
626 // @todo: Need to make this a parameter.
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 610 unchanged lines hidden (view full) ---

619 Packet::Broadcast);
620 data_pkt->dataStatic(load_inst->memData);
621
622 WritebackEvent *wb = new WritebackEvent(load_inst, data_pkt, this);
623
624 // We'll say this has a 1 cycle load-store forwarding latency
625 // for now.
626 // @todo: Need to make this a parameter.
627 cpu->schedule(wb, curTick);
627 cpu->schedule(wb, curTick());
628
629 // Don't need to do anything special for split loads.
630 if (TheISA::HasUnalignedMemAcc && sreqLow) {
631 delete sreqLow;
632 delete sreqHigh;
633 }
634
635 ++lsqForwLoads;

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629 // Don't need to do anything special for split loads.
630 if (TheISA::HasUnalignedMemAcc && sreqLow) {
631 delete sreqLow;
632 delete sreqHigh;
633 }
634
635 ++lsqForwLoads;

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