lsq_unit.hh (7720:65d338a8dba4) lsq_unit.hh (7786:bafa8a197088)
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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58 * part of a load's data) that requires the load to wait until the
59 * store writes back. In the former case it holds onto the instruction
60 * until the dependence unit looks at it, and in the latter it stalls
61 * the LSQ until the store writes back. At that point the load is
62 * replayed.
63 */
64template <class Impl>
65class LSQUnit {
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 49 unchanged lines hidden (view full) ---

58 * part of a load's data) that requires the load to wait until the
59 * store writes back. In the former case it holds onto the instruction
60 * until the dependence unit looks at it, and in the latter it stalls
61 * the LSQ until the store writes back. At that point the load is
62 * replayed.
63 */
64template <class Impl>
65class LSQUnit {
66 protected:
67 typedef TheISA::IntReg IntReg;
68 public:
69 typedef typename Impl::O3CPU O3CPU;
70 typedef typename Impl::DynInstPtr DynInstPtr;
71 typedef typename Impl::CPUPol::IEW IEW;
72 typedef typename Impl::CPUPol::LSQ LSQ;
73 typedef typename Impl::CPUPol::IssueStruct IssueStruct;
74
75 public:

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333 /** The request for the store. */
334 RequestPtr req;
335 /** The split requests for the store. */
336 RequestPtr sreqLow;
337 RequestPtr sreqHigh;
338 /** The size of the store. */
339 int size;
340 /** The store data. */
66 public:
67 typedef typename Impl::O3CPU O3CPU;
68 typedef typename Impl::DynInstPtr DynInstPtr;
69 typedef typename Impl::CPUPol::IEW IEW;
70 typedef typename Impl::CPUPol::LSQ LSQ;
71 typedef typename Impl::CPUPol::IssueStruct IssueStruct;
72
73 public:

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331 /** The request for the store. */
332 RequestPtr req;
333 /** The split requests for the store. */
334 RequestPtr sreqLow;
335 RequestPtr sreqHigh;
336 /** The size of the store. */
337 int size;
338 /** The store data. */
341 char data[sizeof(IntReg)];
339 char data[16];
342 /** Whether or not the store is split into two requests. */
343 bool isSplit;
344 /** Whether or not the store can writeback. */
345 bool canWB;
346 /** Whether or not the store is committed. */
347 bool committed;
348 /** Whether or not the store is completed. */
349 bool completed;

--- 494 unchanged lines hidden --- 		340 /** Whether or not the store is split into two requests. */
341 bool isSplit;
342 /** Whether or not the store can writeback. */
343 bool canWB;
344 /** Whether or not the store is committed. */
345 bool committed;
346 /** Whether or not the store is completed. */
347 bool completed;

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