lsq_unit.hh (7598:c0ae58952ed0) lsq_unit.hh (7720:65d338a8dba4)
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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525 // Make sure this isn't an uncacheable access
526 // A bit of a hackish way to get uncached accesses to work only if they're
527 // at the head of the LSQ and are ready to commit (at the head of the ROB
528 // too).
529 if (req->isUncacheable() &&
530 (load_idx != loadHead || !load_inst->isAtCommit())) {
531 iewStage->rescheduleMemInst(load_inst);
532 ++lsqRescheduledLoads;
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 516 unchanged lines hidden (view full) ---

525 // Make sure this isn't an uncacheable access
526 // A bit of a hackish way to get uncached accesses to work only if they're
527 // at the head of the LSQ and are ready to commit (at the head of the ROB
528 // too).
529 if (req->isUncacheable() &&
530 (load_idx != loadHead || !load_inst->isAtCommit())) {
531 iewStage->rescheduleMemInst(load_inst);
532 ++lsqRescheduledLoads;
533 DPRINTF(LSQUnit, "Uncachable load [sn:%lli] PC %#x\n",
534 load_inst->seqNum, load_inst->readPC());
533 DPRINTF(LSQUnit, "Uncachable load [sn:%lli] PC %s\n",
534 load_inst->seqNum, load_inst->pcState());
535
536 // Must delete request now that it wasn't handed off to
537 // memory. This is quite ugly. @todo: Figure out the proper
538 // place to really handle request deletes.
539 delete req;
540 if (TheISA::HasUnalignedMemAcc && sreqLow) {
541 delete sreqLow;
542 delete sreqHigh;

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682 delete sreqHigh;
683 }
684
685 return NoFault;
686 }
687 }
688
689 // If there's no forwarding case, then go access memory
535
536 // Must delete request now that it wasn't handed off to
537 // memory. This is quite ugly. @todo: Figure out the proper
538 // place to really handle request deletes.
539 delete req;
540 if (TheISA::HasUnalignedMemAcc && sreqLow) {
541 delete sreqLow;
542 delete sreqHigh;

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682 delete sreqHigh;
683 }
684
685 return NoFault;
686 }
687 }
688
689 // If there's no forwarding case, then go access memory
690 DPRINTF(LSQUnit, "Doing memory access for inst [sn:%lli] PC %#x\n",
691 load_inst->seqNum, load_inst->readPC());
690 DPRINTF(LSQUnit, "Doing memory access for inst [sn:%lli] PC %s\n",
691 load_inst->seqNum, load_inst->pcState());
692
693 assert(!load_inst->memData);
694 load_inst->memData = new uint8_t[64];
695
696 ++usedPorts;
697
698 // if we the cache is not blocked, do cache access
699 bool completedFirst = false;

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693 assert(!load_inst->memData);
694 load_inst->memData = new uint8_t[64];
695
696 ++usedPorts;
697
698 // if we the cache is not blocked, do cache access
699 bool completedFirst = false;

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