lsq_unit.hh (5999:3cf8e71257e0) | lsq_unit.hh (6076:e141cc7896ce) |
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1/* 2 * Copyright (c) 2004-2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 500 unchanged lines hidden (view full) --- 509 int store_idx = load_inst->sqIdx; 510 511 int store_size = 0; 512 513 DPRINTF(LSQUnit, "Read called, load idx: %i, store idx: %i, " 514 "storeHead: %i addr: %#x\n", 515 load_idx, store_idx, storeHead, req->getPaddr()); 516 | 1/* 2 * Copyright (c) 2004-2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 500 unchanged lines hidden (view full) --- 509 int store_idx = load_inst->sqIdx; 510 511 int store_size = 0; 512 513 DPRINTF(LSQUnit, "Read called, load idx: %i, store idx: %i, " 514 "storeHead: %i addr: %#x\n", 515 load_idx, store_idx, storeHead, req->getPaddr()); 516 |
517 if (req->isLocked()) { | 517 if (req->isLlsc()) { |
518 // Disable recording the result temporarily. Writing to misc 519 // regs normally updates the result, but this is not the 520 // desired behavior when handling store conditionals. 521 load_inst->recordResult = false; 522 TheISA::handleLockedRead(load_inst.get(), req); 523 load_inst->recordResult = true; 524 } 525 --- 116 unchanged lines hidden (view full) --- 642 load_inst->memData = new uint8_t[64]; 643 644 ++usedPorts; 645 646 // if we the cache is not blocked, do cache access 647 if (!lsq->cacheBlocked()) { 648 PacketPtr data_pkt = 649 new Packet(req, | 518 // Disable recording the result temporarily. Writing to misc 519 // regs normally updates the result, but this is not the 520 // desired behavior when handling store conditionals. 521 load_inst->recordResult = false; 522 TheISA::handleLockedRead(load_inst.get(), req); 523 load_inst->recordResult = true; 524 } 525 --- 116 unchanged lines hidden (view full) --- 642 load_inst->memData = new uint8_t[64]; 643 644 ++usedPorts; 645 646 // if we the cache is not blocked, do cache access 647 if (!lsq->cacheBlocked()) { 648 PacketPtr data_pkt = 649 new Packet(req, |
650 (req->isLocked() ? | 650 (req->isLlsc() ? |
651 MemCmd::LoadLockedReq : MemCmd::ReadReq), 652 Packet::Broadcast); 653 data_pkt->dataStatic(load_inst->memData); 654 655 LSQSenderState *state = new LSQSenderState; 656 state->isLoad = true; 657 state->idx = load_idx; 658 state->inst = load_inst; --- 68 unchanged lines hidden --- | 651 MemCmd::LoadLockedReq : MemCmd::ReadReq), 652 Packet::Broadcast); 653 data_pkt->dataStatic(load_inst->memData); 654 655 LSQSenderState *state = new LSQSenderState; 656 state->isLoad = true; 657 state->idx = load_idx; 658 state->inst = load_inst; --- 68 unchanged lines hidden --- |