lsq_unit.hh (5606:6da7a58b0bc8) lsq_unit.hh (5999:3cf8e71257e0)
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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404
405 /** The oldest load that caused a memory ordering violation. */
406 DynInstPtr memDepViolator;
407
408 // Will also need how many read/write ports the Dcache has. Or keep track
409 // of that in stage that is one level up, and only call executeLoad/Store
410 // the appropriate number of times.
411 /** Total number of loads forwaded from LSQ stores. */
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 395 unchanged lines hidden (view full) ---

404
405 /** The oldest load that caused a memory ordering violation. */
406 DynInstPtr memDepViolator;
407
408 // Will also need how many read/write ports the Dcache has. Or keep track
409 // of that in stage that is one level up, and only call executeLoad/Store
410 // the appropriate number of times.
411 /** Total number of loads forwaded from LSQ stores. */
412 Stats::Scalar<> lsqForwLoads;
412 Stats::Scalar lsqForwLoads;
413
414 /** Total number of loads ignored due to invalid addresses. */
413
414 /** Total number of loads ignored due to invalid addresses. */
415 Stats::Scalar<> invAddrLoads;
415 Stats::Scalar invAddrLoads;
416
417 /** Total number of squashed loads. */
416
417 /** Total number of squashed loads. */
418 Stats::Scalar<> lsqSquashedLoads;
418 Stats::Scalar lsqSquashedLoads;
419
420 /** Total number of responses from the memory system that are
421 * ignored due to the instruction already being squashed. */
419
420 /** Total number of responses from the memory system that are
421 * ignored due to the instruction already being squashed. */
422 Stats::Scalar<> lsqIgnoredResponses;
422 Stats::Scalar lsqIgnoredResponses;
423
424 /** Tota number of memory ordering violations. */
423
424 /** Tota number of memory ordering violations. */
425 Stats::Scalar<> lsqMemOrderViolation;
425 Stats::Scalar lsqMemOrderViolation;
426
427 /** Total number of squashed stores. */
426
427 /** Total number of squashed stores. */
428 Stats::Scalar<> lsqSquashedStores;
428 Stats::Scalar lsqSquashedStores;
429
430 /** Total number of software prefetches ignored due to invalid addresses. */
429
430 /** Total number of software prefetches ignored due to invalid addresses. */
431 Stats::Scalar<> invAddrSwpfs;
431 Stats::Scalar invAddrSwpfs;
432
433 /** Ready loads blocked due to partial store-forwarding. */
432
433 /** Ready loads blocked due to partial store-forwarding. */
434 Stats::Scalar<> lsqBlockedLoads;
434 Stats::Scalar lsqBlockedLoads;
435
436 /** Number of loads that were rescheduled. */
435
436 /** Number of loads that were rescheduled. */
437 Stats::Scalar<> lsqRescheduledLoads;
437 Stats::Scalar lsqRescheduledLoads;
438
439 /** Number of times the LSQ is blocked due to the cache. */
438
439 /** Number of times the LSQ is blocked due to the cache. */
440 Stats::Scalar<> lsqCacheBlocked;
440 Stats::Scalar lsqCacheBlocked;
441
442 public:
443 /** Executes the load at the given index. */
444 template <class T>
445 Fault read(Request *req, T &data, int load_idx);
446
447 /** Executes the store at the given index. */
448 template <class T>

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441
442 public:
443 /** Executes the load at the given index. */
444 template <class T>
445 Fault read(Request *req, T &data, int load_idx);
446
447 /** Executes the store at the given index. */
448 template <class T>

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