lsq_unit.hh (5386:5614618f4027) lsq_unit.hh (5529:9ae69b9cd7fd)
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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41#include "arch/locked_mem.hh"
42#include "config/full_system.hh"
43#include "base/fast_alloc.hh"
44#include "base/hashmap.hh"
45#include "cpu/inst_seq.hh"
46#include "mem/packet.hh"
47#include "mem/port.hh"
48
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 32 unchanged lines hidden (view full) ---

41#include "arch/locked_mem.hh"
42#include "config/full_system.hh"
43#include "base/fast_alloc.hh"
44#include "base/hashmap.hh"
45#include "cpu/inst_seq.hh"
46#include "mem/packet.hh"
47#include "mem/port.hh"
48
49class DerivO3CPUParams;
50
49/**
50 * Class that implements the actual LQ and SQ for each specific
51 * thread. Both are circular queues; load entries are freed upon
52 * committing, while store entries are freed once they writeback. The
53 * LSQUnit tracks if there are memory ordering violations, and also
54 * detects partial load to store forwarding cases (a store only has
55 * part of a load's data) that requires the load to wait until the
56 * store writes back. In the former case it holds onto the instruction
57 * until the dependence unit looks at it, and in the latter it stalls
58 * the LSQ until the store writes back. At that point the load is
59 * replayed.
60 */
61template <class Impl>
62class LSQUnit {
63 protected:
64 typedef TheISA::IntReg IntReg;
65 public:
51/**
52 * Class that implements the actual LQ and SQ for each specific
53 * thread. Both are circular queues; load entries are freed upon
54 * committing, while store entries are freed once they writeback. The
55 * LSQUnit tracks if there are memory ordering violations, and also
56 * detects partial load to store forwarding cases (a store only has
57 * part of a load's data) that requires the load to wait until the
58 * store writes back. In the former case it holds onto the instruction
59 * until the dependence unit looks at it, and in the latter it stalls
60 * the LSQ until the store writes back. At that point the load is
61 * replayed.
62 */
63template <class Impl>
64class LSQUnit {
65 protected:
66 typedef TheISA::IntReg IntReg;
67 public:
66 typedef typename Impl::Params Params;
67 typedef typename Impl::O3CPU O3CPU;
68 typedef typename Impl::DynInstPtr DynInstPtr;
69 typedef typename Impl::CPUPol::IEW IEW;
70 typedef typename Impl::CPUPol::LSQ LSQ;
71 typedef typename Impl::CPUPol::IssueStruct IssueStruct;
72
73 public:
74 /** Constructs an LSQ unit. init() must be called prior to use. */
75 LSQUnit();
76
77 /** Initializes the LSQ unit with the specified number of entries. */
68 typedef typename Impl::O3CPU O3CPU;
69 typedef typename Impl::DynInstPtr DynInstPtr;
70 typedef typename Impl::CPUPol::IEW IEW;
71 typedef typename Impl::CPUPol::LSQ LSQ;
72 typedef typename Impl::CPUPol::IssueStruct IssueStruct;
73
74 public:
75 /** Constructs an LSQ unit. init() must be called prior to use. */
76 LSQUnit();
77
78 /** Initializes the LSQ unit with the specified number of entries. */
78 void init(O3CPU *cpu_ptr, IEW *iew_ptr, Params *params, LSQ *lsq_ptr,
79 unsigned maxLQEntries, unsigned maxSQEntries, unsigned id);
79 void init(O3CPU *cpu_ptr, IEW *iew_ptr, DerivO3CPUParams *params,
80 LSQ *lsq_ptr, unsigned maxLQEntries, unsigned maxSQEntries,
81 unsigned id);
80
81 /** Returns the name of the LSQ unit. */
82 std::string name() const;
83
84 /** Registers statistics. */
85 void regStats();
86
87 /** Sets the pointer to the dcache port. */

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83 /** Returns the name of the LSQ unit. */
84 std::string name() const;
85
86 /** Registers statistics. */
87 void regStats();
88
89 /** Sets the pointer to the dcache port. */

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